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mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28

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Infineon(Cypress) S28Hx-T family does not support legacy CLSR(0x30) opcode.
Instead, it supports CLPEF(0x82) which has the same functionality as CLSR.
spansion_sr_ready() is for multi-die package parts including S28HS02GT, so
we need to use CLPEF instead of CLSR.

This change does not affect to S25x02GT which uses spansion_sr_ready() as
S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30).

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Takahiro Kuwano
2023-12-22 14:46:01 +09:00
committed by Jagan Teki
parent 9768d7c7ec
commit 9901312e09
2 changed files with 2 additions and 1 deletions
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2
drivers/mtd/spi/spi-nor-core.c
View File

@@ -752,7 +752,7 @@ static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy)
else
dev_dbg(nor->dev, "Programming Error occurred\n");
nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
nor->write_reg(nor, SPINOR_OP_CYPRESS_CLPEF, NULL, 0);
return -EIO;
}

1
include/linux/mtd/spi-nor.h
View File

@@ -180,6 +180,7 @@
/* For Cypress flash. */
#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
#define SPINOR_OP_CYPRESS_CLPEF 0x82 /* Clear P/E err flag */
#define SPINOR_REG_CYPRESS_ARCFN 0x00000006
#define SPINOR_REG_CYPRESS_STR1V 0x00800000
#define SPINOR_REG_CYPRESS_CFR1V 0x00800002