From fdda7901cc77b5bc525263c385cc19f151b6612b Mon Sep 17 00:00:00 2001 From: Haolin Li Date: Tue, 22 Mar 2022 05:58:02 -0700 Subject: [PATCH 01/48] mmc: rockchip_sdhci: Correct error checking A pointer can not be negative. Use macro IS_ERR_OR_NULL() for checking. Signed-off-by: Haolin Li Reviewed-by: Simon Glass Reviewed-by: Kever Yang Reviewed-by: Jaehoon Chung --- drivers/mmc/rockchip_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 1fdc8415178..9608770d4ec 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -227,7 +227,7 @@ static int rk3399_emmc_get_phy(struct udevice *dev) } grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - if (grf_base < 0) { + if (IS_ERR_OR_NULL(grf_base)) { printf("%s Get syscon grf failed", __func__); return -ENODEV; } From e963228af50d317a83d4ceffb095e40ef3ab9d53 Mon Sep 17 00:00:00 2001 From: Peter Cai Date: Fri, 4 Feb 2022 15:16:06 -0500 Subject: [PATCH 02/48] adc: rockchip-saradc: add support for getting reference voltage value Mirroring commit 97ab802aa36f ("adc: meson-saradc: add support for getting reference voltage value") for meson-saradc, this adds support for getting the "vref-supply" regulator and register it as the ADC's reference voltage regulator, so clients can translate sampled ADC values to voltage. Signed-off-by: Peter Cai Reviewed-by: John Keeping Tested-by: John Keeping Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- drivers/adc/rockchip-saradc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index e0cbab6aa06..760f8fe6280 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -13,6 +13,7 @@ #include #include #include +#include #define SARADC_CTRL_CHN_MASK GENMASK(2, 0) #define SARADC_CTRL_POWER_CTRL BIT(3) @@ -100,8 +101,11 @@ int rockchip_saradc_stop(struct udevice *dev) int rockchip_saradc_probe(struct udevice *dev) { + struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); struct rockchip_saradc_priv *priv = dev_get_priv(dev); + struct udevice *vref; struct clk clk; + int vref_uv; int ret; ret = clk_get_by_index(dev, 0, &clk); @@ -114,6 +118,23 @@ int rockchip_saradc_probe(struct udevice *dev) priv->active_channel = -1; + ret = device_get_supply_regulator(dev, "vref-supply", &vref); + if (ret) { + printf("can't get vref-supply: %d\n", ret); + return ret; + } + + vref_uv = regulator_get_value(vref); + if (vref_uv < 0) { + printf("can't get vref-supply value: %d\n", vref_uv); + return vref_uv; + } + + /* VDD supplied by common vref pin */ + uc_pdata->vdd_supply = vref; + uc_pdata->vdd_microvolts = vref_uv; + uc_pdata->vss_microvolts = 0; + return 0; } From f0d49d4f0dba4bd3dc4810dbfc48e315afe023fc Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 25 Mar 2022 10:40:35 -0500 Subject: [PATCH 03/48] spi: rockchip_sfc: Add missing include for dm/device_compat.h Add missing include for dm/device_compat.h. Without this include the SFC driver fails to compile because dev_err and dev_dbg are not defined. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- drivers/spi/rockchip_sfc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c index e098addddca..851a6482985 100644 --- a/drivers/spi/rockchip_sfc.c +++ b/drivers/spi/rockchip_sfc.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include From 0abb5b0426e5c20bdbb5748196569a2b5533d711 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 25 Mar 2022 12:09:22 -0500 Subject: [PATCH 04/48] rockchip: clk: add clocks to px30_clk_enable Add the HCLK_OTG, HCLK_SFC, and SCLK_SFC clocks to px30_clk_enable. Without this change U-Boot reports an error of "Enable clock-controller@ff2b0000 failed" on boot when using the SFC or USB in U-Boot. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_px30.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index ea874e3f4b9..5d467447a17 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -1403,10 +1403,13 @@ static int px30_clk_enable(struct clk *clk) { switch (clk->id) { case HCLK_HOST: + case HCLK_OTG: + case HCLK_SFC: case SCLK_GMAC: case SCLK_GMAC_RX_TX: case SCLK_MAC_REF: case SCLK_MAC_REFOUT: + case SCLK_SFC: case ACLK_GMAC: case PCLK_GMAC: case SCLK_GMAC_RMII: From 48cd7a1f6ccb7d971460e95a2b6c053d6e2a28d1 Mon Sep 17 00:00:00 2001 From: Vagrant Cascadian Date: Wed, 6 Apr 2022 13:42:03 -0700 Subject: [PATCH 05/48] rockchip: Enable SCSI in distro bootcmd for rk3399. Include SCSI in the list of boot targets if CONFIG_CMD_SCSI is enabled. Signed-off-by: Vagrant Cascadian Reviewed-by: Kever Yang --- include/configs/rockchip-common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index ba7061a287c..0c08776ae26 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -29,6 +29,12 @@ #define BOOT_TARGET_NVME(func) #endif +#if CONFIG_IS_ENABLED(CMD_SCSI) + #define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0) +#else + #define BOOT_TARGET_SCSI(func) +#endif + #if CONFIG_IS_ENABLED(CMD_USB) #define BOOT_TARGET_USB(func) func(USB, usb, 0) #else @@ -57,6 +63,7 @@ #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC(func) \ BOOT_TARGET_NVME(func) \ + BOOT_TARGET_SCSI(func) \ BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) \ BOOT_TARGET_DHCP(func) \ From 60be6e0860e3f7ea644c70f3342861be7cef8b8f Mon Sep 17 00:00:00 2001 From: Vagrant Cascadian Date: Wed, 6 Apr 2022 13:42:04 -0700 Subject: [PATCH 06/48] rockchip: Enable AHCI/SCSI/SATA on rockpro64-rk3399. Add options to enable AHCI, SCSI and SATA. Signed-off-by: Vagrant Cascadian Reviewed-by: Kever Yang --- configs/rockpro64-rk3399_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index dc9f5f2ac66..f44d15ebec9 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -28,6 +28,13 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SATA=y +CONFIG_SATA_SIL=y +CONFIG_SCSI=y +CONFIG_SCSI_AHCI=y +CONFIG_DM_SCSI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y From 54562045e5937e724ae574f02bdb040338d258be Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:02 +0200 Subject: [PATCH 07/48] rockchip: move ROCKCHIP_STIMER_BASE to Kconfig Move ROCKCHIP_STIMER_BASE to Kconfig. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 10 ++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3036/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3128/Kconfig | 3 +++ arch/arm/mach-rockchip/rk322x/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3308/Kconfig | 10 ++++++---- arch/arm/mach-rockchip/rk3328/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3399/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3568/Kconfig | 3 +++ configs/rock_defconfig | 1 + include/configs/px30_common.h | 1 - include/configs/rk3036_common.h | 1 - include/configs/rk3128_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3308_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/rk3368_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/rk3568_common.h | 1 - 22 files changed, 44 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 308dc09b038..811964973ae 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -339,6 +339,16 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. +config ROCKCHIP_STIMER + bool "Rockchip STIMER support" + default y + help + Enable Rockchip STIMER support. + +config ROCKCHIP_STIMER_BASE + hex + depends on ROCKCHIP_STIMER + config ROCKCHIP_SPL_RESERVE_IRAM hex "Size of IRAM reserved in SPL" default 0 diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 145bf3591ff..4886fe946e3 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -38,6 +38,9 @@ config TARGET_PX30_CORE config ROCKCHIP_BOOT_MODE_REG default 0xff010200 +config ROCKCHIP_STIMER_BASE + default 0xff220020 + config SYS_SOC default "px30" diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index b746795d813..111531be1ef 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x200081c8 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3036" diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig index b867401c7f5..9cc494eb409 100644 --- a/arch/arm/mach-rockchip/rk3128/Kconfig +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x100a0038 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3128" diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 6458cd55814..058f848ddc7 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -8,6 +8,9 @@ config TARGET_EVB_RK3229 config ROCKCHIP_BOOT_MODE_REG default 0x110005c8 +config ROCKCHIP_STIMER_BASE + default 0x110d0020 + config SYS_SOC default "rk322x" diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index f37b1bdfd50..dd8c7826fc1 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -148,6 +148,9 @@ config ROCKCHIP_FAST_SPL config ROCKCHIP_BOOT_MODE_REG default 0xff730094 +config ROCKCHIP_STIMER_BASE + default 0xff810020 + config SYS_SOC default "rk3288" diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 8fa536e15dc..194353e4cd9 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -8,6 +8,12 @@ config TARGET_ROC_RK3308_CC bool "Firefly roc-rk3308-cc" select BOARD_LATE_INIT +config ROCKCHIP_BOOT_MODE_REG + default 0xff000500 + +config ROCKCHIP_STIMER_BASE + default 0xff1b00a0 + config SYS_SOC default "rk3308" @@ -17,10 +23,6 @@ config SYS_MALLOC_F_LEN config SPL_SERIAL default y -config ROCKCHIP_BOOT_MODE_REG - default 0xff000500 - - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d13a1690226..f6f1e06a83f 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -15,6 +15,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff1005c8 +config ROCKCHIP_STIMER_BASE + default 0xff1d0020 + config SYS_SOC default "rk3328" diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 78eb96df3d1..104db36737b 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -45,6 +45,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff738200 +config ROCKCHIP_STIMER_BASE + default 0xff830020 + config SYS_SOC default "rk3368" diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 0833e083d9e..c1f251316cb 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -125,6 +125,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff320300 +config ROCKCHIP_STIMER_BASE + default 0xff8680a0 + config SYS_SOC default "rk3399" diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 201c63c2a9c..4e7c02cce06 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -9,6 +9,9 @@ config TARGET_EVB_RK3568 config ROCKCHIP_BOOT_MODE_REG default 0xfdc20200 +config ROCKCHIP_STIMER_BASE + default 0xfdd1c020 + config SYS_SOC default "rk3568" diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 290f5afd787..4aa4608f904 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock" CONFIG_SPL_TEXT_BASE=0x10080800 CONFIG_ROCKCHIP_RK3188=y +# CONFIG_ROCKCHIP_STIMER is not set CONFIG_TARGET_ROCK=y CONFIG_SPL_STACK_R_ADDR=0x60080000 CONFIG_DEBUG_UART_BASE=0x20064000 diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 09923871571..dc609013f32 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020 #define COUNTER_FREQUENCY 24000000 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 00c453d739d..5905518edf1 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 97caceacfe6..d77a7d7b098 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index ef55ef0a83b..3258820fcdc 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 490da7cb23b..e2e0f70a70c 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 1664707ca65..9cda8d9c48b 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 #define CONFIG_IRAM_BASE 0xfff80000 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 #define CONFIG_SPL_STACK 0x00400000 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index c1e26a019b5..8a5f0c8999f 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -10,7 +10,6 @@ #define CONFIG_IRAM_BASE 0xff090000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 8b239ca07da..239296c1d22 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -15,7 +15,6 @@ #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index ed72c8bb6b1..4037dba58cc 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define COUNTER_FREQUENCY 24000000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 25d7c5cc8ff..5649cd64e0e 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define COUNTER_FREQUENCY 24000000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020 #define CONFIG_IRAM_BASE 0xfdcc0000 From 12a716422fa0f30ae1ce4ba27cee81a8fe890efc Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:03 +0200 Subject: [PATCH 08/48] rockchip: spl: change call condition rockchip_stimer_init() The Rockchip SoCs rk3066/rk3188 have no CONFIG_ROCKCHIP_STIMER_BASE defined. Currently only rk3188 has an exception in SPL. Make this more generic and compile code inside the function rockchip_stimer_init() only when CONFIG_ROCKCHIP_STIMER_BASE is available. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index d51a0727b47..eda2248029d 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -71,7 +71,6 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) return MMCSD_MODE_RAW; } -#if !defined(CONFIG_ROCKCHIP_RK3188) #define TIMER_LOAD_COUNT_L 0x00 #define TIMER_LOAD_COUNT_H 0x04 #define TIMER_CONTROL_REG 0x10 @@ -81,6 +80,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) __weak void rockchip_stimer_init(void) { +#if defined(CONFIG_ROCKCHIP_STIMER_BASE) /* If Timer already enabled, don't re-init it */ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); @@ -95,8 +95,8 @@ __weak void rockchip_stimer_init(void) writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); -} #endif +} __weak int board_early_init_f(void) { @@ -133,9 +133,9 @@ void board_init_f(ulong dummy) hang(); } arch_cpu_init(); -#if !defined(CONFIG_ROCKCHIP_RK3188) + rockchip_stimer_init(); -#endif + #ifdef CONFIG_SYS_ARCH_TIMER /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ timer_init(); From d23f55d21749fc1fc1147edad3b1782d479b9946 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:04 +0200 Subject: [PATCH 09/48] rockchip: tpl: change call condition rockchip_stimer_init() The Rockchip SoCs rk3066/rk3188 have no CONFIG_ROCKCHIP_STIMER_BASE defined. Currently there's no exception in TPL. Make this more generic and compile the code inside the function rockchip_stimer_init() only when CONFIG_ROCKCHIP_STIMER_BASE is available. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/tpl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 3c007bb4508..7f43f584066 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -29,6 +29,7 @@ __weak void rockchip_stimer_init(void) { +#if defined(CONFIG_ROCKCHIP_STIMER_BASE) /* If Timer already enabled, don't re-init it */ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); @@ -45,6 +46,7 @@ __weak void rockchip_stimer_init(void) writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); +#endif } void board_init_f(ulong dummy) From 30a7b824aa5a2774bf320c20f1d460aea2a56db0 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:05 +0200 Subject: [PATCH 10/48] rockchip: tpl: use IS_ENABLED for timer_init() call condition Not all Rockchip SoC models use the ARM arch timer. Call the function timer_init() only when CONFIG_SYS_ARCH_TIMER is available. Use the call condition IS_ENABLED to increase build coverage and make the code easier to read. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/tpl.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 7f43f584066..8126587060f 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -15,6 +15,7 @@ #include #include #include +#include #if CONFIG_IS_ENABLED(BANNER_PRINT) #include @@ -77,8 +78,10 @@ void board_init_f(ulong dummy) /* Init secure timer */ rockchip_stimer_init(); - /* Init ARM arch timer in arch/arm/cpu/ */ - timer_init(); + + /* Init ARM arch timer */ + if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER)) + timer_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { From 516e216a788f62d6638e69632d97bc5798d29f1c Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:06 +0200 Subject: [PATCH 11/48] rockchip: timer: add OF_PLATDATA support for dw-apb-timer The Rockchip rk3066 SoC has 3 dw-apb-timer nodes. U-boot is compiled with OF_PLATDATA TPL/SPL options, so add OF_PLATDATA support for the dw-apb-timer. Also change driver name to be able to compile with U-boot scripts. No reset OF_PLATDATA support was added, because the rk3066 nodes don't need/have them. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- drivers/timer/dw-apb-timer.c | 50 ++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 9aed5dd217a..f7226979342 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -8,10 +8,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include @@ -25,6 +27,12 @@ struct dw_apb_timer_priv { struct reset_ctl_bulk resets; }; +struct dw_apb_timer_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_snps_dw_apb_timer dtplat; +#endif +}; + static u64 dw_apb_timer_get_count(struct udevice *dev) { struct dw_apb_timer_priv *priv = dev_get_priv(dev); @@ -43,20 +51,33 @@ static int dw_apb_timer_probe(struct udevice *dev) struct dw_apb_timer_priv *priv = dev_get_priv(dev); struct clk clk; int ret; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dw_apb_timer_plat *plat = dev_get_plat(dev); + struct dtd_snps_dw_apb_timer *dtplat = &plat->dtplat; - ret = reset_get_bulk(dev, &priv->resets); - if (ret) - dev_warn(dev, "Can't get reset: %d\n", ret); - else - reset_deassert_bulk(&priv->resets); + priv->regs = dtplat->reg[0]; - ret = clk_get_by_index(dev, 0, &clk); - if (ret) + ret = clk_get_by_phandle(dev, &dtplat->clocks[0], &clk); + if (ret < 0) return ret; - uc_priv->clock_rate = clk_get_rate(&clk); + uc_priv->clock_rate = dtplat->clock_frequency; +#endif + if (CONFIG_IS_ENABLED(OF_REAL)) { + ret = reset_get_bulk(dev, &priv->resets); + if (ret) + dev_warn(dev, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&priv->resets); - clk_free(&clk); + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + uc_priv->clock_rate = clk_get_rate(&clk); + + clk_free(&clk); + } /* init timer */ writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL); @@ -68,9 +89,11 @@ static int dw_apb_timer_probe(struct udevice *dev) static int dw_apb_timer_of_to_plat(struct udevice *dev) { - struct dw_apb_timer_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct dw_apb_timer_priv *priv = dev_get_priv(dev); - priv->regs = dev_read_addr(dev); + priv->regs = dev_read_addr(dev); + } return 0; } @@ -91,8 +114,8 @@ static const struct udevice_id dw_apb_timer_ids[] = { {} }; -U_BOOT_DRIVER(dw_apb_timer) = { - .name = "dw_apb_timer", +U_BOOT_DRIVER(snps_dw_apb_timer) = { + .name = "snps_dw_apb_timer", .id = UCLASS_TIMER, .ops = &dw_apb_timer_ops, .probe = dw_apb_timer_probe, @@ -100,4 +123,5 @@ U_BOOT_DRIVER(dw_apb_timer) = { .of_to_plat = dw_apb_timer_of_to_plat, .remove = dw_apb_timer_remove, .priv_auto = sizeof(struct dw_apb_timer_priv), + .plat_auto = sizeof(struct dw_apb_timer_plat), }; From 3930209526b32d9075ee9c01e87ee50201934313 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:07 +0200 Subject: [PATCH 12/48] rockchip: timer: dw-apb-timer: fix whitespace in U_BOOT_DRIVER structure The line with .of_to_plat in the U_BOOT_DRIVER structure of dw-apb-timer.c is not aligned with the rest. Add an extra TAB to fix the whitespace. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- drivers/timer/dw-apb-timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index f7226979342..10f0a9f646e 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -120,7 +120,7 @@ U_BOOT_DRIVER(snps_dw_apb_timer) = { .ops = &dw_apb_timer_ops, .probe = dw_apb_timer_probe, .of_match = dw_apb_timer_ids, - .of_to_plat = dw_apb_timer_of_to_plat, + .of_to_plat = dw_apb_timer_of_to_plat, .remove = dw_apb_timer_remove, .priv_auto = sizeof(struct dw_apb_timer_priv), .plat_auto = sizeof(struct dw_apb_timer_plat), From 9d75dafb1bee4cdc165c3c3ca246e9bc70690a7f Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:08 +0200 Subject: [PATCH 13/48] rockchip: mmc: rockchip_dw_mmc: fix ciu clock index The document rockchip-dw-mshc.yaml decribes a maximum of 4 clocks. In the rockchip_dw_mmc driver the clock name in use was "fixed" to "ciu" with index 1, but later reverted back to index 0. The clock drivers can handle both, but the calling driver should submit correct data as a standard practice. Fix the "ciu" clock index by setting it back to 1. clock-names: minItems: 2 items: - const: biu - const: ciu - const: ciu-drive - const: ciu-sample Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/mmc/rockchip_dw_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 7f8dea1e343..be065ec0c34 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -123,11 +123,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev) priv->minmax[0] = 400000; /* 400 kHz */ priv->minmax[1] = dtplat->max_frequency; - ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); + ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk); if (ret < 0) return ret; #else - ret = clk_get_by_index(dev, 0, &priv->clk); + ret = clk_get_by_index(dev, 1, &priv->clk); if (ret < 0) return ret; #endif From 2d3bb400f37b86c3da3a64a9ee4c1d79caa2fdd6 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:09 +0200 Subject: [PATCH 14/48] rockchip: mmc: rockchip_dw_mmc: add rk3066/rk3188 support The Rockchip SoCs rk3066/rk3188 have MMC DT nodes with as compatible string "rockchip,rk2928-dw-mshc". Add OF_PLATDATA support to the existing driver with help of a DM_DRIVER_ALIAS. This type needs a permanent enabled fifo. The other Rockchip SoCs always have the property "u-boot,spl-fifo-mode" in the MMC DT nodes, because MMC to SRAM can't do DMA. Make this property a requirement for MMC OF_PLATDATA structures. The property "fifo-mode" must be added for all other compile modes. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/mmc/rockchip_dw_mmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index be065ec0c34..573bf16c875 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -119,7 +119,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) host->priv = dev; host->dev_index = 0; priv->fifo_depth = dtplat->fifo_depth; - priv->fifo_mode = 0; + priv->fifo_mode = dtplat->u_boot_spl_fifo_mode; priv->minmax[0] = 400000; /* 400 kHz */ priv->minmax[1] = dtplat->max_frequency; @@ -180,5 +180,6 @@ U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = { .plat_auto = sizeof(struct rockchip_mmc_plat), }; +DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk2928_dw_mshc) DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc) DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc) From 728489753c75888b2ffd70ad37b2b0590edc45d9 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:10 +0200 Subject: [PATCH 15/48] rockchip: serial: restyle the serial_rockchip.c driver The ns16550.c driver has the following conditions for .of_match: CONFIG_IS_ENABLED(OF_REAL) For Rockchip SoCs with TPL/SPL and platform data that need serial support the serial_rockchip.c driver was made. It copies this data and then calls ns16550_serial_probe(). With the addition of yet an other SoC type this driver is in need for a little restyle. Simplify struct rockchip_uart_plat and add extra SoCs with DM_DRIVER_ALIAS(). Return -ENODEV when the ns16550.c driver probe function is available. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- drivers/serial/serial_rockchip.c | 37 +++++++++++++------------------- 1 file changed, 15 insertions(+), 22 deletions(-) diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index 97d40869a2a..f5ac705f4de 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -12,22 +12,20 @@ #include #include -#if defined(CONFIG_ROCKCHIP_RK3188) -struct rockchip_uart_plat { - struct dtd_rockchip_rk3188_uart dtplat; - struct ns16550_plat plat; -}; -struct dtd_rockchip_rk3188_uart *dtplat, s_dtplat; -#elif defined(CONFIG_ROCKCHIP_RK3288) struct rockchip_uart_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) struct dtd_rockchip_rk3288_uart dtplat; +#endif struct ns16550_plat plat; }; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat; #endif static int rockchip_serial_probe(struct udevice *dev) { +#if CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_uart_plat *plat = dev_get_plat(dev); /* Create some new platform data for the standard driver */ @@ -38,24 +36,19 @@ static int rockchip_serial_probe(struct udevice *dev) dev_set_plat(dev, &plat->plat); return ns16550_serial_probe(dev); +#else + return -ENODEV; +#endif } -U_BOOT_DRIVER(rockchip_rk3188_uart) = { - .name = "rockchip_rk3188_uart", - .id = UCLASS_SERIAL, - .priv_auto = sizeof(struct ns16550), - .plat_auto = sizeof(struct rockchip_uart_plat), - .probe = rockchip_serial_probe, - .ops = &ns16550_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; - U_BOOT_DRIVER(rockchip_rk3288_uart) = { - .name = "rockchip_rk3288_uart", - .id = UCLASS_SERIAL, + .name = "rockchip_rk3288_uart", + .id = UCLASS_SERIAL, .priv_auto = sizeof(struct ns16550), .plat_auto = sizeof(struct rockchip_uart_plat), - .probe = rockchip_serial_probe, - .ops = &ns16550_serial_ops, - .flags = DM_FLAG_PRE_RELOC, + .probe = rockchip_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, }; +DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3066_uart) +DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3188_uart) From 04ee76c988859a586e9bc6b7f65755a5af295105 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:11 +0200 Subject: [PATCH 16/48] rockchip: serial: move driver alias to serial_rockchip.c The Rockchip uart DT nodes have "snps,dw-apb-uart" as fall back string. The driver ns16550.c has CONFIG_IS_ENABLED(OF_REAL) as condition to of_match and does not copy dtplat data. For TPL/SPL the driver serial_rockchip.c is used. Move driver alias to correct driver. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- drivers/serial/ns16550.c | 2 -- drivers/serial/serial_rockchip.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 796ff1658cd..a4220fd0ae2 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -624,8 +624,6 @@ U_BOOT_DRIVER(ns16550_serial) = { #endif }; -DM_DRIVER_ALIAS(ns16550_serial, rockchip_rk3328_uart) -DM_DRIVER_ALIAS(ns16550_serial, rockchip_rk3368_uart) DM_DRIVER_ALIAS(ns16550_serial, ti_da830_uart) #endif #endif /* SERIAL_PRESENT */ diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index f5ac705f4de..10e731caa18 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -52,3 +52,5 @@ U_BOOT_DRIVER(rockchip_rk3288_uart) = { }; DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3066_uart) DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3188_uart) +DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3328_uart) +DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3368_uart) From 6e2ee2ebb808721ab5cb4b03642a169c5ec739c7 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:12 +0200 Subject: [PATCH 17/48] rockchip: serial: rename U_BOOT_DRIVER name to rockchip_uart When a defconfig for rk3288 is compiled it gives the warning: rockchip_rk3288_uart: Missing .compatible in ./drivers/serial/serial_rockchip.c : WARNING: the driver rockchip_rk3288_uart was not found in the driver list Fix by renaming U_BOOT_DRIVER name of serial_rockchip.c to rockchip_uart. Add rk3288 serial support with a DM_DRIVER_ALIAS define. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/serial/serial_rockchip.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index 10e731caa18..f4e9422ed91 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -14,13 +14,13 @@ struct rockchip_uart_plat { #if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_rockchip_rk3288_uart dtplat; + struct dtd_rockchip_uart dtplat; #endif struct ns16550_plat plat; }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat; +struct dtd_rockchip_uart *dtplat, s_dtplat; #endif static int rockchip_serial_probe(struct udevice *dev) @@ -41,8 +41,8 @@ static int rockchip_serial_probe(struct udevice *dev) #endif } -U_BOOT_DRIVER(rockchip_rk3288_uart) = { - .name = "rockchip_rk3288_uart", +U_BOOT_DRIVER(rockchip_uart) = { + .name = "rockchip_uart", .id = UCLASS_SERIAL, .priv_auto = sizeof(struct ns16550), .plat_auto = sizeof(struct rockchip_uart_plat), @@ -50,7 +50,8 @@ U_BOOT_DRIVER(rockchip_rk3288_uart) = { .ops = &ns16550_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; -DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3066_uart) -DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3188_uart) -DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3328_uart) -DM_DRIVER_ALIAS(rockchip_rk3288_uart, rockchip_rk3368_uart) +DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3066_uart) +DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3188_uart) +DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3288_uart) +DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3328_uart) +DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3368_uart) From 6dcaf2d22b1c3f88481431372f1e48d36aa2a23c Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:13 +0200 Subject: [PATCH 18/48] rockchip: serial: Kconfig: add select SYS_NS16550 to config ROCKCHIP_SERIAL The Rockchip serial driver depends on an enabled NS16550 driver, so add select SYS_NS16550 to config ROCKCHIP_SERIAL. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- drivers/serial/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index dc514c95d33..b5c6005b048 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -763,6 +763,7 @@ config PL01X_SERIAL config ROCKCHIP_SERIAL bool "Rockchip on-chip UART support" depends on DM_SERIAL && SPL_OF_PLATDATA + select SYS_NS16550 help Select this to enable a debug UART for Rockchip devices when using CONFIG_SPL_OF_PLATDATA (i.e. a compiled-in device tree replacemenmt). From 9ee6c0766da8bb95c50a12bd774081bcdb0cdedb Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:14 +0200 Subject: [PATCH 19/48] rockchip: serial: Kconfig: allow ROCKCHIP_SERIAL enabled in TPL The serial_rockchip.c driver converts platdata to the data structure used in the ns16550.c file and then calls the function ns16550_serial_probe(). When compiled with OF_REAL the serial_rockchip.c driver returns now -ENODEV when probed and does no harm. The config ROCKCHIP_SERIAL is currently depends on SPL_OF_PLATDATA. Allow serial port use for both SPL and TPL by removing this dependency and SPL_BUILD restriction. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/serial/Kconfig | 4 ++-- drivers/serial/Makefile | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index b5c6005b048..1e595d06004 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -762,11 +762,11 @@ config PL01X_SERIAL config ROCKCHIP_SERIAL bool "Rockchip on-chip UART support" - depends on DM_SERIAL && SPL_OF_PLATDATA + depends on DM_SERIAL select SYS_NS16550 help Select this to enable a debug UART for Rockchip devices when using - CONFIG_SPL_OF_PLATDATA (i.e. a compiled-in device tree replacemenmt). + OF_PLATDATA (i.e. a compiled-in device tree replacemenmt). This uses the ns16550 driver, converting the platdata from of-platdata to the ns16550 format. diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index b68b5e7b2bf..d8e26d72ea2 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -46,9 +46,7 @@ obj-$(CONFIG_MXC_UART) += serial_mxc.o obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o obj-$(CONFIG_MESON_SERIAL) += serial_meson.o obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o -ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o -endif obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o From 5e6ee6bde5dd8ef804665b6bf45237e30f45575b Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:37 +0200 Subject: [PATCH 20/48] rockchip: rk3066-power: sync power domain dt-binding header from Linux In order to update the DT for rk3066 sync the power domain dt-binding header. This is the state as of v5.12 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- include/dt-bindings/power/rk3066-power.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 include/dt-bindings/power/rk3066-power.h diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h new file mode 100644 index 00000000000..acf9f310ac5 --- /dev/null +++ b/include/dt-bindings/power/rk3066-power.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ +#define __DT_BINDINGS_POWER_RK3066_POWER_H__ + +/* VD_CORE */ +#define RK3066_PD_A9_0 0 +#define RK3066_PD_A9_1 1 +#define RK3066_PD_DBG 4 +#define RK3066_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3066_PD_VIDEO 6 +#define RK3066_PD_VIO 7 +#define RK3066_PD_GPU 8 +#define RK3066_PD_PERI 9 +#define RK3066_PD_CPU 10 +#define RK3066_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3066_PD_RTC 12 + +#endif From e6b0ed0e74099fcfa94263e849d8695992060e19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Jarosz?= Date: Sat, 16 Apr 2022 17:09:38 +0200 Subject: [PATCH 21/48] rockchip: rk3066: add grf header file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit grf is needed by various drivers for rk3066 soc. Signed-off-by: Paweł Jarosz Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/grf_rk3066.h | 210 ++++++++++++++++++ 1 file changed, 210 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h new file mode 100644 index 00000000000..d8e0812ceea --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021 Paweł Jarosz + */ + +#ifndef _ASM_ARCH_GRF_RK3066_H +#define _ASM_ARCH_GRF_RK3066_H + +#include +#include + +#define REG(name, h, l) \ + name##_MASK = GENMASK(h, l), \ + name##_SHIFT = __bf_shf(name##_MASK) + +struct rk3066_grf_gpio_lh { + u32 l; + u32 h; +}; + +struct rk3066_grf { + struct rk3066_grf_gpio_lh gpio_dir[7]; + struct rk3066_grf_gpio_lh gpio_do[7]; + struct rk3066_grf_gpio_lh gpio_en[7]; + + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + + u32 gpio4a_iomux; + u32 gpio4b_iomux; + u32 gpio4c_iomux; + u32 gpio4d_iomux; + + u32 reserved0[5]; + + u32 gpio6b_iomux; + + u32 reserved1[2]; + + struct rk3066_grf_gpio_lh gpio_pull[7]; + + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + + u32 soc_status0; + + u32 dmac1_con[3]; + u32 dmac2_con[4]; + + u32 uoc0_con[3]; + u32 uoc1_con[4]; + u32 ddrc_con; + u32 ddrc_stat; + + u32 reserved2[10]; + + u32 os_reg[4]; +}; + +check_member(rk3066_grf, os_reg[3], 0x01d4); + +/* GRF_GPIO1B_IOMUX */ +enum { + REG(GPIO1B1, 2, 2), + GPIO1B1_GPIO = 0, + GPIO1B1_UART2_SOUT, + + REG(GPIO1B0, 0, 0), + GPIO1B0_GPIO = 0, + GPIO1B0_UART2_SIN +}; + +/* GRF_GPIO3B_IOMUX */ +enum { + REG(GPIO3B6, 12, 12), + GPIO3B6_GPIO = 0, + GPIO3B6_SDMMC0_DECTN, + + REG(GPIO3B5, 10, 10), + GPIO3B5_GPIO = 0, + GPIO3B5_SDMMC0_DATA3, + + REG(GPIO3B4, 8, 8), + GPIO3B4_GPIO = 0, + GPIO3B4_SDMMC0_DATA2, + + REG(GPIO3B3, 6, 6), + GPIO3B3_GPIO = 0, + GPIO3B3_SDMMC0_DATA1, + + REG(GPIO3B2, 4, 4), + GPIO3B2_GPIO = 0, + GPIO3B2_SDMMC0_DATA0, + + REG(GPIO3B1, 2, 2), + GPIO3B1_GPIO = 0, + GPIO3B1_SDMMC0_CMD, + + REG(GPIO3B0, 0, 0), + GPIO3B0_GPIO = 0, + GPIO3B0_SDMMC0_CLKOUT, +}; + +/* GRF_SOC_CON0 */ +enum { + REG(SMC_MUX_CON, 13, 13), + + REG(NOC_REMAP, 12, 12), + + REG(EMMC_FLASH_SEL, 11, 11), + + REG(TZPC_REVISION, 10, 7), + + REG(L2CACHE_ACC, 6, 5), + + REG(L2RD_WAIT, 4, 3), + + REG(IMEMRD_WAIT, 2, 1), + + REG(SOC_REMAP, 0, 0), +}; + +/* GRF_SOC_CON1 */ +enum { + REG(RKI2C4_SEL, 15, 15), + + REG(RKI2C3_SEL, 14, 14), + + REG(RKI2C2_SEL, 13, 13), + + REG(RKI2C1_SEL, 12, 12), + + REG(RKI2C0_SEL, 11, 11), + + REG(VCODEC_SEL, 10, 10), + + REG(PERI_EMEM_PAUSE, 9, 9), + + REG(PERI_USB_PAUSE, 8, 8), + + REG(SMC_MUX_MODE_0, 6, 6), + + REG(SMC_SRAM_MW_0, 5, 4), + + REG(SMC_REMAP_0, 3, 3), + + REG(SMC_A_GT_M0_SYNC, 2, 2), + + REG(EMAC_SPEED, 1, 1), + + REG(EMAC_MODE, 0, 0), +}; + +/* GRF_SOC_CON2 */ +enum { + REG(MSCH4_MAINDDR3, 7, 7), + MSCH4_MAINDDR3_DDR3 = 1, + + REG(EMAC_NEWRCV_EN, 6, 6), + + REG(SW_ADDR15_EN, 5, 5), + + REG(SW_ADDR16_EN, 4, 4), + + REG(SW_ADDR17_EN, 3, 3), + + REG(BANK2_TO_RANK_EN, 2, 2), + + REG(RANK_TO_ROW15_EN, 1, 1), + + REG(UPCTL_C_ACTIVE_IN, 0, 0), + UPCTL_C_ACTIVE_IN_MAY = 0, + UPCTL_C_ACTIVE_IN_WILL, +}; + +/* GRF_DDRC_CON0 */ +enum { + REG(DTO_LB, 12, 11), + + REG(DTO_TE, 10, 9), + + REG(DTO_PDR, 8, 7), + + REG(DTO_PDD, 6, 5), + + REG(DTO_IOM, 4, 3), + + REG(DTO_OE, 2, 1), + + REG(ATO_AE, 0, 0), +}; +#endif From 730a402450516667e51fab4c519ba16709d2251b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Jarosz?= Date: Sat, 16 Apr 2022 17:09:39 +0200 Subject: [PATCH 22/48] rockchip: rk3066: add clock driver for rk3066 soc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the clock driver for the rk3066 platform. Derived from the rk3288 and rk3188 driver it supports only a bare minimum to bring up the system to reduce the TPL size for: SDRAM clock configuration. The boot devices NAND, EMMC, SDMMC, SPI. A UART for the debug messages (fixed) at 115200n8. A SARADC for the recovery button. A TIMER for the delays (fixed). There's support for two possible frequencies, the safe 600MHz which will work with default pmic settings and will be set to get away from the 24MHz default and the maximum of 1.416Ghz, which boards can set if they were able to get pmic support for it. After the clock tree is set during the TPL probe there's no parent update support. In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c obtain the (fixed) clk_get_rate from the clock driver instead of platdata. The rk3066 cru node has a number of assigned-clocks properties that call the .set_rate() function. Add them to the list so that they return a 0 instead of -ENOENT. Signed-off-by: Paweł Jarosz Signed-off-by: Johan Jonker Reviewed-by: Sean Anderson Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/cru_rk3066.h | 157 ++++ drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3066.c | 717 ++++++++++++++++++ 3 files changed, 875 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h create mode 100644 drivers/clk/rockchip/clk_rk3066.c diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3066.h b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h new file mode 100644 index 00000000000..76a715a8e6a --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Paweł Jarosz + */ + +#ifndef _ASM_ARCH_CRU_RK3066_H +#define _ASM_ARCH_CRU_RK3066_H + +#include +#include + +#define REG(name, h, l) \ + name##_MASK = GENMASK(h, l), \ + name##_SHIFT = __bf_shf(name##_MASK) + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (1416 * 1000000) +#define APLL_SAFE_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) +#define CPLL_HZ (384 * 1000000) + +/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ +#define CPU_ACLK_HZ 297000000 +#define CPU_HCLK_HZ 148500000 +#define CPU_PCLK_HZ 74250000 +#define CPU_H2P_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3066_clk_priv { + struct rk3066_grf *grf; + struct rk3066_cru *cru; + ulong rate; + bool has_bwadj; +}; + +struct rk3066_cru { + struct rk3066_pll { + u32 con0; + u32 con1; + u32 con2; + u32 con3; + } pll[4]; + u32 cru_mode_con; + u32 cru_clksel_con[35]; + u32 cru_clkgate_con[10]; + u32 reserved1[2]; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 reserved2[2]; + u32 cru_softrst_con[9]; + u32 cru_misc_con; + u32 reserved3[2]; + u32 cru_glb_cnt_th; +}; + +check_member(rk3066_cru, cru_glb_cnt_th, 0x0140); + +/* CRU_CLKSEL0_CON */ +enum { + REG(CPU_ACLK_PLL, 8, 8), + CPU_ACLK_PLL_SELECT_APLL = 0, + CPU_ACLK_PLL_SELECT_GPLL, + + REG(CORE_PERI_DIV, 7, 6), + + REG(A9_CORE_DIV, 4, 0), +}; + +/* CRU_CLKSEL1_CON */ +enum { + REG(AHB2APB_DIV, 15, 14), + + REG(CPU_PCLK_DIV, 13, 12), + + REG(CPU_HCLK_DIV, 9, 8), + + REG(CPU_ACLK_DIV, 2, 0), +}; + +/* CRU_CLKSEL10_CON */ +enum { + REG(PERI_SEL_PLL, 15, 15), + PERI_SEL_CPLL = 0, + PERI_SEL_GPLL, + + REG(PERI_PCLK_DIV, 13, 12), + + REG(PERI_HCLK_DIV, 9, 8), + + REG(PERI_ACLK_DIV, 4, 0), +}; + +/* CRU_CLKSEL11_CON */ +enum { + REG(MMC0_DIV, 5, 0), +}; + +/* CRU_CLKSEL12_CON */ +enum { + REG(UART_PLL, 15, 15), + UART_PLL_SELECT_GENERAL = 0, + UART_PLL_SELECT_CODEC, + + REG(EMMC_DIV, 13, 8), + + REG(SDIO_DIV, 5, 0), +}; + +/* CRU_CLKSEL24_CON */ +enum { + REG(SARADC_DIV, 15, 8), +}; + +/* CRU_CLKSEL25_CON */ +enum { + REG(SPI1_DIV, 14, 8), + + REG(SPI0_DIV, 6, 0), +}; + +/* CRU_CLKSEL34_CON */ +enum { + REG(TSADC_DIV, 15, 0), +}; + +/* CRU_MODE_CON */ +enum { + REG(GPLL_MODE, 13, 12), + + REG(CPLL_MODE, 9, 8), + + REG(DPLL_MODE, 5, 4), + + REG(APLL_MODE, 1, 0), + PLL_MODE_SLOW = 0, + PLL_MODE_NORMAL, + PLL_MODE_DEEP, +}; + +/* CRU_APLL_CON0 */ +enum { + REG(CLKR, 13, 8), + + REG(CLKOD, 3, 0), +}; + +/* CRU_APLL_CON1 */ +enum { + REG(CLKF, 12, 0), +}; + +#endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 913f611a0ff..a72d8fe58a6 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -6,6 +6,7 @@ obj-y += clk_pll.o obj-$(CONFIG_ROCKCHIP_PX30) += clk_px30.o obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3066) += clk_rk3066.o obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c new file mode 100644 index 00000000000..2c12f6e0441 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3066.c @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2015 Google, Inc + * (C) Copyright 2016 Heiko Stuebner + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct rk3066_clk_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3066a_cru dtd; +#endif +}; + +struct pll_div { + u32 nr; + u32 nf; + u32 no; +}; + +enum { + VCO_MAX_HZ = 1416U * 1000000, + VCO_MIN_HZ = 300 * 1000000, + OUTPUT_MAX_HZ = 1416U * 1000000, + OUTPUT_MIN_HZ = 30 * 1000000, + FREF_MAX_HZ = 1416U * 1000000, + FREF_MIN_HZ = 30 * 1000, +}; + +enum { + /* PLL CON0 */ + PLL_OD_MASK = GENMASK(3, 0), + + /* PLL CON1 */ + PLL_NF_MASK = GENMASK(12, 0), + + /* PLL CON2 */ + PLL_BWADJ_MASK = GENMASK(11, 0), + + /* PLL CON3 */ + PLL_RESET_SHIFT = 5, + + /* GRF_SOC_STATUS0 */ + SOCSTS_DPLL_LOCK = BIT(4), + SOCSTS_APLL_LOCK = BIT(5), + SOCSTS_CPLL_LOCK = BIT(6), + SOCSTS_GPLL_LOCK = BIT(7), +}; + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _nr, _no) {\ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)) + +/* Keep divisors as low as possible to reduce jitter and power usage. */ +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); + +static int rk3066_clk_set_pll(struct rk3066_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + int pll_id = rk_pll_id(clk_id); + struct rk3066_pll *pll = &cru->pll[pll_id]; + /* All PLLs have the same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; + uint output_hz = vco_hz / div->no; + + debug("%s: PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", __func__, + (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && + (div->no == 1 || !(div->no % 2))); + + /* Enter reset. */ + rk_setreg(&pll->con3, BIT(PLL_RESET_SHIFT)); + + rk_clrsetreg(&pll->con0, + CLKR_MASK | PLL_OD_MASK, + ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); + rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); + + rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); + + /* Exit reset. */ + rk_clrreg(&pll->con3, BIT(PLL_RESET_SHIFT)); + + return 0; +} + +static int rk3066_clk_configure_ddr(struct rk3066_cru *cru, struct rk3066_grf *grf, + unsigned int hz) +{ + static const struct pll_div dpll_cfg[] = { + {.nf = 25, .nr = 2, .no = 1}, + {.nf = 400, .nr = 9, .no = 2}, + {.nf = 500, .nr = 9, .no = 2}, + {.nf = 100, .nr = 3, .no = 1}, + }; + int cfg; + + switch (hz) { + case 300000000: + cfg = 0; + break; + case 533000000: /* actually 533.3P MHz */ + cfg = 1; + break; + case 666000000: /* actually 666.6P MHz */ + cfg = 2; + break; + case 800000000: + cfg = 3; + break; + default: + debug("%s: unsupported SDRAM frequency", __func__); + return -EINVAL; + } + + /* Enter PLL slow mode. */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, + PLL_MODE_SLOW << DPLL_MODE_SHIFT); + + rk3066_clk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); + + /* Wait for PLL lock. */ + while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) + udelay(1); + + /* Enter PLL normal mode. */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, + PLL_MODE_NORMAL << DPLL_MODE_SHIFT); + + return 0; +} + +static int rk3066_clk_configure_cpu(struct rk3066_cru *cru, struct rk3066_grf *grf, + unsigned int hz) +{ + static const struct pll_div apll_cfg[] = { + {.nf = 50, .nr = 1, .no = 2}, + {.nf = 59, .nr = 1, .no = 1}, + }; + int div_core_peri, div_cpu_aclk, cfg; + + /* + * We support two possible frequencies, the safe 600MHz + * which will work with default pmic settings and will + * be set to get away from the 24MHz default and + * the maximum of 1.416Ghz, which boards can set if they + * were able to get pmic support for it. + */ + switch (hz) { + case APLL_SAFE_HZ: + cfg = 0; + div_core_peri = 1; + div_cpu_aclk = 3; + break; + case APLL_HZ: + cfg = 1; + div_core_peri = 2; + div_cpu_aclk = 3; + break; + default: + debug("unsupported ARMCLK frequency"); + return -EINVAL; + } + + /* Enter PLL slow mode. */ + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, + PLL_MODE_SLOW << APLL_MODE_SHIFT); + + rk3066_clk_set_pll(cru, CLK_ARM, &apll_cfg[cfg]); + + /* Wait for PLL lock. */ + while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK)) + udelay(1); + + /* Set divider for peripherals attached to the CPU core. */ + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_PERI_DIV_MASK, + div_core_peri << CORE_PERI_DIV_SHIFT); + + /* Set up dependent divisor for cpu_aclk. */ + rk_clrsetreg(&cru->cru_clksel_con[1], + CPU_ACLK_DIV_MASK, + div_cpu_aclk << CPU_ACLK_DIV_SHIFT); + + /* Enter PLL normal mode. */ + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, + PLL_MODE_NORMAL << APLL_MODE_SHIFT); + + return hz; +} + +static uint32_t rk3066_clk_pll_get_rate(struct rk3066_cru *cru, + enum rk_clk_id clk_id) +{ + u32 nr, no, nf; + u32 con; + int pll_id = rk_pll_id(clk_id); + struct rk3066_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, + GPLL_MODE_SHIFT + }; + uint shift; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + switch (FIELD_GET(APLL_MODE_MASK, con >> shift)) { + case PLL_MODE_SLOW: + return OSC_HZ; + case PLL_MODE_NORMAL: + /* normal mode */ + con = readl(&pll->con0); + no = bitfield_extract_by_mask(con, CLKOD_MASK) + 1; + nr = bitfield_extract_by_mask(con, CLKR_MASK) + 1; + con = readl(&pll->con1); + nf = bitfield_extract_by_mask(con, CLKF_MASK) + 1; + + return (OSC_HZ * nf) / (nr * no); + case PLL_MODE_DEEP: + default: + return 32768; + } +} + +static ulong rk3066_clk_mmc_get_clk(struct rk3066_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case HCLK_EMMC: + case SCLK_EMMC: + con = readl(&cru->cru_clksel_con[12]); + div = bitfield_extract_by_mask(con, EMMC_DIV_MASK); + break; + case HCLK_SDMMC: + case SCLK_SDMMC: + con = readl(&cru->cru_clksel_con[11]); + div = bitfield_extract_by_mask(con, MMC0_DIV_MASK); + break; + case HCLK_SDIO: + case SCLK_SDIO: + con = readl(&cru->cru_clksel_con[12]); + div = bitfield_extract_by_mask(con, SDIO_DIV_MASK); + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div) / 2; +} + +static ulong rk3066_clk_mmc_set_clk(struct rk3066_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div; + + debug("%s: gclk_rate=%u\n", __func__, gclk_rate); + /* MMC clock by default divides by 2 internally, so need to provide double in CRU. */ + src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1; + assert(src_clk_div <= 0x3f); + + switch (periph) { + case HCLK_EMMC: + case SCLK_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_DIV_MASK, + src_clk_div << EMMC_DIV_SHIFT); + break; + case HCLK_SDMMC: + case SCLK_SDMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_DIV_MASK, + src_clk_div << MMC0_DIV_SHIFT); + break; + case HCLK_SDIO: + case SCLK_SDIO: + rk_clrsetreg(&cru->cru_clksel_con[12], + SDIO_DIV_MASK, + src_clk_div << SDIO_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rk3066_clk_mmc_get_clk(cru, gclk_rate, periph); +} + +static ulong rk3066_clk_spi_get_clk(struct rk3066_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case SCLK_SPI0: + con = readl(&cru->cru_clksel_con[25]); + div = bitfield_extract_by_mask(con, SPI0_DIV_MASK); + break; + case SCLK_SPI1: + con = readl(&cru->cru_clksel_con[25]); + div = bitfield_extract_by_mask(con, SPI1_DIV_MASK); + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div); +} + +static ulong rk3066_clk_spi_set_clk(struct rk3066_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; + + assert(src_clk_div < 128); + switch (periph) { + case SCLK_SPI0: + assert(src_clk_div <= SPI0_DIV_MASK >> SPI0_DIV_SHIFT); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI0_DIV_MASK, + src_clk_div << SPI0_DIV_SHIFT); + break; + case SCLK_SPI1: + assert(src_clk_div <= SPI1_DIV_MASK >> SPI1_DIV_SHIFT); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI1_DIV_MASK, + src_clk_div << SPI1_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rk3066_clk_spi_get_clk(cru, gclk_rate, periph); +} + +static ulong rk3066_clk_saradc_get_clk(struct rk3066_cru *cru, int periph) +{ + u32 div, con; + + switch (periph) { + case SCLK_SARADC: + con = readl(&cru->cru_clksel_con[24]); + div = bitfield_extract_by_mask(con, SARADC_DIV_MASK); + break; + case SCLK_TSADC: + con = readl(&cru->cru_clksel_con[34]); + div = bitfield_extract_by_mask(con, TSADC_DIV_MASK); + break; + default: + return -EINVAL; + } + return DIV_TO_RATE(PERI_PCLK_HZ, div); +} + +static ulong rk3066_clk_saradc_set_clk(struct rk3066_cru *cru, uint hz, + int periph) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(PERI_PCLK_HZ, hz) - 1; + assert(src_clk_div < 128); + + switch (periph) { + case SCLK_SARADC: + rk_clrsetreg(&cru->cru_clksel_con[24], + SARADC_DIV_MASK, + src_clk_div << SARADC_DIV_SHIFT); + break; + case SCLK_TSADC: + rk_clrsetreg(&cru->cru_clksel_con[34], + SARADC_DIV_MASK, + src_clk_div << SARADC_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rk3066_clk_saradc_get_clk(cru, periph); +} + +static void rk3066_clk_init(struct rk3066_cru *cru, struct rk3066_grf *grf) +{ + u32 aclk_div, hclk_div, pclk_div, h2p_div; + + /* Enter PLL slow mode. */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | + CPLL_MODE_MASK, + PLL_MODE_SLOW << GPLL_MODE_SHIFT | + PLL_MODE_SLOW << CPLL_MODE_SHIFT); + + /* Init PLL. */ + rk3066_clk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + rk3066_clk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); + + /* Wait for PLL lock. */ + while ((readl(&grf->soc_status0) & + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) + udelay(1); + + /* + * Select CPU clock PLL source and + * reparent aclk_cpu_pre from APPL to GPLL. + * Set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1; + assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CPU_ACLK_PLL_MASK | + A9_CORE_DIV_MASK, + CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT | + aclk_div << A9_CORE_DIV_SHIFT); + + hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ); + assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3); + pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ); + assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4); + h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ); + assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[1], + AHB2APB_DIV_MASK | + CPU_PCLK_DIV_MASK | + CPU_HCLK_DIV_MASK, + h2p_div << AHB2APB_DIV_SHIFT | + pclk_div << CPU_PCLK_DIV_SHIFT | + hclk_div << CPU_HCLK_DIV_SHIFT); + + /* + * Select PERI clock PLL source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && (pclk_div < 0x4)); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PCLK_DIV_MASK | + PERI_HCLK_DIV_MASK | + PERI_ACLK_DIV_MASK, + PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* Enter PLL normal mode. */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | + CPLL_MODE_MASK, + PLL_MODE_NORMAL << GPLL_MODE_SHIFT | + PLL_MODE_NORMAL << CPLL_MODE_SHIFT); + + rk3066_clk_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000); +} + +static ulong rk3066_clk_get_rate(struct clk *clk) +{ + struct rk3066_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate, gclk_rate; + + gclk_rate = rk3066_clk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case 1 ... 4: + new_rate = rk3066_clk_pll_get_rate(priv->cru, clk->id); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + case SCLK_EMMC: + case SCLK_SDMMC: + case SCLK_SDIO: + new_rate = rk3066_clk_mmc_get_clk(priv->cru, PERI_HCLK_HZ, + clk->id); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rk3066_clk_spi_get_clk(priv->cru, PERI_PCLK_HZ, + clk->id); + break; + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_I2C4: + return gclk_rate; + case SCLK_SARADC: + case SCLK_TSADC: + new_rate = rk3066_clk_saradc_get_clk(priv->cru, clk->id); + break; + case SCLK_TIMER0: + case SCLK_TIMER1: + case SCLK_TIMER2: + case SCLK_UART0: + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + return OSC_HZ; + default: + return -ENOENT; + } + + return new_rate; +} + +static ulong rk3066_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3066_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3066_cru *cru = priv->cru; + ulong new_rate; + + switch (clk->id) { + case PLL_APLL: + new_rate = rk3066_clk_configure_cpu(priv->cru, priv->grf, rate); + break; + case CLK_DDR: + new_rate = rk3066_clk_configure_ddr(priv->cru, priv->grf, rate); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + case SCLK_EMMC: + case SCLK_SDMMC: + case SCLK_SDIO: + new_rate = rk3066_clk_mmc_set_clk(cru, PERI_HCLK_HZ, + clk->id, rate); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rk3066_clk_spi_set_clk(cru, PERI_PCLK_HZ, + clk->id, rate); + break; + case SCLK_SARADC: + case SCLK_TSADC: + new_rate = rk3066_clk_saradc_set_clk(cru, rate, clk->id); + break; + case PLL_CPLL: + case PLL_GPLL: + case ACLK_CPU: + case HCLK_CPU: + case PCLK_CPU: + case ACLK_PERI: + case HCLK_PERI: + case PCLK_PERI: + return 0; + default: + return -ENOENT; + } + + return new_rate; +} + +static int rk3066_clk_enable(struct clk *clk) +{ + struct rk3066_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case HCLK_NANDC0: + rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(9)); + break; + case HCLK_SDMMC: + rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(10)); + break; + case HCLK_SDIO: + rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(11)); + break; + } + + return 0; +} + +static int rk3066_clk_disable(struct clk *clk) +{ + struct rk3066_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case HCLK_NANDC0: + rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(9)); + break; + case HCLK_SDMMC: + rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(10)); + break; + case HCLK_SDIO: + rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(11)); + break; + } + + return 0; +} + +static struct clk_ops rk3066_clk_ops = { + .disable = rk3066_clk_disable, + .enable = rk3066_clk_enable, + .get_rate = rk3066_clk_get_rate, + .set_rate = rk3066_clk_set_rate, +}; + +static int rk3066_clk_of_to_plat(struct udevice *dev) +{ + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3066_clk_priv *priv = dev_get_priv(dev); + + priv->cru = dev_read_addr_ptr(dev); + } + + return 0; +} + +static int rk3066_clk_probe(struct udevice *dev) +{ + struct rk3066_clk_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + return PTR_ERR(priv->grf); + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3066_clk_plat *plat = dev_get_plat(dev); + + priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); +#endif + + if (IS_ENABLED(CONFIG_TPL_BUILD)) { + rk3066_clk_init(priv->cru, priv->grf); + + /* Init CPU frequency. */ + rk3066_clk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ); + } + + return 0; +} + +static int rk3066_clk_bind(struct udevice *dev) +{ + struct udevice *sys_child; + struct sysreset_reg *priv; + int reg_offset, ret; + + /* The reset driver does not have a device node, so bind it here. */ + ret = device_bind(dev, DM_DRIVER_GET(sysreset_rockchip), "sysreset", + NULL, ofnode_null(), &sys_child); + if (ret) { + dev_dbg(dev, "Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3066_cru, + cru_glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rk3066_cru, + cru_glb_srst_snd_value); + dev_set_priv(sys_child, priv); + } + + if (CONFIG_IS_ENABLED(RESET_ROCKCHIP)) { + reg_offset = offsetof(struct rk3066_cru, cru_softrst_con[0]); + ret = rockchip_reset_bind(dev, reg_offset, 9); + if (ret) + dev_dbg(dev, "Warning: software reset driver bind failed\n"); + } + + return 0; +} + +static const struct udevice_id rk3066_clk_ids[] = { + { .compatible = "rockchip,rk3066a-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3066a_cru) = { + .name = "rockchip_rk3066a_cru", + .id = UCLASS_CLK, + .ops = &rk3066_clk_ops, + .probe = rk3066_clk_probe, + .bind = rk3066_clk_bind, + .of_match = rk3066_clk_ids, + .of_to_plat = rk3066_clk_of_to_plat, + .priv_auto = sizeof(struct rk3066_clk_priv), + .plat_auto = sizeof(struct rk3066_clk_plat), +}; From 086863c9829ed17e3a7d0425c63fd2898d6c04a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Jarosz?= Date: Sat, 16 Apr 2022 17:09:40 +0200 Subject: [PATCH 23/48] rockchip: rk3066: add rk3066 pinctrl driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add driver supporting pin multiplexing on rk3066 platform. Signed-off-by: Paweł Jarosz Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl-rk3066.c | 112 ++++++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3066.c diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index fcf19f877a9..7d03f8101df 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -5,6 +5,7 @@ obj-y += pinctrl-rockchip-core.o obj-$(CONFIG_ROCKCHIP_PX30) += pinctrl-px30.o obj-$(CONFIG_ROCKCHIP_RK3036) += pinctrl-rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3066) += pinctrl-rk3066.o obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c b/drivers/pinctrl/rockchip/pinctrl-rk3066.c new file mode 100644 index 00000000000..598b63223e3 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-rockchip.h" + +static int rk3066_pinctrl_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RK3066_PULL_OFFSET 0x118 +#define RK3066_PULL_PINS_PER_REG 16 +#define RK3066_PULL_BANK_STRIDE 8 + +static void rk3066_pinctrl_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + *reg = RK3066_PULL_OFFSET; + *reg += bank->bank_num * RK3066_PULL_BANK_STRIDE; + *reg += (pin_num / RK3066_PULL_PINS_PER_REG) * 4; + + *bit = pin_num % RK3066_PULL_PINS_PER_REG; +}; + +static int rk3066_pinctrl_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit; + u32 data; + + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && + pull != PIN_CONFIG_BIAS_DISABLE) + return -EOPNOTSUPP; + + rk3066_pinctrl_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + data = BIT(bit + 16); + if (pull == PIN_CONFIG_BIAS_DISABLE) + data |= BIT(bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + +static struct rockchip_pin_bank rk3066_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), + PIN_BANK(4, 32, "gpio4"), + PIN_BANK(6, 16, "gpio6"), +}; + +static struct rockchip_pin_ctrl rk3066_pin_ctrl = { + .pin_banks = rk3066_pin_banks, + .nr_banks = ARRAY_SIZE(rk3066_pin_banks), + .grf_mux_offset = 0xa8, + .set_mux = rk3066_pinctrl_set_mux, + .set_pull = rk3066_pinctrl_set_pull, +}; + +static const struct udevice_id rk3066_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3066a-pinctrl", + .data = (ulong)&rk3066_pin_ctrl + }, + {} +}; + +U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = { + .name = "rockchip_rk3066a_pinctrl", + .id = UCLASS_PINCTRL, + .ops = &rockchip_pinctrl_ops, + .probe = rockchip_pinctrl_probe, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif + .of_match = rk3066_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), +}; From 4b957e7ff5024c0e9105af331c3b2dc3073c44e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Jarosz?= Date: Sat, 16 Apr 2022 17:09:41 +0200 Subject: [PATCH 24/48] rockchip: rk3066: add sdram driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add rockchip rk3066 sdram driver Signed-off-by: Paweł Jarosz Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/ram/rockchip/Makefile | 1 + drivers/ram/rockchip/sdram_rk3066.c | 892 ++++++++++++++++++++++++++++ 2 files changed, 893 insertions(+) create mode 100644 drivers/ram/rockchip/sdram_rk3066.c diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index ca1c289b884..6d530c29afd 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o +obj-$(CONFIG_ROCKCHIP_RK3066) = sdram_rk3066.o obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c new file mode 100644 index 00000000000..832154ee3af --- /dev/null +++ b/drivers/ram/rockchip/sdram_rk3066.c @@ -0,0 +1,892 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * (C) Copyright 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * Adapted from the very similar rk3188 ddr init. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct rk3066_dmc_chan_info { + struct rk3288_ddr_pctl *pctl; + struct rk3288_ddr_publ *publ; + struct rk3188_msch *msch; +}; + +struct rk3066_dmc_dram_info { + struct rk3066_dmc_chan_info chan[1]; + struct ram_info info; + struct clk ddr_clk; + struct rk3066_cru *cru; + struct rk3066_grf *grf; + struct rk3066_sgrf *sgrf; + struct rk3188_pmu *pmu; +}; + +struct rk3066_dmc_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3066_dmc of_plat; +#endif + struct rk3288_sdram_channel ch[2]; + struct rk3288_sdram_pctl_timing pctl_timing; + struct rk3288_sdram_phy_timing phy_timing; + struct rk3288_base_params base; + int num_channels; + struct regmap *map; +}; + +const int rk3066_dmc_ddrconf_table[] = { + /* + * [5:4] row(13+n) + * [1:0] col(9+n), assume bw=2 + * row col,bw + */ + 0, + (2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, + (1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, + (0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, + (2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, + (1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, + (0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, + (1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT, + (0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#define TEST_PATTERN 0x5aa5f00f +#define DQS_GATE_TRAINING_ERROR_RANK0 BIT(4) +#define DQS_GATE_TRAINING_ERROR_RANK1 BIT(5) + +static void rk3066_dmc_copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +static void rk3066_dmc_ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy) +{ + u32 phy_ctl_srstn_shift = 13; + u32 ctl_psrstn_shift = 11; + u32 ctl_srstn_shift = 10; + u32 phy_psrstn_shift = 9; + u32 phy_srstn_shift = 8; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | + 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | + 1 << phy_srstn_shift, + phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | + ctl << ctl_srstn_shift | phy << phy_psrstn_shift | + phy << phy_srstn_shift); +} + +static void rk3066_dmc_ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n) +{ + u32 phy_ctl_srstn_shift = 13; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); +} + +static void rk3066_dmc_phy_pctrl_reset(struct rk3066_cru *cru, + struct rk3288_ddr_publ *publ, + int channel) +{ + int i; + + rk3066_dmc_ddr_reset(cru, channel, 1, 1); + udelay(1); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + rk3066_dmc_ddr_reset(cru, channel, 1, 0); + udelay(10); + rk3066_dmc_ddr_reset(cru, channel, 0, 0); + udelay(10); +} + +static void rk3066_dmc_phy_dll_bypass_set(struct rk3288_ddr_publ *publ, u32 freq) +{ + int i; + + if (freq <= 250000000) { + if (freq <= 150000000) + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + else + setbits_le32(&publ->dllgcr, SBIAS_BYPASS); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + + setbits_le32(&publ->pir, PIR_DLLBYP); + } else { + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) { + clrbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + } + + clrbits_le32(&publ->pir, PIR_DLLBYP); + } +} + +static void rk3066_dmc_dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) +{ + writel(DFI_INIT_START, &pctl->dfistcfg0); + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, + &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); + writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); + writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); + writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); + writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); + writel(1, &pctl->dfitphyupdtype0); + + /* CS0 and CS1 write ODT enable. */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), + &pctl->dfiodtcfg); + /* Write ODT length. */ + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + /* Disable phyupd and ctrlupd. */ + writel(0, &pctl->dfiupdcfg); +} + +static void rk3066_dmc_ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel, + bool ddr3_mode) +{ + uint mask, val; + + mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT; + val = ddr3_mode << MSCH4_MAINDDR3_SHIFT; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +static void rk3066_dmc_ddr_rank_2_row15en(struct rk3066_grf *grf, bool enable) +{ + uint mask, val; + + mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT; + val = enable << RANK_TO_ROW15_EN_SHIFT; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +static void rk3066_dmc_pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, + struct rk3066_dmc_sdram_params *sdram_params, + struct rk3066_grf *grf) +{ + rk3066_dmc_copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, + sizeof(sdram_params->pctl_timing)); + switch (sdram_params->base.dramtype) { + case DDR3: + if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { + writel(sdram_params->pctl_timing.tcl - 3, + &pctl->dfitrddataen); + } else { + writel(sdram_params->pctl_timing.tcl - 2, + &pctl->dfitrddataen); + } + writel(sdram_params->pctl_timing.tcwl - 1, + &pctl->dfitphywrlat); + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | + DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + rk3066_dmc_ddr_set_ddr3_mode(grf, channel, true); + break; + } + + setbits_le32(&pctl->scfg, 1); +} + +static void rk3066_dmc_phy_cfg(const struct rk3066_dmc_chan_info *chan, int channel, + struct rk3066_dmc_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; + u32 dinit2; + int i; + + dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); + /* Set DDR PHY timing. */ + rk3066_dmc_copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, + sizeof(sdram_params->phy_timing)); + writel(sdram_params->base.noc_timing, &msch->ddrtiming); + writel(0x3f, &msch->readlatency); + writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | + 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); + writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, + &publ->ptr[1]); + writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, + &publ->ptr[2]); + + switch (sdram_params->base.dramtype) { + case DDR3: + clrbits_le32(&publ->pgcr, 0x1f); + clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, + DDRMD_DDR3 << DDRMD_SHIFT); + break; + } + if (sdram_params->base.odt) { + /* Enable dynamic RTT. */ + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } else { + /* Disable dynamic RTT. */ + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } +} + +static void rk3066_dmc_phy_init(struct rk3288_ddr_publ *publ) +{ + setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST + | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); + udelay(1); + while ((readl(&publ->pgsr) & + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) + ; +} + +static void rk3066_dmc_send_command(struct rk3288_ddr_pctl *pctl, u32 rank, + u32 cmd, u32 arg) +{ + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); + udelay(1); + while (readl(&pctl->mcmd) & START_CMD) + ; +} + +static inline void rk3066_dmc_send_command_op(struct rk3288_ddr_pctl *pctl, + u32 rank, u32 cmd, u32 ma, u32 op) +{ + rk3066_dmc_send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | + (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); +} + +static void rk3066_dmc_memory_init(struct rk3288_ddr_publ *publ, + u32 dramtype) +{ + setbits_le32(&publ->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + udelay(1); + while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) + != (PGSR_IDONE | PGSR_DLDONE)) + ; +} + +static void rk3066_dmc_move_to_config_state(struct rk3288_ddr_publ *publ, + struct rk3288_ddr_pctl *pctl) +{ + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) + != ACCESS) + ; + /* Wait DLL lock. */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + /* + * If at low power state we need to wakeup first + * and then enter the config. + */ + fallthrough; + case ACCESS: + fallthrough; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + break; + case CONFIG: + return; + default: + break; + } + } +} + +static void rk3066_dmc_set_bandwidth_ratio(const struct rk3066_dmc_chan_info *chan, int channel, + u32 n, struct rk3066_grf *grf) +{ + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + + if (n == 1) { + setbits_le32(&pctl->ppcfg, 1); + setbits_le32(&msch->ddrtiming, 1 << 31); + /* Data byte disable. */ + clrbits_le32(&publ->datx8[2].dxgcr, 1); + clrbits_le32(&publ->datx8[3].dxgcr, 1); + /* Disable DLL. */ + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + } else { + clrbits_le32(&pctl->ppcfg, 1); + clrbits_le32(&msch->ddrtiming, 1 << 31); + /* Data byte enable.*/ + setbits_le32(&publ->datx8[2].dxgcr, 1); + setbits_le32(&publ->datx8[3].dxgcr, 1); + + /* Enable DLL. */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + /* Reset DLL. */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + udelay(10); + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + } + setbits_le32(&pctl->dfistcfg0, 1 << 2); +} + +static int rk3066_dmc_data_training(const struct rk3066_dmc_chan_info *chan, int channel, + struct rk3066_dmc_sdram_params *sdram_params) +{ + unsigned int j; + int ret = 0; + u32 rank; + int i; + u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + + /* Disable auto refresh. */ + writel(0, &pctl->trefi); + + if (sdram_params->base.dramtype != LPDDR3) + setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + rank = sdram_params->ch[channel].rank | 1; + for (j = 0; j < ARRAY_SIZE(step); j++) { + /* + * Trigger QSTRN and RVTRN. + * Clear DTDONE status. + */ + setbits_le32(&publ->pir, PIR_CLRSR); + + /* Trigger DTT. */ + setbits_le32(&publ->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); + udelay(1); + /* Wait echo byte DTDONE. */ + while ((readl(&publ->datx8[0].dxgsr[0]) & rank) + != rank) + ; + while ((readl(&publ->datx8[1].dxgsr[0]) & rank) + != rank) + ; + if (!(readl(&pctl->ppcfg) & 1)) { + while ((readl(&publ->datx8[2].dxgsr[0]) + & rank) != rank) + ; + while ((readl(&publ->datx8[3].dxgsr[0]) + & rank) != rank) + ; + } + if (readl(&publ->pgsr) & + (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { + ret = -1; + break; + } + } + /* Send some auto refresh to complement the lost while DTT. */ + for (i = 0; i < (rank > 1 ? 8 : 4); i++) + rk3066_dmc_send_command(pctl, rank, REF_CMD, 0); + + if (sdram_params->base.dramtype != LPDDR3) + clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + + /* Resume auto refresh. */ + writel(sdram_params->pctl_timing.trefi, &pctl->trefi); + + return ret; +} + +static void rk3066_dmc_move_to_access_state(const struct rk3066_dmc_chan_info *chan) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & + LP_TRIG_MASK) == 1) + return; + + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + ; + /* Wait DLL lock. */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + break; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + fallthrough; + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) + ; + break; + case ACCESS: + return; + default: + break; + } + } +} + +static void rk3066_dmc_dram_cfg_rbc(const struct rk3066_dmc_chan_info *chan, u32 chnum, + struct rk3066_dmc_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + + if (sdram_params->ch[chnum].bk == 3) + clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, + 1 << PDQ_SHIFT); + else + clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); + + writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); +} + +static void rk3066_dmc_dram_all_config(const struct rk3066_dmc_dram_info *dram, + struct rk3066_dmc_sdram_params *sdram_params) +{ + unsigned int chan; + u32 sys_reg = 0; + + sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; + for (chan = 0; chan < sdram_params->num_channels; chan++) { + const struct rk3288_sdram_channel *info = + &sdram_params->ch[chan]; + + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); + + rk3066_dmc_dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); + } + if (sdram_params->ch[0].rank == 2) + rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0); + else + rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1); + + writel(sys_reg, &dram->pmu->sys_reg[2]); +} + +static int rk3066_dmc_sdram_rank_bw_detect(struct rk3066_dmc_dram_info *dram, int channel, + struct rk3066_dmc_sdram_params *sdram_params) +{ + int reg; + int need_trainig = 0; + const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_publ *publ = chan->publ; + + rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0); + + if (rk3066_dmc_data_training(chan, channel, sdram_params) < 0) { + debug("first data training fail!\n"); + reg = readl(&publ->datx8[0].dxgsr[0]); + /* Check the result for rank 0. */ + if (channel == 0 && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { + debug("data training fail!\n"); + return -EIO; + } + + /* Check the result for rank 1. */ + if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { + sdram_params->ch[channel].rank = 1; + clrsetbits_le32(&publ->pgcr, 0xF << 18, + sdram_params->ch[channel].rank << 18); + need_trainig = 1; + } + reg = readl(&publ->datx8[2].dxgsr[0]); + if (reg & (1 << 4)) { + sdram_params->ch[channel].bw = 1; + rk3066_dmc_set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, + dram->grf); + need_trainig = 1; + } + } + /* Assume that the die bit width is equel to the chip bit width. */ + sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; + + if (need_trainig && + (rk3066_dmc_data_training(chan, channel, sdram_params) < 0)) { + if (sdram_params->base.dramtype == LPDDR3) { + rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 1); + udelay(10); + rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 0); + udelay(10); + } + debug("2nd data training failed!"); + return -EIO; + } + + return 0; +} + +static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, int channel, + struct rk3066_dmc_sdram_params *sdram_params) +{ + int row, col; + unsigned int addr; + const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + int ret = 0; + + /* Detect col. */ + for (col = 11; col >= 9; col--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + + (1 << (col + sdram_params->ch[channel].bw - 1)); + writel(TEST_PATTERN, addr); + if ((readl(addr) == TEST_PATTERN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (col == 8) { + debug("Col detect error\n"); + ret = -EINVAL; + goto out; + } else { + sdram_params->ch[channel].col = col; + } + + rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1); + rk3066_dmc_move_to_config_state(publ, pctl); + writel(1, &chan->msch->ddrconf); + rk3066_dmc_move_to_access_state(chan); + /* Detect row, max 15, min13 for rk3066 */ + for (row = 16; row >= 13; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(TEST_PATTERN, addr); + if ((readl(addr) == TEST_PATTERN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (row == 12) { + debug("Row detect error\n"); + ret = -EINVAL; + } else { + sdram_params->ch[channel].cs1_row = row; + sdram_params->ch[channel].row_3_4 = 0; + debug("chn %d col %d, row %d\n", channel, col, row); + sdram_params->ch[channel].cs0_row = row; + } + +out: + return ret; +} + +static int rk3066_dmc_sdram_get_niu_config(struct rk3066_dmc_sdram_params *sdram_params) +{ + int i, tmp, size, ret = 0; + + tmp = sdram_params->ch[0].col - 9; + tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; + tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4); + size = ARRAY_SIZE(rk3066_dmc_ddrconf_table) / sizeof(rk3066_dmc_ddrconf_table[0]); + for (i = 0; i < size; i++) + if (tmp == rk3066_dmc_ddrconf_table[i]) + break; + if (i >= size) { + debug("niu config not found\n"); + ret = -EINVAL; + } else { + debug("niu config %d\n", i); + sdram_params->base.ddrconfig = i; + } + + return ret; +} + +static int rk3066_dmc_sdram_init(struct rk3066_dmc_dram_info *dram, + struct rk3066_dmc_sdram_params *sdram_params) +{ + int channel; + int zqcr; + int ret; + + if ((sdram_params->base.dramtype == DDR3 && + sdram_params->base.ddr_freq > 800000000)) { + debug("SDRAM frequency is too high!"); + return -E2BIG; + } + + ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); + if (ret) { + debug("Could not set DDR clock\n"); + return ret; + } + + for (channel = 0; channel < 1; channel++) { + const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + + rk3066_dmc_phy_pctrl_reset(dram->cru, publ, channel); + rk3066_dmc_phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); + + rk3066_dmc_dfi_cfg(pctl, sdram_params->base.dramtype); + + rk3066_dmc_pctl_cfg(channel, pctl, sdram_params, dram->grf); + + rk3066_dmc_phy_cfg(chan, channel, sdram_params); + + rk3066_dmc_phy_init(publ); + + writel(POWER_UP_START, &pctl->powctl); + while (!(readl(&pctl->powstat) & POWER_UP_DONE)) + ; + + rk3066_dmc_memory_init(publ, sdram_params->base.dramtype); + rk3066_dmc_move_to_config_state(publ, pctl); + + /* Use 32bit bus width for detection. */ + sdram_params->ch[channel].bw = 2; + rk3066_dmc_set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, dram->grf); + /* + * set cs, using n=3 for detect + * CS0, n=1 + * CS1, n=2 + * CS0 & CS1, n = 3 + */ + sdram_params->ch[channel].rank = 2; + clrsetbits_le32(&publ->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); + + /* DS=40ohm,ODT=155ohm */ + zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | + 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | + 0x19 << PD_OUTPUT_SHIFT; + writel(zqcr, &publ->zq1cr[0]); + writel(zqcr, &publ->zq0cr[0]); + + /* Detect the rank and bit-width with data-training. */ + writel(1, &chan->msch->ddrconf); + rk3066_dmc_sdram_rank_bw_detect(dram, channel, sdram_params); + + if (sdram_params->base.dramtype == LPDDR3) { + u32 i; + + writel(0, &pctl->mrrcfg0); + + for (i = 0; i < 17; i++) + rk3066_dmc_send_command_op(pctl, 1, MRR_CMD, i, 0); + } + writel(4, &chan->msch->ddrconf); + rk3066_dmc_move_to_access_state(chan); + /* DDR3 and LPDDR3 are always 8 bank, no need to detect. */ + sdram_params->ch[channel].bk = 3; + /* Detect Col and Row number. */ + ret = rk3066_dmc_sdram_col_row_detect(dram, channel, sdram_params); + if (ret) + goto error; + } + /* Find NIU DDR configuration. */ + ret = rk3066_dmc_sdram_get_niu_config(sdram_params); + if (ret) + goto error; + + rk3066_dmc_dram_all_config(dram, sdram_params); + debug("SDRAM init OK!\n"); + + return 0; +error: + debug("SDRAM init failed!\n"); + hang(); +} + +static int rk3066_dmc_setup_sdram(struct udevice *dev) +{ + struct rk3066_dmc_dram_info *priv = dev_get_priv(dev); + struct rk3066_dmc_sdram_params *params = dev_get_plat(dev); + + return rk3066_dmc_sdram_init(priv, params); +} + +static int rk3066_dmc_conv_of_plat(struct udevice *dev) +{ +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev); + struct dtd_rockchip_rk3066_dmc *of_plat = &plat->of_plat; + int ret; + + memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, + sizeof(plat->pctl_timing)); + memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, + sizeof(plat->phy_timing)); + memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); + /* RK3066 supports dual-channel, set default channel num to 2. */ + plat->num_channels = 1; + ret = regmap_init_mem_plat(dev, of_plat->reg, + ARRAY_SIZE(of_plat->reg) / 2, &plat->map); + if (ret) + return ret; + + return 0; +#else + return -EINVAL; +#endif +} + +static int rk3066_dmc_probe(struct udevice *dev) +{ + struct rk3066_dmc_dram_info *priv = dev_get_priv(dev); + + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + + if (IS_ENABLED(CONFIG_TPL_BUILD)) { + struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev); + struct regmap *map; + struct udevice *dev_clk; + int ret; + + ret = rk3066_dmc_conv_of_plat(dev); + if (ret) + return ret; + + map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); + if (IS_ERR(map)) + return PTR_ERR(map); + priv->chan[0].msch = regmap_get_range(map, 0); + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].publ = regmap_get_range(plat->map, 1); + + ret = rockchip_get_clk(&dev_clk); + if (ret) + return ret; + + priv->ddr_clk.id = CLK_DDR; + ret = clk_request(dev_clk, &priv->ddr_clk); + if (ret) + return ret; + + priv->cru = rockchip_get_cru(); + if (IS_ERR(priv->cru)) + return PTR_ERR(priv->cru); + + ret = rk3066_dmc_setup_sdram(dev); + if (ret) + return ret; + } else { + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]); + } + + return 0; +} + +static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct rk3066_dmc_dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3066_dmc_ops = { + .get_info = rk3066_dmc_get_info, +}; + +static const struct udevice_id rk3066_dmc_ids[] = { + { .compatible = "rockchip,rk3066-dmc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3066_dmc) = { + .name = "rockchip_rk3066_dmc", + .id = UCLASS_RAM, + .ops = &rk3066_dmc_ops, + .probe = rk3066_dmc_probe, + .of_match = rk3066_dmc_ids, + .priv_auto = sizeof(struct rk3066_dmc_dram_info), +#if IS_ENABLED(CONFIG_TPL_BUILD) + .plat_auto = sizeof(struct rk3066_dmc_sdram_params), +#endif +}; From c9b0051d67f133f0002ed4542fa84c9e3d99ca09 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:42 +0200 Subject: [PATCH 25/48] arm: dts: rockchip: fix rk3xxx-u-boot.dtsi The file rk3xxx-u-boot.dtsi was original only for rk3188 and SPL. With rk3066 added some nodes are also needed in TPL, so change them to u-boot,dm-pre-reloc Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3xxx-u-boot.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi index 581594c35d3..e67432fb392 100644 --- a/arch/arm/dts/rk3xxx-u-boot.dtsi +++ b/arch/arm/dts/rk3xxx-u-boot.dtsi @@ -4,7 +4,7 @@ noc: syscon@10128000 { compatible = "rockchip,rk3188-noc", "syscon"; reg = <0x10128000 0x2000>; - u-boot,dm-spl; + u-boot,dm-pre-reloc; }; dmc: dmc@20020000 { @@ -18,16 +18,16 @@ rockchip,grf = <&grf>; rockchip,pmu = <&pmu>; rockchip,noc = <&noc>; - u-boot,dm-spl; + u-boot,dm-pre-reloc; }; }; &grf { - u-boot,dm-spl; + u-boot,dm-pre-reloc; }; &pmu { - u-boot,dm-spl; + u-boot,dm-pre-reloc; }; &uart2 { From 65a28bc4db01ceed1593ced1076b6507af8a728f Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:43 +0200 Subject: [PATCH 26/48] arm: dts: rockchip: fix include rk3xxx-u-boot.dtsi Move the include for rk3xxx-u-boot.dtsi to rk3188-u-boot.dtsi to stay in line with U-boot dtsi files. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3188-u-boot.dtsi | 1 + arch/arm/dts/rk3188.dtsi | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi index 43f05b9876d..735776c16b8 100644 --- a/arch/arm/dts/rk3188-u-boot.dtsi +++ b/arch/arm/dts/rk3188-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include "rockchip-u-boot.dtsi" +#include "rk3xxx-u-boot.dtsi" &global_timer { status = "okay"; diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi index 6c1c2ff5339..6764776cce1 100644 --- a/arch/arm/dts/rk3188.dtsi +++ b/arch/arm/dts/rk3188.dtsi @@ -9,7 +9,6 @@ #include #include #include "rk3xxx.dtsi" -#include "rk3xxx-u-boot.dtsi" / { compatible = "rockchip,rk3188"; From b08f32c1595eacdbb2ae1be0c15edc1a63227e81 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:44 +0200 Subject: [PATCH 27/48] arm: dts: rockchip: add rk3066a.dtsi In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Add rk3066a.dtsi. Move U-boot specific things in a rk3066a-u-boot.dtsi file. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3066a-u-boot.dtsi | 4 + arch/arm/dts/rk3066a.dtsi | 879 +++++++++++++++++++++++++++++++ 2 files changed, 883 insertions(+) create mode 100644 arch/arm/dts/rk3066a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3066a.dtsi diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi new file mode 100644 index 00000000000..bc6e609d02b --- /dev/null +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rockchip-u-boot.dtsi" +#include "rk3xxx-u-boot.dtsi" diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi new file mode 100644 index 00000000000..c25b9695db4 --- /dev/null +++ b/arch/arm/dts/rk3066a.dtsi @@ -0,0 +1,879 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#include +#include +#include +#include +#include "rk3xxx.dtsi" + +/ { + compatible = "rockchip,rk3066a"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + operating-points = + /* kHz uV */ + <1416000 1300000>, + <1200000 1175000>, + <1008000 1125000>, + <816000 1125000>, + <600000 1100000>, + <504000 1100000>, + <312000 1075000>; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop0_out>, <&vop1_out>; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x10000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + + vop0: vop@1010c000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010c000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC0>, + <&cru DCLK_LCDC0>, + <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, + <&cru SRST_LCDC0_AHB>, + <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop0_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop0_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop0>; + }; + }; + }; + + vop1: vop@1010e000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010e000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, + <&cru SRST_LCDC1_AHB>, + <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop1_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop1_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop1>; + }; + }; + }; + + hdmi: hdmi@10116000 { + compatible = "rockchip,rk3066-hdmi"; + reg = <0x10116000 0x2000>; + interrupts = ; + clocks = <&cru HCLK_HDMI>; + clock-names = "hclk"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; + power-domains = <&power RK3066_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vop0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop0_out_hdmi>; + }; + + hdmi_in_vop1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vop1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + i2s0: i2s@10118000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x10118000 0x2000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 4>, <&dmac1_s 5>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1: i2s@1011a000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2: i2s@1011c000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011c000 0x2000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 9>, <&dmac1_s 10>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + assigned-clock-rates = <400000000>, <594000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>; + }; + + timer2: timer@2000e000 { + compatible = "snps,dw-apb-timer"; + reg = <0x2000e000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; + clock-names = "timer", "pclk"; + }; + + efuse: efuse@20010000 { + compatible = "rockchip,rk3066a-efuse"; + reg = <0x20010000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + + timer0: timer@20038000 { + compatible = "snps,dw-apb-timer"; + reg = <0x20038000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + + timer1: timer@2003a000 { + compatible = "snps,dw-apb-timer"; + reg = <0x2003a000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; + clock-names = "timer", "pclk"; + }; + + tsadc: tsadc@20060000 { + compatible = "rockchip,rk3066-tsadc"; + reg = <0x20060000 0x100>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "saradc", "apb_pclk"; + interrupts = ; + #io-channel-cells = <1>; + resets = <&cru SRST_TSADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO6>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emac { + emac_xfer: emac-xfer { + rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ + <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ + <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ + <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ + <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ + <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ + <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ + <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ + <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; + }; + + emmc_rst: emmc-rst { + rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; + }; + + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, + <2 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, + <2 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, + <3 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, + <3 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, + <1 RK_PA1 1 &pcfg_pull_default>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, + <1 RK_PA5 1 &pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, + <3 RK_PD4 1 &pcfg_pull_default>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, + <3 RK_PB3 1 &pcfg_pull_default>, + <3 RK_PB4 1 &pcfg_pull_default>, + <3 RK_PB5 1 &pcfg_pull_default>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, + <3 RK_PC2 1 &pcfg_pull_default>, + <3 RK_PC3 1 &pcfg_pull_default>, + <3 RK_PC4 1 &pcfg_pull_default>; + }; + }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, + <0 RK_PB0 1 &pcfg_pull_default>, + <0 RK_PB1 1 &pcfg_pull_default>, + <0 RK_PB2 1 &pcfg_pull_default>, + <0 RK_PB3 1 &pcfg_pull_default>, + <0 RK_PB4 1 &pcfg_pull_default>, + <0 RK_PB5 1 &pcfg_pull_default>, + <0 RK_PB6 1 &pcfg_pull_default>, + <0 RK_PB7 1 &pcfg_pull_default>; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, + <0 RK_PC1 1 &pcfg_pull_default>, + <0 RK_PC2 1 &pcfg_pull_default>, + <0 RK_PC3 1 &pcfg_pull_default>, + <0 RK_PC4 1 &pcfg_pull_default>, + <0 RK_PC5 1 &pcfg_pull_default>; + }; + }; + + i2s2 { + i2s2_bus: i2s2-bus { + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, + <0 RK_PD1 1 &pcfg_pull_default>, + <0 RK_PD2 1 &pcfg_pull_default>, + <0 RK_PD3 1 &pcfg_pull_default>, + <0 RK_PD4 1 &pcfg_pull_default>, + <0 RK_PD5 1 &pcfg_pull_default>; + }; + }; + }; +}; + +&gpu { + compatible = "rockchip,rk3066-mali", "arm,mali-400"; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + power-domains = <&power RK3066_PD_GPU>; +}; + +&grf { + compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; + + usbphy: usbphy { + compatible = "rockchip,rk3066a-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@17c { + reg = <0x17c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@188 { + reg = <0x188>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + +&mmc0 { + clock-frequency = <50000000>; + dmas = <&dmac2 1>; + dma-names = "rx-tx"; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; +}; + +&mmc1 { + dmas = <&dmac2 3>; + dma-names = "rx-tx"; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; +}; + +&emmc { + dmas = <&dmac2 4>; + dma-names = "rx-tx"; +}; + +&pmu { + power: power-controller { + compatible = "rockchip,rk3066-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3066_PD_VIO { + reg = ; + clocks = <&cru ACLK_LCDC0>, + <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC0>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC0>, + <&cru HCLK_LCDC1>, + <&cru SCLK_CIF1>, + <&cru ACLK_CIF1>, + <&cru HCLK_CIF1>, + <&cru SCLK_CIF0>, + <&cru ACLK_CIF0>, + <&cru HCLK_CIF0>, + <&cru HCLK_HDMI>, + <&cru ACLK_IPP>, + <&cru HCLK_IPP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_lcdc0>, + <&qos_lcdc1>, + <&qos_cif0>, + <&qos_cif1>, + <&qos_ipp>, + <&qos_rga>; + #power-domain-cells = <0>; + }; + + power-domain@RK3066_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru HCLK_VEPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3066_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + +&uart0 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac1_s 0>, <&dmac1_s 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac1_s 2>, <&dmac1_s 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac2 6>, <&dmac2 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac2 8>, <&dmac2 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; + +&vpu { + power-domains = <&power RK3066_PD_VIDEO>; +}; + +&wdt { + compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; +}; + +&emac { + compatible = "rockchip,rk3066-emac"; +}; From 41ed3912c0fd5b2c5a0e20e524aae28dc062769e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:45 +0200 Subject: [PATCH 28/48] arm: dts: rockchip: add rk3066a-mk808.dts MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, HDMI and a micro-SD card slot. It also includes on-board NAND and 1GB of SDRAM. Add rk3066a-mk808.dts. Move U-boot specific things in a rk3066a-mk808-u-boot.dtsi file. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 3 + arch/arm/dts/rk3066a-mk808-u-boot.dtsi | 49 ++++++ arch/arm/dts/rk3066a-mk808.dts | 216 +++++++++++++++++++++++++ 3 files changed, 268 insertions(+) create mode 100644 arch/arm/dts/rk3066a-mk808-u-boot.dtsi create mode 100644 arch/arm/dts/rk3066a-mk808.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index df7b4addf99..2a0efd8edad 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -90,6 +90,9 @@ dtb-$(CONFIG_ROCKCHIP_PX30) += \ dtb-$(CONFIG_ROCKCHIP_RK3036) += \ rk3036-sdk.dtb +dtb-$(CONFIG_ROCKCHIP_RK3066) += \ + rk3066a-mk808.dtb + dtb-$(CONFIG_ROCKCHIP_RK3128) += \ rk3128-evb.dtb diff --git a/arch/arm/dts/rk3066a-mk808-u-boot.dtsi b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi new file mode 100644 index 00000000000..e0aa929fcef --- /dev/null +++ b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3066a-u-boot.dtsi" + +/ { + config { + u-boot,boot-led = "mk808:blue:power"; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&dmc { + compatible = "rockchip,rk3066-dmc", "syscon"; + rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6 + 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4 + 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0 + 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0 + 0x4 0x0>; + rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00 + 0x220 0x40 0x0 0x0>; + rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>; +}; + +&mmc0 { + fifo-mode; + max-frequency = <4000000>; + u-boot,dm-spl; + u-boot,spl-fifo-mode; +}; + +&mmc1 { + status = "disabled"; +}; + +&noc { + compatible = "rockchip,rk3066-noc", "syscon"; +}; + +&timer2 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts new file mode 100644 index 00000000000..667d57a4ff4 --- /dev/null +++ b/arch/arm/dts/rk3066a-mk808.dts @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Paweł Jarosz + */ + +/dts-v1/; +#include +#include "rk3066a.dtsi" + +/ { + model = "Rikomagic MK808"; + compatible = "rikomagic,mk808", "rockchip,rk3066a"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@60000000 { + reg = <0x60000000 0x40000000>; + device_type = "memory"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <2500000>; + poll-interval = <100>; + + recovery { + label = "recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue_led: led-0 { + label = "mk808:blue:power"; + gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "default-on"; + }; + }; + + hdmi_con { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vcc_2v5: vcc-2v5 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&host_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&otg_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "vcc_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_wifi: sdio-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wifi_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vop1 { + status = "disabled"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + non-removable; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_wifi>; + status = "okay"; +}; + +&pinctrl { + usb-host { + host_drv: host-drv { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + usb-otg { + otg_drv: otg-drv { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdio { + wifi_pwr: wifi-pwr { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_2v5>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&vop0 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; From 0034f1da5ae18cb21eb2012b1e175147118834cf Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:46 +0200 Subject: [PATCH 29/48] rockchip: tools: add rk3066 support to rkcommon.c Add rk3066 support to rkcommon.c Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- tools/rkcommon.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index ff62c75caad..0db45c2d41c 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -123,6 +123,7 @@ struct spl_info { static struct spl_info spl_infos[] = { { "px30", "RK33", 0x2800, false, RK_HEADER_V1 }, { "rk3036", "RK30", 0x1000, false, RK_HEADER_V1 }, + { "rk3066", "RK30", 0x8000 - 0x800, true, RK_HEADER_V1 }, { "rk3128", "RK31", 0x1800, false, RK_HEADER_V1 }, { "rk3188", "RK31", 0x8000 - 0x800, true, RK_HEADER_V1 }, { "rk322x", "RK32", 0x8000 - 0x1000, false, RK_HEADER_V1 }, From 33f4750783080302afd8f00bb07bd18d6e94f073 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:47 +0200 Subject: [PATCH 30/48] rockchip: rk3066: add core support Add the core architecture code for the rk3066. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rk3066/boot0.h | 8 +++ arch/arm/include/asm/arch-rk3066/gpio.h | 8 +++ arch/arm/include/asm/arch-rk3066/timer.h | 6 ++ arch/arm/mach-rockchip/Kconfig | 23 ++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3066/Kconfig | 30 ++++++++++ arch/arm/mach-rockchip/rk3066/Makefile | 5 ++ arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 +++++++++++ arch/arm/mach-rockchip/rk3066/rk3066.c | 49 +++++++++++++++++ arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 55 +++++++++++++++++++ include/configs/mk808.h | 9 +++ include/configs/rk3066_common.h | 47 ++++++++++++++++ 12 files changed, 274 insertions(+) create mode 100644 arch/arm/include/asm/arch-rk3066/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3066/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3066/timer.h create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c create mode 100644 arch/arm/mach-rockchip/rk3066/rk3066.c create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c create mode 100644 include/configs/mk808.h create mode 100644 include/configs/rk3066_common.h diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h new file mode 100644 index 00000000000..28c0fb9a4c6 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/gpio.h b/arch/arm/include/asm/arch-rk3066/gpio.h new file mode 100644 index 00000000000..a4a3b3289c2 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/timer.h b/arch/arm/include/asm/arch-rk3066/timer.h new file mode 100644 index 00000000000..3bb39428cd6 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/timer.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_TIMER_H__ +#define __ASM_ARCH_TIMER_H__ + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 811964973ae..18aff5480ba 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -35,6 +35,28 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3066 + bool "Support Rockchip RK3066" + select CPU_V7A + select SPL_BOARD_INIT if SPL + select SUPPORT_SPL + select SUPPORT_TPL + select SPL + select TPL + select TPL_ROCKCHIP_BACK_TO_BROM + select TPL_ROCKCHIP_EARLYRETURN_TO_BROM + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SERIAL + imply TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SERIAL + help + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9 + including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two + video interfaces, several memory options and video codec support. + Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, + UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A @@ -405,6 +427,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3066/Kconfig" source "arch/arm/mach-rockchip/rk3128/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk322x/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 00aef0ecee6..6c1c7b8a108 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o obj-$(CONFIG_ROCKCHIP_PX30) += px30/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig new file mode 100644 index 00000000000..335f49bc557 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -0,0 +1,30 @@ +if ROCKCHIP_RK3066 + +config ROCKCHIP_BOOT_MODE_REG + default 0x20004040 + +config SYS_SOC + default "rk3066" + +config SYS_MALLOC_F_LEN + default 0x0800 + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_SERIAL + default y + +config TPL_LIBCOMMON_SUPPORT + default y + +config TPL_LIBGENERIC_SUPPORT + default y + +config TPL_SERIAL + default y + +endif diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile new file mode 100644 index 00000000000..9e2a9d4b0aa --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += clk_rk3066.o +obj-y += rk3066.o +obj-y += syscon_rk3066.o diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c new file mode 100644 index 00000000000..c47526dca5d --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3066a_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3066_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c new file mode 100644 index 00000000000..78c7d894f90 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include + +#define GRF_BASE 0x20008000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000", + [BROM_BOOTSOURCE_SD] = "/mmc@10214000", +}; + +void board_debug_uart_init(void) +{ + struct rk3066_grf * const grf = (void *)GRF_BASE; + + /* Enable early UART on the RK3066 */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B0_MASK, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); +} + +void spl_board_init(void) +{ + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return; + + if (IS_ENABLED(CONFIG_SPL_DM_MMC)) { + struct rk3066_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B0_MASK | GPIO3B1_MASK | GPIO3B2_MASK | + GPIO3B3_MASK | GPIO3B4_MASK | GPIO3B5_MASK | + GPIO3B6_MASK, + GPIO3B0_SDMMC0_CLKOUT << GPIO3B0_SHIFT | + GPIO3B1_SDMMC0_CMD << GPIO3B1_SHIFT | + GPIO3B2_SDMMC0_DATA0 << GPIO3B2_SHIFT | + GPIO3B3_SDMMC0_DATA1 << GPIO3B3_SHIFT | + GPIO3B4_SDMMC0_DATA2 << GPIO3B4_SHIFT | + GPIO3B5_SDMMC0_DATA3 << GPIO3B5_SHIFT | + GPIO3B6_SDMMC0_DECTN << GPIO3B6_SHIFT); + } +} diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c new file mode 100644 index 00000000000..a598f6400de --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include + +static const struct udevice_id rk3066_syscon_ids[] = { + { .compatible = "rockchip,rk3066-noc", .data = ROCKCHIP_SYSCON_NOC }, + { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3066) = { + .name = "rk3066_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids, +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3066_syscon_bind_of_plat(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3066_noc) = { + .name = "rockchip_rk3066_noc", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids, + .bind = rk3066_syscon_bind_of_plat, +}; + +U_BOOT_DRIVER(rockchip_rk3066_grf) = { + .name = "rockchip_rk3066_grf", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids + 1, + .bind = rk3066_syscon_bind_of_plat, +}; + +U_BOOT_DRIVER(rockchip_rk3066_pmu) = { + .name = "rockchip_rk3066_pmu", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids + 2, + .bind = rk3066_syscon_bind_of_plat, +}; +#endif diff --git a/include/configs/mk808.h b/include/configs/mk808.h new file mode 100644 index 00000000000..e2ab2b512c8 --- /dev/null +++ b/include/configs/mk808.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include + +#endif diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h new file mode 100644 index 00000000000..be7d644e1e5 --- /dev/null +++ b/include/configs/rk3066_common.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_RK3066_COMMON_H +#define __CONFIG_RK3066_COMMON_H + +#include +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 256 + +#define CONFIG_SYS_INIT_SP_ADDR 0x78000000 + +#define CONFIG_IRAM_BASE 0x10080000 + +#define CONFIG_SPL_MAX_SIZE 0x32000 + +#define CONFIG_SPL_STACK 0x1008FFFF + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define SDRAM_BANK_SIZE (1024UL << 20UL) +#define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6fffffff\0" \ + "initrd_high=0x6fffffff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#endif From 62fcd72ef29c62961a50f77a6427e454627762de Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:48 +0200 Subject: [PATCH 31/48] rockchip: rk3066: add Rikomagic MK808 board MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, HDMI and a micro-SD card slot. It also includes on-board NAND and 1GB of SDRAM. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3066/Kconfig | 9 +++++++++ board/rikomagic/mk808/Kconfig | 15 +++++++++++++++ board/rikomagic/mk808/MAINTAINERS | 6 ++++++ board/rikomagic/mk808/Makefile | 3 +++ board/rikomagic/mk808/mk808.c | 3 +++ 5 files changed, 36 insertions(+) create mode 100644 board/rikomagic/mk808/Kconfig create mode 100644 board/rikomagic/mk808/MAINTAINERS create mode 100644 board/rikomagic/mk808/Makefile create mode 100644 board/rikomagic/mk808/mk808.c diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig index 335f49bc557..95d7fc8a291 100644 --- a/arch/arm/mach-rockchip/rk3066/Kconfig +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -1,5 +1,12 @@ if ROCKCHIP_RK3066 +config TARGET_MK808 + bool "MK808" + help + MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, + HDMI and a micro-SD card slot. It also includes on-board NAND + and 1GB of SDRAM. + config ROCKCHIP_BOOT_MODE_REG default 0x20004040 @@ -27,4 +34,6 @@ config TPL_LIBGENERIC_SUPPORT config TPL_SERIAL default y +source "board/rikomagic/mk808/Kconfig" + endif diff --git a/board/rikomagic/mk808/Kconfig b/board/rikomagic/mk808/Kconfig new file mode 100644 index 00000000000..4abad7e7500 --- /dev/null +++ b/board/rikomagic/mk808/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MK808 + +config SYS_BOARD + default "mk808" + +config SYS_VENDOR + default "rikomagic" + +config SYS_CONFIG_NAME + default "mk808" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rikomagic/mk808/MAINTAINERS b/board/rikomagic/mk808/MAINTAINERS new file mode 100644 index 00000000000..b3ef6adb917 --- /dev/null +++ b/board/rikomagic/mk808/MAINTAINERS @@ -0,0 +1,6 @@ +MK808 +M: Johan Jonker +S: Maintained +F: board/rikomagic/mk808 +F: configs/mk808_defconfig +F: include/configs/mk808.h diff --git a/board/rikomagic/mk808/Makefile b/board/rikomagic/mk808/Makefile new file mode 100644 index 00000000000..a4d16884dfc --- /dev/null +++ b/board/rikomagic/mk808/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += mk808.o diff --git a/board/rikomagic/mk808/mk808.c b/board/rikomagic/mk808/mk808.c new file mode 100644 index 00000000000..e0bfc6f3311 --- /dev/null +++ b/board/rikomagic/mk808/mk808.c @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include From ccd8ab374e2f072b0081b3d4f7bc298b8af2533a Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:49 +0200 Subject: [PATCH 32/48] rockchip: rk3066: add mk808_defconfig This commit adds the default configuration file and relevant description for a MK808 board. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- configs/mk808_defconfig | 102 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 configs/mk808_defconfig diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig new file mode 100644 index 00000000000..20bca75adfc --- /dev/null +++ b/configs/mk808_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y +# CONFIG_SPL_SYS_THUMB_BUILD is not set +# CONFIG_TPL_SYS_THUMB_BUILD is not set +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x60408000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808" +CONFIG_SPL_TEXT_BASE=0x60000000 +CONFIG_ROCKCHIP_RK3066=y +# CONFIG_ROCKCHIP_STIMER is not set +CONFIG_TPL_TEXT_BASE=0x10080C04 +CONFIG_TPL_MAX_SIZE=32764 +CONFIG_TPL_STACK=0x1008FFFF +CONFIG_TARGET_MK808=y +CONFIG_SPL_STACK_R_ADDR=0x70000000 +CONFIG_DEBUG_UART_BASE=0x20064000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SYS_LOAD_ADDR=0x70800800 +CONFIG_SPL_PAYLOAD="u-boot.bin" +CONFIG_DEBUG_UART=y +CONFIG_SD_BOOT=y +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2 +CONFIG_TPL_NEEDS_SEPARATE_STACK=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_SPL_OF_PLATDATA=y +CONFIG_TPL_OF_PLATDATA=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_TPL_DM=y +# CONFIG_DM_WARN is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +# CONFIG_SIMPLE_BUS is not set +# CONFIG_SPL_SIMPLE_BUS is not set +# CONFIG_TPL_BLK is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_TPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +# CONFIG_SPL_DM_I2C is not set +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_TPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +# CONFIG_TPL_OF_LIBFDT is not set From ed33f8c4e3ddeee897326dc0e9760175a13716d9 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:50 +0200 Subject: [PATCH 33/48] doc: rockchip: restyle rockchip.rst With more text coming to the rockchip.rst document, give it a restyle first. Changed: sort build examples alphabetically add git clone example fix bash examples fix phrases (grammer) fix typos Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- doc/board/rockchip/rockchip.rst | 140 ++++++++++++++++++++------------ 1 file changed, 89 insertions(+), 51 deletions(-) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index a75e60b9fa3..1a4de7ff1e5 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -13,7 +13,7 @@ and it's usage steps. Rockchip boards --------------- -Rockchip is SoC solutions provider for tablets & PCs, streaming media +Rockchip is a SoC solutions provider for tablets & PCs, streaming media TV boxes, AI audio & vision, IoT hardware. A wide range of Rockchip SoCs with associated boards are supported in @@ -85,42 +85,58 @@ Building TF-A ^^^^ -TF-A would require to build for ARM64 Rockchip SoCs platforms. +TF-A is required when building ARM64 Rockchip SoCs images. -To build TF-A:: +To build TF-A: - git clone https://github.com/ARM-software/arm-trusted-firmware.git +.. code-block:: bash + + git clone --depth 1 https://github.com/ARM-software/arm-trusted-firmware.git cd arm-trusted-firmware make realclean make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 + cd .. Specify the PLAT= with desired Rockchip platform to build TF-A for. U-Boot ^^^^^^ -To build rk3328 boards:: +.. code-block:: bash - export BL31=/path/to/arm-trusted-firmware/to/bl31.elf - make evb-rk3328_defconfig - make + git clone --depth 1 https://source.denx.de/u-boot/u-boot.git + cd u-boot -To build rk3288 boards:: +To build rk3288 boards: + +.. code-block:: bash make evb-rk3288_defconfig - make + make CROSS_COMPILE=arm-linux-gnueabihf- -To build rk3368 boards:: +To build rk3328 boards: - export BL31=/path/to/arm-trusted-firmware/to/bl31.elf +.. code-block:: bash + + export BL31=../arm-trusted-firmware/build/rk3328/release/bl31/bl31.elf + make evb-rk3328_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- + +To build rk3368 boards: + +.. code-block:: bash + + export BL31=../arm-trusted-firmware/build/rk3368/release/bl31/bl31.elf make evb-px5_defconfig - make + make CROSS_COMPILE=aarch64-linux-gnu- -To build rk3399 boards:: +To build rk3399 boards: - export BL31=/path/to/arm-trusted-firmware/to/bl31.elf +.. code-block:: bash + + export BL31=../arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf make evb-rk3399_defconfig - make + make CROSS_COMPILE=aarch64-linux-gnu- Flashing -------- @@ -131,10 +147,12 @@ Flashing SD Card ^^^^^^^ -All Rockchip platforms, except rk3128 (which doesn't use SPL) are now -supporting single boot image using binman and pad_cat. +All Rockchip platforms (except rk3128 which doesn't use SPL) are now +supporting a single boot image using binman and pad_cat. -To write an image that boots from an SD card (assumed to be /dev/sda):: +To write an image that boots from a SD card (assumed to be /dev/sda): + +.. code-block:: bash sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64 sync @@ -144,45 +162,60 @@ eMMC eMMC flash would probe on mmc0 in most of the Rockchip platforms. -Create GPT partition layout as defined in configurations:: +Create GPT partition layout as defined in $partitions: + +.. code-block:: bash mmc dev 0 gpt write mmc 0 $partitions -Connect the USB-OTG cable between host and target device. +Connect the USB-OTG cable between the host and a target device. -Launch fastboot at target:: +Launch fastboot on the target with: + +.. code-block:: bash fastboot 0 -Upon successful gadget connection,host show the USB device like:: +Upon a successful gadget connection the host shows the USB device with: + +.. code-block:: bash lsusb - Bus 001 Device 020: ID 2207:330c Fuzhou Rockchip Electronics Company RK3399 in Mask ROM mode + # Bus 001 Device 020: ID 2207:330c Fuzhou Rockchip Electronics Company RK3399 in Mask ROM mode -Program the flash:: +Program the flash with: + +.. code-block:: bash sudo fastboot -i 0x2207 flash loader1 idbloader.img sudo fastboot -i 0x2207 flash loader2 u-boot.itb -Note: for Rockchip 32-bit platforms the U-Boot proper image +Note: + +For Rockchip 32-bit platforms the U-Boot proper image is u-boot-dtb.img SPI ^^^ -Generating idbloader for SPI boot would require to input a multi image -image format to mkimage tool instead of concerting (like for MMC boot). +The SPI boot method requires the generation of idbloader.img with help of the mkimage tool. -SPL-alone SPI boot image:: +SPL-alone SPI boot image: + +.. code-block:: bash ./tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader.img -TPL+SPL SPI boot image:: +TPL+SPL SPI boot image: + +.. code-block:: bash ./tools/mkimage -n rk3399 -T rkspi -d tpl/u-boot-tpl.bin:spl/u-boot-spl.bin idbloader.img -Copy SPI boot images into SD card and boot from SD:: +Copy SPI boot images into SD card and boot from SD: + +.. code-block:: bash sf probe load mmc 1:1 $kernel_addr_r idbloader.img @@ -195,35 +228,42 @@ Copy SPI boot images into SD card and boot from SD:: 2. Package the image with Rockchip miniloader --------------------------------------------- -Image package with Rockchip miniloader requires robin [1]. +Image package with Rockchip miniloader requires rkbin [1]. -Create idbloader.img +.. code-block:: bash -.. code-block:: none + cd .. + git clone --depth 1 https://github.com/rockchip-linux/rkbin - cd u-boot - ./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin idbloader.img - cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img - sudo dd if=idbloader.img of=/dev/sda seek=64 +Create idbloader.img: -Create trust.img +.. code-block:: bash -.. code-block:: none + cd u-boot + ./tools/mkimage -n px30 -T rksd -d ../rkbin/bin/rk33/px30_ddr_333MHz_v1.16.bin idbloader.img + cat ../rkbin/bin/rk33/px30_miniloader_v1.31.bin >> idbloader.img + sudo dd if=idbloader.img of=/dev/sda seek=64 - cd rkbin - ./tools/trust_merger RKTRUST/PX30TRUST.ini - sudo dd if=trust.img of=/dev/sda seek=24576 +Create trust.img: -Create uboot.img +.. code-block:: bash -.. code-block:: none + cd ../rkbin + ./tools/trust_merger RKTRUST/PX30TRUST.ini + sudo dd if=trust.img of=/dev/sda seek=24576 - rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x200000 - sudo dd if=uboot.img of=/dev/sda seek=16384 +Create uboot.img [2]: + +.. code-block:: bash + + cd ../u-boot + ../rkbin/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x200000 + sudo dd if=uboot.img of=/dev/sda seek=16384 Note: -1. 0x200000 is load address and it's an optional in some platforms. -2. rkbin binaries are kept on updating, so would recommend to use the latest versions. + +1. rkbin binaries are regularly updated, so it would be recommended to use the latest version. +2. 0x200000 is a load address and is an option for some platforms. TODO ---- @@ -233,7 +273,5 @@ TODO - Document SPI flash boot - Add missing SoC's with it boards list -[1] https://github.com/rockchip-linux/rkbin - .. Jagan Teki .. Wednesday 28 October 2020 06:47:26 PM IST From 0c99c6e63ef3fcfdf2c21cbface359752164a085 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:51 +0200 Subject: [PATCH 34/48] doc: rockchip: add px30/rk3326 boards and examples There are several PX30/RK3326 boards in use without mentioning in rockchip.rst. Add boards and examples. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- doc/board/rockchip/rockchip.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 1a4de7ff1e5..9b94abe25e7 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -21,6 +21,12 @@ mainline U-Boot. List of mainline supported Rockchip boards: +* px30 + - Rockchip Evb-PX30 (evb-px30) + - Engicam PX30.Core C.TOUCH 2.0 (px30-core-ctouch2-px30) + - Engicam PX30.Core C.TOUCH 2.0 10.1 (px30-core-ctouch2-of10-px30) + - Engicam PX30.Core EDIMM2.2 Starter Kit (px30-core-edimm2.2-px30) + - Firefly Core-PX30-JD4 (firefly-px30) * rk3036 - Rockchip Evb-RK3036 (evb-rk3036) - Kylin (kylin_rk3036) @@ -46,6 +52,8 @@ List of mainline supported Rockchip boards: * rk3308 - Rockchip Evb-RK3308 (evb-rk3308) - Roc-cc-RK3308 (roc-cc-rk3308) +* rk3326 + - ODROID-GO Advance (odroid-go2) * rk3328 - Rockchip Evb-RK3328 (evb-rk3328) - Pine64 Rock64 (rock64-rk3328) @@ -107,6 +115,14 @@ U-Boot git clone --depth 1 https://source.denx.de/u-boot/u-boot.git cd u-boot +To build px30 boards: + +.. code-block:: bash + + export BL31=../arm-trusted-firmware/build/px30/release/bl31/bl31.elf + make evb-px30_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- + To build rk3288 boards: .. code-block:: bash From c57677b06f550502ab00d74b4213f220a68ebfc0 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:52 +0200 Subject: [PATCH 35/48] doc: rockchip: add rk3066 Rikomagic MK808 Add rk3066 Rikomagic MK808 to the list of mainline supported Rockchip boards. Include instructions for creating and programming images to NAND and SD card. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- doc/board/rockchip/rockchip.rst | 108 ++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9b94abe25e7..4ca7b00b1fb 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -30,6 +30,8 @@ List of mainline supported Rockchip boards: * rk3036 - Rockchip Evb-RK3036 (evb-rk3036) - Kylin (kylin_rk3036) +* rk3066 + - Rikomagic MK808 (mk808) * rk3128 - Rockchip Evb-RK3128 (evb-rk3128) * rk3188 @@ -123,6 +125,13 @@ To build px30 boards: make evb-px30_defconfig make CROSS_COMPILE=aarch64-linux-gnu- +To build rk3066 boards: + +.. code-block:: bash + + make mk808_defconfig + make CROSS_COMPILE=arm-linux-gnueabihf- + To build rk3288 boards: .. code-block:: bash @@ -281,6 +290,105 @@ Note: 1. rkbin binaries are regularly updated, so it would be recommended to use the latest version. 2. 0x200000 is a load address and is an option for some platforms. +3. Package the RK3066 image with U-Boot TPL/SPL on NAND +------------------------------------------------------- + +Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support. +If all other boot options fail then it enters into a BootROM mode on the USB OTG port. +This method loads TPL/SPL on NAND with U-boot and kernel on SD card. + +SD Card +^^^^^^^ + +U-boot expects a GPT partition map and a boot directory structure with files on the SD card. + +.. code-block:: none + + Partition Map for MMC device 0 -- Partition Type: EFI + Part Start LBA End LBA Name + 1 0x00000040 0x00001f7f "loader1" + 2 0x00004000 0x00005fff "loader2" + 3 0x00006000 0x00007fff "trust" + 4 0x00008000 0x0003ffff "boot" + 5 0x00040000 0x00ed7fde "rootfs" + +Make sure boot and esp flag are set for the boot partition. +Loader1 partition is not used by RK3066. + +Boot partition: + +.. code-block:: none + + extlinux + extlinux.conf + + zImage + rk3066a-mk808.dtb + +To write a U-boot image to the SD card (assumed to be /dev/sda): + +.. code-block:: bash + + sudo dd if=u-boot-dtb.img of=/dev/sda seek=16384 + sync + +NAND +^^^^ + +Bring device in BootROM mode: + +If bricked and no BootROM mode shows up then connect pin 8 and 9 of the NAND flash +with a needle while reconnecting to the USB OTG port to a PC. + +Show connected devices with: + +.. code-block:: bash + + lsusb + # Bus 001 Device 004: ID 2207:300a Fuzhou Rockchip Electronics Company RK3066 in Mask ROM mode + + +Create NAND image: + +Size of SPL and TPL must be aligned to 2kb. + +Program with commands in a bash script ./flash.sh: + +.. code-block:: bash + + #!/bin/sh + + printf "RK30" > tplspl.bin + dd if=u-boot-tpl.bin >> tplspl.bin + truncate -s %2048 tplspl.bin + truncate -s %2048 u-boot-spl.bin + ../tools/boot_merger --verbose config-flash.ini + ../tools/upgrade_tool ul ./RK30xxLoader_uboot.bin + +config-flash.ini: + +.. code-block:: none + + [CHIP_NAME] + NAME=RK30 + [VERSION] + MAJOR=2 + MINOR=21 + [CODE471_OPTION] + NUM=1 + Path1=30_LPDDR2_300MHz_DD.bin + [CODE472_OPTION] + NUM=1 + Path1=rk30usbplug.bin + [LOADER_OPTION] + NUM=2 + LOADER1=FlashData + LOADER2=FlashBoot + FlashData=tplspl.bin + FlashBoot=u-boot-spl.bin + [OUTPUT] + PATH=RK30xxLoader_uboot.bin + TODO ---- From 3c48a6246027a06453cb6519ce7a4edbce499c9d Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:32 +0200 Subject: [PATCH 36/48] rockchip: rk3228-power: sync power domain dt-binding header from Linux In order to update the DT for rk3228 sync the power domain dt-binding header. This is the state as of v5.17 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- include/dt-bindings/power/rk3228-power.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/power/rk3228-power.h diff --git a/include/dt-bindings/power/rk3228-power.h b/include/dt-bindings/power/rk3228-power.h new file mode 100644 index 00000000000..6a8dc1bf76c --- /dev/null +++ b/include/dt-bindings/power/rk3228-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__ +#define __DT_BINDINGS_POWER_RK3228_POWER_H__ + +/** + * RK3228 idle id Summary. + */ + +#define RK3228_PD_CORE 0 +#define RK3228_PD_MSCH 1 +#define RK3228_PD_BUS 2 +#define RK3228_PD_SYS 3 +#define RK3228_PD_VIO 4 +#define RK3228_PD_VOP 5 +#define RK3228_PD_VPU 6 +#define RK3228_PD_RKVDEC 7 +#define RK3228_PD_GPU 8 +#define RK3228_PD_PERI 9 +#define RK3228_PD_GMAC 10 + +#endif From 6914ef8e6773e490d4c6b412d21143b27bb00b02 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:33 +0200 Subject: [PATCH 37/48] rockchip: rk3228-cru: sync the clock dt-binding header from Linux In order to update the DT for rk3228 sync the clock dt-binding header. This is the state as of v5.17 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- include/dt-bindings/clock/rk3228-cru.h | 54 +++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 1217d5239f5..de550ea56ee 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H @@ -39,6 +40,7 @@ #define SCLK_EMMC_DRV 117 #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 +#define SCLK_SDIO_SRC 120 #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 @@ -51,6 +53,18 @@ #define SCLK_MAC_TX 130 #define SCLK_MAC_PHY 131 #define SCLK_MAC_OUT 132 +#define SCLK_VDEC_CABAC 133 +#define SCLK_VDEC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_HDCP 136 +#define SCLK_HDMI_CEC 137 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_HSADC 140 +#define SCLK_WIFI 141 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_HDMI_PHY 144 /* dclk gates */ #define DCLK_VOP 190 @@ -58,15 +72,32 @@ /* aclk gates */ #define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VPU_PRE 196 +#define ACLK_RKVDEC_PRE 197 +#define ACLK_RGA_PRE 198 +#define ACLK_IEP_PRE 199 +#define ACLK_HDCP_PRE 200 +#define ACLK_VOP_PRE 201 +#define ACLK_VPU 202 +#define ACLK_RKVDEC 203 +#define ACLK_IEP 204 +#define ACLK_RGA 205 +#define ACLK_HDCP 206 #define ACLK_PERI 210 #define ACLK_VOP 211 #define ACLK_GMAC 212 +#define ACLK_GPU 213 /* pclk gates */ #define PCLK_GPIO0 320 #define PCLK_GPIO1 321 #define PCLK_GPIO2 322 #define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_HDCP 325 +#define PCLK_EFUSE_1024 326 +#define PCLK_EFUSE_256 327 #define PCLK_GRF 329 #define PCLK_I2C0 332 #define PCLK_I2C1 333 @@ -79,6 +110,7 @@ #define PCLK_TSADC 344 #define PCLK_PWM 350 #define PCLK_TIMER 353 +#define PCLK_CPU 354 #define PCLK_PERI 363 #define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_PHY 365 @@ -94,6 +126,24 @@ #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 +#define HCLK_CPU 460 +#define HCLK_VPU_PRE 461 +#define HCLK_RKVDEC_PRE 462 +#define HCLK_VIO_PRE 463 +#define HCLK_VPU 464 +#define HCLK_RKVDEC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_HDCP_MMU 470 +#define HCLK_HOST0 471 +#define HCLK_HOST1 472 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_M_CRYPTO 476 +#define HCLK_S_CRYPTO 477 #define HCLK_PERI 478 #define CLK_NR_CLKS (HCLK_PERI + 1) From d886532a7c96345c0ccf90ce715b55f297be4256 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:34 +0200 Subject: [PATCH 38/48] arm: dts: rockchip: move all rk322x u-boot specific properties in separate dtsi files In order to sync rk322x.dtsi from Linux, move all U-boot specific properties in separate dtsi files. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3229-evb-u-boot.dtsi | 28 +++++++++++++++ arch/arm/dts/rk3229-evb.dts | 17 --------- arch/arm/dts/rk322x-u-boot.dtsi | 56 +++++++++++++++++++++++++++++ arch/arm/dts/rk322x.dtsi | 37 ------------------- 4 files changed, 84 insertions(+), 54 deletions(-) create mode 100644 arch/arm/dts/rk3229-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk322x-u-boot.dtsi diff --git a/arch/arm/dts/rk3229-evb-u-boot.dtsi b/arch/arm/dts/rk3229-evb-u-boot.dtsi new file mode 100644 index 00000000000..b65149c2491 --- /dev/null +++ b/arch/arm/dts/rk3229-evb-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk322x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3 + 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4 + 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1 + 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4 + 0x0 0x924>; + rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>; + rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15 + 0 300 3 0 120>; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index 632cdc9bc3d..66a3ba23167 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -11,10 +11,6 @@ model = "Rockchip RK3229 Evaluation board"; compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - chosen { - stdout-path = &uart2; - }; - memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; @@ -38,17 +34,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3 - 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4 - 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1 - 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4 - 0x0 0x924>; - rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>; - rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15 - 0 300 3 0 120>; -}; - &gmac { assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; @@ -66,7 +51,6 @@ }; &emmc { - u-boot,dm-pre-reloc; status = "okay"; }; @@ -82,7 +66,6 @@ }; &uart2 { - u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/rk322x-u-boot.dtsi b/arch/arm/dts/rk322x-u-boot.dtsi new file mode 100644 index 00000000000..79c41e481be --- /dev/null +++ b/arch/arm/dts/rk322x-u-boot.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rockchip-u-boot.dtsi" + +/ { + bus_intmem@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x9000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x9000>; + + smp-sram@0 { + compatible = "rockchip,rk322x-smp-sram"; + reg = <0x00 0x10>; + }; + + ddr_sram: ddr-sram@1000 { + compatible = "rockchip,rk322x-ddr-sram"; + reg = <0x1000 0x8000>; + }; + }; + + dmc: dmc@11200000 { + compatible = "rockchip,rk3228-dmc", "syscon"; + reg = <0x11200000 0x3fc + 0x12000000 0x400>; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + rockchip,sram = <&ddr_sram>; + u-boot,dm-pre-reloc; + }; + + service_msch: syscon@31090000 { + compatible = "rockchip,rk3228-msch", "syscon"; + reg = <0x31090000 0x2000>; + u-boot,dm-pre-reloc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&emmc { + max-frequency = <150000000>; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + max-frequency = <150000000>; +}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 4a8be5dabbd..3245da3c6af 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -107,22 +107,6 @@ #clock-cells = <0>; }; - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x9000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x9000>; - smp-sram@0 { - compatible = "rockchip,rk322x-smp-sram"; - reg = <0x00 0x10>; - }; - ddr_sram: ddr-sram@1000 { - compatible = "rockchip,rk322x-ddr-sram"; - reg = <0x1000 0x8000>; - }; - }; - i2s1: i2s1@100b0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100b0000 0x4000>; @@ -165,7 +149,6 @@ }; grf: syscon@11000000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3228-grf", "syscon"; reg = <0x11000000 0x1000>; }; @@ -317,7 +300,6 @@ }; cru: clock-controller@110e0000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3228-cru"; reg = <0x110e0000 0x1000>; rockchip,grf = <&grf>; @@ -387,7 +369,6 @@ sdmmc: dwmmc@30000000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30000000 0x4000>; - max-frequency = <150000000>; interrupts = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; @@ -414,7 +395,6 @@ emmc: dwmmc@30020000 { compatible = "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; - max-frequency = <150000000>; interrupts = ; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; @@ -768,21 +748,4 @@ }; }; }; - - dmc: dmc@11200000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3228-dmc", "syscon"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,msch = <&service_msch>; - reg = <0x11200000 0x3fc - 0x12000000 0x400>; - rockchip,sram = <&ddr_sram>; - }; - - service_msch: syscon@31090000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3228-msch", "syscon"; - reg = <0x31090000 0x2000>; - }; }; From 6980e83c415d577d8d360a77a0d8452e9f60ceef Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:35 +0200 Subject: [PATCH 39/48] arm: dts: rockchip: sync rk322x.dtsi from Linux Sync rk322x.dtsi from Linux version 5.17. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3229-evb.dts | 2 +- arch/arm/dts/rk322x.dtsi | 844 +++++++++++++++++++++++++++++------- 2 files changed, 695 insertions(+), 151 deletions(-) diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index 66a3ba23167..d2681d1a059 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -69,6 +69,6 @@ status = "okay"; }; -&usb20_otg { +&usb_otg { status = "okay"; }; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 3245da3c6af..c5330c19864 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -1,7 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include #include @@ -9,6 +6,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -22,6 +20,7 @@ serial2 = &uart2; mmc0 = &emmc; mmc1 = &sdmmc; + spi0 = &spi0; }; cpus { @@ -33,13 +32,11 @@ compatible = "arm,cortex-a7"; reg = <0xf00>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; + operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; + enable-method = "psci"; }; cpu1: cpu@f01 { @@ -47,6 +44,9 @@ compatible = "arm,cortex-a7"; reg = <0xf01>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + enable-method = "psci"; }; cpu2: cpu@f02 { @@ -54,6 +54,9 @@ compatible = "arm,cortex-a7"; reg = <0xf02>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + enable-method = "psci"; }; cpu3: cpu@f03 { @@ -61,23 +64,37 @@ compatible = "arm,cortex-a7"; reg = <0xf03>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + enable-method = "psci"; }; }; - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000>; }; }; @@ -90,6 +107,11 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; @@ -107,12 +129,15 @@ #clock-cells = <0>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + i2s1: i2s1@100b0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100b0000 0x4000>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; dmas = <&pdma 14>, <&pdma 15>; @@ -126,8 +151,6 @@ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100c0000 0x4000>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; dmas = <&pdma 11>, <&pdma 12>; @@ -135,12 +158,23 @@ status = "disabled"; }; + spdif: spdif@100d0000 { + compatible = "rockchip,rk3228-spdif"; + reg = <0x100d0000 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&pdma 10>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + status = "disabled"; + }; + i2s2: i2s2@100e0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100e0000 0x4000>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; dmas = <&pdma 0>, <&pdma 1>; @@ -149,8 +183,124 @@ }; grf: syscon@11000000 { - compatible = "rockchip,rk3228-grf", "syscon"; + compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; reg = <0x11000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,rk3228-io-voltage-domain"; + status = "disabled"; + }; + + power: power-controller { + compatible = "rockchip,rk3228-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3228_PD_VIO { + reg = ; + clocks = <&cru ACLK_HDCP>, + <&cru SCLK_HDCP>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru SCLK_RGA>; + pm_qos = <&qos_hdcp>, + <&qos_iep>, + <&qos_rga_r>, + <&qos_rga_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VOP { + reg = ; + clocks =<&cru ACLK_VOP>, + <&cru DCLK_VOP>, + <&cru HCLK_VOP>; + pm_qos = <&qos_vop>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_RKVDEC { + reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + pm_qos = <&qos_rkvdec_r>, + <&qos_rkvdec_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + + u2phy0: usb2phy@760 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0760 0x0c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + u2phy1: usb2phy@800 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0800 0x0c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_otg: otg-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; uart0: serial@11010000 { @@ -189,12 +339,29 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&uart21_xfer>; + pinctrl-0 = <&uart2_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; + efuse: efuse@11040000 { + compatible = "rockchip,rk3228-efuse"; + reg = <0x11040000 0x20>; + clocks = <&cru PCLK_EFUSE_256>; + clock-names = "pclk_efuse"; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + efuse_id: id@7 { + reg = <0x7 0x10>; + }; + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + i2c0: i2c@11050000 { compatible = "rockchip,rk3228-i2c"; reg = <0x11050000 0x1000>; @@ -247,12 +414,32 @@ status = "disabled"; }; + spi0: spi@11090000 { + compatible = "rockchip,rk3228-spi"; + reg = <0x11090000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; + status = "disabled"; + }; + + wdt: watchdog@110a0000 { + compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; + reg = <0x110a0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_CPU>; + status = "disabled"; + }; + pwm0: pwm@110b0000 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0000 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; status = "disabled"; @@ -263,7 +450,6 @@ reg = <0x110b0010 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; status = "disabled"; @@ -274,7 +460,6 @@ reg = <0x110b0020 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; status = "disabled"; @@ -285,18 +470,17 @@ reg = <0x110b0030 0x10>; #pwm-cells = <2>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; status = "disabled"; }; timer: timer@110c0000 { - compatible = "rockchip,rk3288-timer"; + compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; reg = <0x110c0000 0x20>; interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; }; cru: clock-controller@110e0000 { @@ -305,8 +489,29 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru ARMCLK>, + <&cru PLL_CPLL>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>; + assigned-clock-rates = + <594000000>, <816000000>, + <500000000>, <150000000>, + <150000000>, <75000000>, + <150000000>, <150000000>, + <75000000>; + }; + + pdma: pdma@110f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x110f0000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; }; thermal-zones { @@ -338,12 +543,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; + <&cpu0 THERMAL_NO_LIMIT 6>, + <&cpu1 THERMAL_NO_LIMIT 6>, + <&cpu2 THERMAL_NO_LIMIT 6>, + <&cpu3 THERMAL_NO_LIMIT 6>; }; map1 { trip = <&cpu_alert1>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -355,53 +566,220 @@ interrupts = ; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <32768>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <0>; + pinctrl-2 = <&otp_pin>; + #thermal-sensor-cells = <1>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; }; - sdmmc: dwmmc@30000000 { + hdmi_phy: hdmi-phy@12030000 { + compatible = "rockchip,rk3228-hdmi-phy"; + reg = <0x12030000 0x10000>; + clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; + clock-names = "sysclk", "refoclk", "refpclk"; + #clock-cells = <0>; + clock-output-names = "hdmiphy_phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + gpu: gpu@20000000 { + compatible = "rockchip,rk3228-mali", "arm,mali-400"; + reg = <0x20000000 0x10000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; + power-domains = <&power RK3228_PD_GPU>; + resets = <&cru SRST_GPU_A>; + status = "disabled"; + }; + + vpu: video-codec@20020000 { + compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; + reg = <0x20020000 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3228_PD_VPU>; + }; + + vpu_mmu: iommu@20020800 { + compatible = "rockchip,iommu"; + reg = <0x20020800 0x100>; + interrupts = ; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VPU>; + #iommu-cells = <0>; + }; + + vdec: video-codec@20030000 { + compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; + reg = <0x20030000 0x480>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <300000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3228_PD_RKVDEC>; + }; + + vdec_mmu: iommu@20030480 { + compatible = "rockchip,iommu"; + reg = <0x20030480 0x40>, <0x200304c0 0x40>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_RKVDEC>; + #iommu-cells = <0>; + }; + + vop: vop@20050000 { + compatible = "rockchip,rk3228-vop"; + reg = <0x20050000 0x1ffc>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + power-domains = <&power RK3228_PD_VOP>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + + vop_mmu: iommu@20053f00 { + compatible = "rockchip,iommu"; + reg = <0x20053f00 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VOP>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga: rga@20060000 { + compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; + reg = <0x20060000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3228_PD_VIO>; + resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; + reset-names = "core", "axi", "ahb"; + }; + + iep_mmu: iommu@20070800 { + compatible = "rockchip,iommu"; + reg = <0x20070800 0x100>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + hdmi: hdmi@200a0000 { + compatible = "rockchip,rk3228-dw-hdmi"; + reg = <0x200a0000 0x20000>; + reg-io-width = <4>; + interrupts = ; + assigned-clocks = <&cru SCLK_HDMI_PHY>; + assigned-clock-parents = <&hdmi_phy>; + clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; + clock-names = "isfr", "iahb", "cec"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; + resets = <&cru SRST_HDMI_P>; + reset-names = "hdmi"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + }; + + sdmmc: mmc@30000000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30000000 0x4000>; interrupts = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; status = "disabled"; }; - sdio: dwmmc@30010000 { + sdio: mmc@30010000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30010000 0x4000>; interrupts = ; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; status = "disabled"; }; - emmc: dwmmc@30020000 { - compatible = "rockchip,rk3288-dw-mshc"; + emmc: mmc@30020000 { + compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; interrupts = ; + clock-frequency = <37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; bus-width = <8>; - default-sample-phase = <158>; - num-slots = <1>; + rockchip,default-sample-phase = <158>; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; @@ -410,13 +788,79 @@ status = "disabled"; }; - usb20_otg: usb@30040000 { - compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", + usb_otg: usb@30040000 { + compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x30040000 0x40000>; interrupts = ; - hnp-srp-disable; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ehci: usb@30080000 { + compatible = "generic-ehci"; + reg = <0x30080000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@300a0000 { + compatible = "generic-ohci"; + reg = <0x300a0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@300c0000 { + compatible = "generic-ehci"; + reg = <0x300c0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@300e0000 { + compatible = "generic-ohci"; + reg = <0x300e0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host2_ehci: usb@30100000 { + compatible = "generic-ehci"; + reg = <0x30100000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host2_ohci: usb@30120000 { + compatible = "generic-ohci"; + reg = <0x30120000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; status = "disabled"; }; @@ -439,6 +883,51 @@ status = "disabled"; }; + qos_iep: qos@31030080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030080 0x20>; + }; + + qos_rga_w: qos@31030100 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030100 0x20>; + }; + + qos_hdcp: qos@31030180 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030180 0x20>; + }; + + qos_rga_r: qos@31030200 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030200 0x20>; + }; + + qos_vpu: qos@31040000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31040000 0x20>; + }; + + qos_gpu: qos@31050000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31050000 0x20>; + }; + + qos_vop: qos@31060000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31060000 0x20>; + }; + + qos_rkvdec_r: qos@31070000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070000 0x20>; + }; + + qos_rkvdec_w: qos@31070080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070080 0x20>; + }; + gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller; @@ -459,7 +948,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@11110000 { + gpio0: gpio@11110000 { compatible = "rockchip,gpio-bank"; reg = <0x11110000 0x100>; interrupts = ; @@ -472,7 +961,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@11120000 { + gpio1: gpio@11120000 { compatible = "rockchip,gpio-bank"; reg = <0x11120000 0x100>; interrupts = ; @@ -485,7 +974,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@11130000 { + gpio2: gpio@11130000 { compatible = "rockchip,gpio-bank"; reg = <0x11130000 0x100>; interrupts = ; @@ -498,7 +987,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@11140000 { + gpio3: gpio@11140000 { compatible = "rockchip,gpio-bank"; reg = <0x11140000 0x100>; interrupts = ; @@ -529,222 +1018,277 @@ sdmmc { sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; }; sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, + <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; }; }; sdio { sdio_clk: sdio-clk { - rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; }; sdio_cmd: sdio-cmd { - rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; }; sdio_bus4: sdio-bus4 { - rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, + <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, + <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, + <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; }; }; emmc { emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, + <1 RK_PD1 2 &pcfg_pull_none>, + <1 RK_PD2 2 &pcfg_pull_none>, + <1 RK_PD3 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>, + <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD6 2 &pcfg_pull_none>, + <1 RK_PD7 2 &pcfg_pull_none>; }; }; gmac { rgmii_pins: rgmii-pins { - rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC5 2 &pcfg_pull_none>, + <2 RK_PC4 2 &pcfg_pull_none>, + <2 RK_PB3 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>; }; rmii_pins: rmii-pins { - rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>; }; phy_pins: phy-pins { - rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, + <2 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; + }; + + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, + <0 RK_PA7 2 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; }; }; i2s1 { i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, + <0 RK_PB1 1 &pcfg_pull_none>, + <0 RK_PB3 1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none>, + <0 RK_PB5 1 &pcfg_pull_none>, + <0 RK_PB6 1 &pcfg_pull_none>, + <1 RK_PA2 2 &pcfg_pull_none>, + <1 RK_PA4 2 &pcfg_pull_none>, + <1 RK_PA5 2 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; }; }; tsadc { - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; otp_out: otp-out { - rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, + <2 RK_PD3 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB2 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, - <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + uart21_xfer: uart21-xfer { + rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, + <1 RK_PB1 2 &pcfg_pull_none>; }; uart2_cts: uart2-cts { - rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; }; uart2_rts: uart2-rts { - rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2-1 { - uart21_xfer: uart21-xfer { - rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, - <1 9 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; }; }; }; From d3cb7565de8a4ee320e743add979c5447dcbb6ec Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:36 +0200 Subject: [PATCH 40/48] arm: dts: rockchip: sync rk3229-evb.dts from Linux Sync rk3229-evb.dts from Linux version 5.17. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3229-evb.dts | 214 +++++++++++++++++++++++++++++++++--- arch/arm/dts/rk3229.dtsi | 52 +++++++++ arch/arm/dts/rk322x.dtsi | 2 - 3 files changed, 250 insertions(+), 18 deletions(-) create mode 100644 arch/arm/dts/rk3229.dtsi diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index d2681d1a059..797476e8bef 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -1,21 +1,32 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; -#include "rk322x.dtsi" +#include +#include "rk3229.dtsi" / { model = "Rockchip RK3229 Evaluation board"; compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; + aliases { + mmc0 = &emmc; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + ext_gmac: ext_gmac { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -23,6 +34,18 @@ #clock-cells = <0>; }; + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + vcc_phy: vcc-phy-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -31,7 +54,95 @@ regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; + vin-supply = <&vccio_1v8>; }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vccio_1v8: vccio-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vccio_3v3: vccio-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vdd_arm: vdd-arm-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + gpio_keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power_key: power-key { + label = "GPIO Key Power"; + gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + wakeup-source; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + non-removable; + status = "okay"; }; &gmac { @@ -50,25 +161,96 @@ status = "okay"; }; -&emmc { +&io_domains { + status = "okay"; + + vccio1-supply = <&vccio_3v3>; + vccio2-supply = <&vccio_1v8>; + vccio4-supply = <&vccio_3v3>; +}; + +&pinctrl { + keys { + pwr_key: pwr-key { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { status = "okay"; }; -&sdmmc { +&pwm2 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ status = "okay"; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - supports-sd; }; &uart2 { status = "okay"; }; -&usb_otg { - status = "okay"; +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_ehci { + status = "okay"; +}; + +&usb_host2_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; }; diff --git a/arch/arm/dts/rk3229.dtsi b/arch/arm/dts/rk3229.dtsi new file mode 100644 index 00000000000..c340fb30e77 --- /dev/null +++ b/arch/arm/dts/rk3229.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "rk322x.dtsi" + +/ { + compatible = "rockchip,rk3229"; + + /delete-node/ opp-table0; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1325000>; + }; + opp-1392000000 { + opp-hz = /bits/ 64 <1392000000>; + opp-microvolt = <1375000>; + }; + opp-1464000000 { + opp-hz = /bits/ 64 <1464000000>; + opp-microvolt = <1400000>; + }; + }; +}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index c5330c19864..8eed9e3a92e 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -18,8 +18,6 @@ serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; - mmc0 = &emmc; - mmc1 = &sdmmc; spi0 = &spi0; }; From 444311196e6e84c3e87f82bdc53b6510d0919e84 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:37 +0200 Subject: [PATCH 41/48] rockchip: rk3288-power: sync power domain dt-binding header from Linux In order to update the DT for rk3288 sync the power domain dt-binding header. This is the state as of v5.17 in Linux. Change location to be more in line with other SoCs. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3288.dtsi | 2 +- include/dt-bindings/power-domain/rk3288.h | 11 -------- include/dt-bindings/power/rk3288-power.h | 32 +++++++++++++++++++++++ 3 files changed, 33 insertions(+), 12 deletions(-) delete mode 100644 include/dt-bindings/power-domain/rk3288.h create mode 100644 include/dt-bindings/power/rk3288-power.h diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 22bb06cec5b..2086dbfda44 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include "skeleton.dtsi" diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h deleted file mode 100644 index ca68c11475c..00000000000 --- a/include/dt-bindings/power-domain/rk3288.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ -#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ - -/* RK3288 power domain index */ -#define RK3288_PD_GPU 0 -#define RK3288_PD_VIO 1 -#define RK3288_PD_VIDEO 2 -#define RK3288_PD_HEVC 3 -#define RK3288_PD_PERI 4 - -#endif diff --git a/include/dt-bindings/power/rk3288-power.h b/include/dt-bindings/power/rk3288-power.h new file mode 100644 index 00000000000..f710b56ccd8 --- /dev/null +++ b/include/dt-bindings/power/rk3288-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__ +#define __DT_BINDINGS_POWER_RK3288_POWER_H__ + +/** + * RK3288 Power Domain and Voltage Domain Summary. + */ + +/* VD_CORE */ +#define RK3288_PD_A17_0 0 +#define RK3288_PD_A17_1 1 +#define RK3288_PD_A17_2 2 +#define RK3288_PD_A17_3 3 +#define RK3288_PD_SCU 4 +#define RK3288_PD_DEBUG 5 +#define RK3288_PD_MEM 6 + +/* VD_LOGIC */ +#define RK3288_PD_BUS 7 +#define RK3288_PD_PERI 8 +#define RK3288_PD_VIO 9 +#define RK3288_PD_ALIVE 10 +#define RK3288_PD_HEVC 11 +#define RK3288_PD_VIDEO 12 + +/* VD_GPU */ +#define RK3288_PD_GPU 13 + +/* VD_PMU */ +#define RK3288_PD_PMU 14 + +#endif From 334d519a13e4636dd454738510fc840467109b0e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:38 +0200 Subject: [PATCH 42/48] rockchip: rk3288-cru: sync the clock dt-binding header from Linux In order to update the DT for rk3288 sync the clock dt-binding header. This is the state as of v5.17 in Linux. Keep SCLK_MAC_PLL in use for rk3288 clock driver. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- include/dt-bindings/clock/rk3288-cru.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index e368d767506..453f66718c6 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -1,9 +1,12 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner */ +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H + /* core clocks */ #define PLL_APLL 1 #define PLL_DPLL 2 @@ -74,6 +77,9 @@ #define SCLK_USBPHY480M_SRC 122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_CRYPTO 125 +#define SCLK_MIPIDSI_24M 126 +#define SCLK_VIP_OUT 127 #define SCLK_MAC_PLL 150 #define SCLK_MAC 151 @@ -153,6 +159,9 @@ #define PCLK_DDRUPCTL1 366 #define PCLK_PUBL1 367 #define PCLK_WDT 368 +#define PCLK_EFUSE256 369 +#define PCLK_EFUSE1024 370 +#define PCLK_ISP_IN 371 /* hclk gates */ #define HCLK_GPS 448 @@ -368,3 +377,5 @@ #define SRST_TSP_CLKIN0 189 #define SRST_TSP_CLKIN1 190 #define SRST_TSP_27M 191 + +#endif From 52a0c68994596544bfdbb3f8d0a034a5d2b13c1e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:39 +0200 Subject: [PATCH 43/48] arm: dts: rockchip: move all rk3288 u-boot specific properties in separate dtsi files In order to sync rk3288.dtsi from Linux it needed to move all u-boot specific properties in separate dtsi files. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-evb-u-boot.dtsi | 11 +++ arch/arm/dts/rk3288-evb.dts | 11 --- arch/arm/dts/rk3288-firefly-u-boot.dtsi | 31 +++++++ arch/arm/dts/rk3288-firefly.dts | 17 ---- arch/arm/dts/rk3288-firefly.dtsi | 3 - arch/arm/dts/rk3288-miqi-u-boot.dtsi | 20 +++++ arch/arm/dts/rk3288-miqi.dts | 11 --- arch/arm/dts/rk3288-miqi.dtsi | 2 - arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi | 44 ++++++++++ arch/arm/dts/rk3288-phycore-rdk.dts | 18 ---- arch/arm/dts/rk3288-phycore-som.dtsi | 6 -- arch/arm/dts/rk3288-popmetal-u-boot.dtsi | 11 +++ arch/arm/dts/rk3288-popmetal.dts | 11 --- arch/arm/dts/rk3288-rock2-square-u-boot.dtsi | 30 +++++++ arch/arm/dts/rk3288-rock2-square.dts | 18 ---- arch/arm/dts/rk3288-u-boot.dtsi | 84 ++++++++++++++++--- arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi | 14 ++++ arch/arm/dts/rk3288-veyron-jerry.dts | 11 --- arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi | 14 ++++ arch/arm/dts/rk3288-veyron-mickey.dts | 11 --- arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi | 14 ++++ arch/arm/dts/rk3288-veyron-minnie.dts | 11 --- arch/arm/dts/rk3288-veyron-u-boot.dtsi | 61 ++++++++++++++ arch/arm/dts/rk3288-veyron.dtsi | 39 --------- arch/arm/dts/rk3288.dtsi | 49 +---------- 25 files changed, 322 insertions(+), 230 deletions(-) create mode 100644 arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-rock2-square-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi diff --git a/arch/arm/dts/rk3288-evb-u-boot.dtsi b/arch/arm/dts/rk3288-evb-u-boot.dtsi index 8ac7840f8f9..c8f51207116 100644 --- a/arch/arm/dts/rk3288-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3288-evb-u-boot.dtsi @@ -5,6 +5,17 @@ #include "rk3288-u-boot.dtsi" +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts index eac91a873f2..bb24a96cddf 100644 --- a/arch/arm/dts/rk3288-evb.dts +++ b/arch/arm/dts/rk3288-evb.dts @@ -15,17 +15,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 - 0x8 0x1f4>; - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 - 0x0 0xc3 0x6 0x2>; - rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; -}; - &pwm1 { status = "okay"; }; diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index 8b9c38310fb..cc84d7c4ae1 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -5,6 +5,37 @@ #include "rk3288-u-boot.dtsi" +/ { + config { + u-boot,dm-pre-reloc; + u-boot,boot-led = "firefly:green:power"; + }; + + leds { + u-boot,dm-pre-reloc; + + work { + u-boot,dm-pre-reloc; + }; + + power { + u-boot,dm-pre-reloc; + }; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + /* Add a dummy value to cause of-platdata think this is bytes */ + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts index 1cff04e7c7b..72982efdf6d 100644 --- a/arch/arm/dts/rk3288-firefly.dts +++ b/arch/arm/dts/rk3288-firefly.dts @@ -13,23 +13,6 @@ chosen { stdout-path = &uart2; }; - - config { - u-boot,dm-pre-reloc; - u-boot,boot-led = "firefly:green:power"; - }; -}; - -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - /* Add a dummy value to cause of-platdata think this is bytes */ - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; &ir { diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi index b7f279f706f..1117d3913ed 100644 --- a/arch/arm/dts/rk3288-firefly.dtsi +++ b/arch/arm/dts/rk3288-firefly.dtsi @@ -37,11 +37,9 @@ }; leds { - u-boot,dm-pre-reloc; compatible = "gpio-leds"; work { - u-boot,dm-pre-reloc; gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; label = "firefly:blue:user"; linux,default-trigger = "rc-feedback"; @@ -50,7 +48,6 @@ }; power { - u-boot,dm-pre-reloc; gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; label = "firefly:green:power"; linux,default-trigger = "default-on"; diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi index 4f63fc9f131..2a74fdd15fb 100644 --- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi @@ -4,6 +4,26 @@ */ #include "rk3288-u-boot.dtsi" +/ { + leds { + u-boot,dm-pre-reloc; + + work { + u-boot,dm-pre-reloc; + }; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; &pinctrl { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts index e47170c6530..4a2f249e1b1 100644 --- a/arch/arm/dts/rk3288-miqi.dts +++ b/arch/arm/dts/rk3288-miqi.dts @@ -14,14 +14,3 @@ stdout-path = "serial2:115200n8"; }; }; - -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; -}; diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi index 432f744bebc..cb80cbf27df 100644 --- a/arch/arm/dts/rk3288-miqi.dtsi +++ b/arch/arm/dts/rk3288-miqi.dtsi @@ -34,11 +34,9 @@ leds { - u-boot,dm-pre-reloc; compatible = "gpio-leds"; work { - u-boot,dm-pre-reloc; gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; label = "miqi:green:user"; linux,default-trigger = "default-on"; diff --git a/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi new file mode 100644 index 00000000000..30f4cb106e2 --- /dev/null +++ b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-u-boot.dtsi" + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&i2c0 { + u-boot,dm-pre-reloc; + + rk818: pmic@1c { + u-boot,dm-pre-reloc; + + regulators { + u-boot,dm-pre-reloc; + }; + }; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts index cc3921095c3..ebea8e67ead 100644 --- a/arch/arm/dts/rk3288-phycore-rdk.dts +++ b/arch/arm/dts/rk3288-phycore-rdk.dts @@ -112,19 +112,6 @@ }; }; -&dmc { - rockchip,num-channels = <2>; - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>; -}; - &gmac { status = "okay"; }; @@ -175,8 +162,6 @@ }; &pinctrl { - u-boot,dm-pre-reloc; - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { bias-pull-up; drive-strength = <12>; @@ -246,8 +231,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; - bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; @@ -268,7 +251,6 @@ }; &uart2 { - u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index 02d11968cb3..821525f7148 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -149,8 +149,6 @@ &emmc { status = "okay"; - u-boot,dm-pre-reloc; - bus-width = <8>; cap-mmc-highspeed; disable-wp; @@ -201,8 +199,6 @@ &i2c0 { status = "okay"; - u-boot,dm-pre-reloc; - clock-frequency = <400000>; rk818: pmic@1c { @@ -216,7 +212,6 @@ rockchip,system-power-controller; wakeup-source; #clock-cells = <1>; - u-boot,dm-pre-reloc; vcc1-supply = <&vdd_sys>; vcc2-supply = <&vdd_sys>; @@ -230,7 +225,6 @@ vddio-supply = <&vdd_3v3_io>; regulators { - u-boot,dm-pre-reloc; vdd_log: DCDC_REG1 { regulator-name = "vdd_log"; regulator-always-on; diff --git a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi index 8ac7840f8f9..3782253c8aa 100644 --- a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi +++ b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi @@ -5,6 +5,17 @@ #include "rk3288-u-boot.dtsi" +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts index 5c6d06f2fdb..736dc51e261 100644 --- a/arch/arm/dts/rk3288-popmetal.dts +++ b/arch/arm/dts/rk3288-popmetal.dts @@ -15,17 +15,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; -}; - &pwm1 { status = "okay"; }; diff --git a/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi b/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi new file mode 100644 index 00000000000..509f789b98b --- /dev/null +++ b/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-u-boot.dtsi" + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + +&gpio7 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts index 11c580a0b56..41676696ba3 100644 --- a/arch/arm/dts/rk3288-rock2-square.dts +++ b/arch/arm/dts/rk3288-rock2-square.dts @@ -96,7 +96,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; @@ -139,7 +138,6 @@ }; &pinctrl { - u-boot,dm-pre-reloc; ir { ir_int: ir-int { rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; @@ -171,7 +169,6 @@ &uart2 { status = "okay"; - u-boot,dm-pre-reloc; reg-shift = <2>; }; @@ -182,18 +179,3 @@ &usb_host0_ehci { status = "okay"; }; - -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; -}; - -&gpio7 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index e3c6c10f130..9eb696b1411 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -7,10 +7,53 @@ #include "rockchip-optee.dtsi" / { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + gpio8 = &gpio8; + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio0; + mmc3 = &sdio1; + }; + chosen { u-boot,spl-boot-order = \ "same-as-spl", &emmc, &sdmmc; }; + + dmc: dmc@ff610000 { + compatible = "rockchip,rk3288-dmc", "syscon"; + reg = <0xff610000 0x3fc + 0xff620000 0x294 + 0xff630000 0x3fc + 0xff640000 0x294>; + clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, + <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, + <&cru ARMCLK>; + clock-names = "pclk_ddrupctl0", "pclk_publ0", + "pclk_ddrupctl1", "pclk_publ1", + "arm_clk"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,noc = <&noc>; + rockchip,pmu = <&pmu>; + rockchip,sgrf = <&sgrf>; + rockchip,sram = <&ddr_sram>; + u-boot,dm-pre-reloc; + }; + + noc: syscon@ffac0000 { + compatible = "rockchip,rk3288-noc", "syscon"; + reg = <0xffac0000 0x2000>; + u-boot,dm-pre-reloc; + }; }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE @@ -37,7 +80,22 @@ }; #endif -&dmc { +&bus_intmem { + ddr_sram: ddr-sram@1000 { + compatible = "rockchip,rk3288-ddr-sram"; + reg = <0x1000 0x4000>; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&gpio7 { + u-boot,dm-pre-reloc; +}; + +&grf { u-boot,dm-pre-reloc; }; @@ -49,12 +107,20 @@ u-boot,dm-pre-reloc; }; -&cru { - u-boot,dm-pre-reloc; +&uart0 { + clock-frequency = <24000000>; }; -&grf { - u-boot,dm-pre-reloc; +&uart1 { + clock-frequency = <24000000>; +}; + +&uart2 { + clock-frequency = <24000000>; +}; + +&uart3 { + clock-frequency = <24000000>; }; &vopb { @@ -64,11 +130,3 @@ &vopl { u-boot,dm-pre-reloc; }; - -&noc { - u-boot,dm-pre-reloc; -}; - -&gpio7 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi new file mode 100644 index 00000000000..2cc6b090acb --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-veyron-u-boot.dtsi" + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts index c251d9d5942..ff7669eba4d 100644 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -66,17 +66,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; -}; - &gpio_keys { power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi new file mode 100644 index 00000000000..213a46babf0 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-veyron-u-boot.dtsi" + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>; +}; diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts index e0dc3620618..0521d9e0e9a 100644 --- a/arch/arm/dts/rk3288-veyron-mickey.dts +++ b/arch/arm/dts/rk3288-veyron-mickey.dts @@ -161,17 +161,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 - 0x8 0x1f4>; - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 - 0x0 0xc3 0x6 0x2>; - rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>; -}; - &emmc { /delete-property/mmc-hs200-1_8v; }; diff --git a/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi new file mode 100644 index 00000000000..8211da41fcc --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-veyron-u-boot.dtsi" + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>; +}; diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts index 646f6ae7424..b56a3f4f51a 100644 --- a/arch/arm/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/dts/rk3288-veyron-minnie.dts @@ -137,17 +137,6 @@ power-supply = <&backlight_regulator>; }; -&dmc { - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 - 0x8 0x1f4>; - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 - 0x0 0xc3 0x6 0x1>; - rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>; -}; - &emmc { /delete-property/mmc-hs200-1_8v; }; diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi index 899fe6e7a04..21e1aec2911 100644 --- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi @@ -5,7 +5,68 @@ #include "rk3288-u-boot.dtsi" +/ { + chosen { + u-boot,spl-boot-order = &spi_flash; + }; +}; + +&dmc { + logic-supply = <&vdd_logic>; + rockchip,odt-disable-freq = <333000000>; + rockchip,dll-disable-freq = <333000000>; + rockchip,sr-enable-freq = <333000000>; + rockchip,pd-enable-freq = <666000000>; + rockchip,auto-self-refresh-cnt = <0>; + rockchip,auto-power-down-cnt = <64>; + rockchip,ddr-speed-bin = <21>; + rockchip,trcd = <10>; + rockchip,trp = <10>; + operating-points = < + /* KHz uV */ + 200000 1050000 + 333000 1100000 + 533000 1150000 + 666000 1200000 + >; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + &gpio7 { u-boot,dm-pre-reloc; }; +&gpio8 { + u-boot,dm-pre-reloc; +}; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&rk808 { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&spi2 { + u-boot,dm-pre-reloc; +}; + +&spi_flash { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 8754043b9b3..4a9c27a49e2 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -16,7 +16,6 @@ chosen { stdout-path = &uart2; - u-boot,spl-boot-order = &spi_flash; }; firmware { @@ -220,26 +219,6 @@ cpu0-supply = <&vdd_cpu>; }; -&dmc { - logic-supply = <&vdd_logic>; - rockchip,odt-disable-freq = <333000000>; - rockchip,dll-disable-freq = <333000000>; - rockchip,sr-enable-freq = <333000000>; - rockchip,pd-enable-freq = <666000000>; - rockchip,auto-self-refresh-cnt = <0>; - rockchip,auto-power-down-cnt = <64>; - rockchip,ddr-speed-bin = <21>; - rockchip,trcd = <10>; - rockchip,trp = <10>; - operating-points = < - /* KHz uV */ - 200000 1050000 - 333000 1100000 - 533000 1150000 - 666000 1200000 - >; -}; - &efuse { status = "okay"; }; @@ -299,10 +278,8 @@ &spi2 { status = "okay"; - u-boot,dm-pre-reloc; spi_flash: spiflash@0 { - u-boot,dm-pre-reloc; compatible = "spidev", "jedec,spi-nor"; spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */ reg = <0>; @@ -315,7 +292,6 @@ clock-frequency = <400000>; i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ i2c-scl-rising-time-ns = <100>; /* 45ns measured */ - u-boot,dm-pre-reloc; rk808: pmic@1b { compatible = "rockchip,rk808"; @@ -328,7 +304,6 @@ rockchip,system-power-controller; wakeup-source; #clock-cells = <1>; - u-boot,dm-pre-reloc; vcc1-supply = <&vcc33_sys>; vcc2-supply = <&vcc33_sys>; @@ -557,7 +532,6 @@ &uart2 { status = "okay"; - u-boot,dm-pre-reloc; reg-shift = <2>; }; @@ -601,7 +575,6 @@ }; &pinctrl { - u-boot,dm-pre-reloc; pinctrl-names = "default", "sleep"; pinctrl-0 = < /* Common for sleep and wake, but no owners */ @@ -826,15 +799,3 @@ assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; assigned-clock-parents = <&cru SCLK_OTGPHY0>; }; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 2086dbfda44..c4abfa3702c 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -15,25 +15,12 @@ interrupt-parent = <&gic>; aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &gpio5; - gpio6 = &gpio6; - gpio7 = &gpio7; - gpio8 = &gpio8; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; - mmc0 = &emmc; - mmc1 = &sdmmc; - mmc2 = &sdio0; - mmc3 = &sdio1; mshc0 = &emmc; mshc1 = &sdmmc; mshc2 = &sdio0; @@ -323,7 +310,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -337,7 +323,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -351,7 +336,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -364,7 +348,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -378,7 +361,6 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -476,26 +458,6 @@ status = "disabled"; }; - dmc: dmc@ff610000 { - compatible = "rockchip,rk3288-dmc", "syscon"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - rockchip,sgrf = <&sgrf>; - rockchip,noc = <&noc>; - reg = <0xff610000 0x3fc - 0xff620000 0x294 - 0xff630000 0x3fc - 0xff640000 0x294>; - rockchip,sram = <&ddr_sram>; - clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, - <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, - <&cru ARMCLK>; - clock-names = "pclk_ddrupctl0", "pclk_publ0", - "pclk_ddrupctl1", "pclk_publ1", - "arm_clk"; - }; - i2c0: i2c@ff650000 { compatible = "rockchip,rk3288-i2c"; reg = <0xff650000 0x1000>; @@ -570,7 +532,7 @@ status = "disabled"; }; - bus_intmem@ff700000 { + bus_intmem: bus_intmem@ff700000 { compatible = "mmio-sram"; reg = <0xff700000 0x18000>; #address-cells = <1>; @@ -580,10 +542,6 @@ compatible = "rockchip,rk3066-smp-sram"; reg = <0x00 0x10>; }; - ddr_sram: ddr-sram@1000 { - compatible = "rockchip,rk3288-ddr-sram"; - reg = <0x1000 0x4000>; - }; }; sram@ff720000 { @@ -912,11 +870,6 @@ status = "disabled"; }; - noc: syscon@ffac0000 { - compatible = "rockchip,rk3288-noc", "syscon"; - reg = <0xffac0000 0x2000>; - }; - efuse: efuse@ffb40000 { compatible = "rockchip,rk3288-efuse"; reg = <0xffb40000 0x10000>; From 5859bb286306b5515e803083b1bc74397293d3b9 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:43 +0200 Subject: [PATCH 44/48] rockchip: fix boot_devices constants The DT node name pattern in mmc-controller.yaml for mmc is "^mmc(@.*)?$". The Rockchip mmc nodes have been synced with Linux, so update the boot_devices constants as well. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3188/rk3188.c | 4 ++-- arch/arm/mach-rockchip/rk322x/rk322x.c | 4 ++-- arch/arm/mach-rockchip/rk3288/rk3288.c | 4 ++-- arch/arm/mach-rockchip/rk3328/rk3328.c | 4 ++-- arch/arm/mach-rockchip/rk3368/rk3368.c | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index 5a02914e1b0..df8fa1566f0 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -21,8 +21,8 @@ #define GRF_BASE 0x20008000 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@10214000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000", + [BROM_BOOTSOURCE_SD] = "/mmc@10214000", }; #ifdef CONFIG_DEBUG_UART_BOARD_INIT diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index ad4ac62e514..a304795fec6 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -9,8 +9,8 @@ #include const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@30000000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@30020000", + [BROM_BOOTSOURCE_SD] = "/mmc@30000000", }; #ifdef CONFIG_DEBUG_UART_BOARD_INIT diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index bc20bc5ab90..3ad2887575d 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -28,8 +28,8 @@ DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xff770000 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", }; #ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index ec3336cb49a..de17b886827 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; #define FW_DDR_CON_REG 0xFF7C0040 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000", - [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff500000", }; static struct mm_region rk3328_mem_map[] = { diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 9b7132d471c..d0a6107e5e0 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -58,8 +58,8 @@ static struct mm_region rk3368_mem_map[] = { struct mm_region *mem_map = rk3368_mem_map; const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", }; #ifdef CONFIG_ARCH_EARLY_INIT_R From 8042717afa8c41eb28c8d3976cf104cfa72179fd Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:44 +0200 Subject: [PATCH 45/48] board: google: veyron: add more DT files to MAINTAINERS The Google Veyron rk3288 DT files are synced from Linux. Add a maintainer to look after them and to help with review and testing. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- board/google/veyron/MAINTAINERS | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS index d97978076d3..67341b5d556 100644 --- a/board/google/veyron/MAINTAINERS +++ b/board/google/veyron/MAINTAINERS @@ -1,6 +1,8 @@ CHROMEBOOK JERRY BOARD M: Simon Glass S: Maintained +F: arch/arm/dts/rk3288-veyron-jerry.dts +F: arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h F: configs/chromebook_jerry_defconfig @@ -8,6 +10,8 @@ F: configs/chromebook_jerry_defconfig CHROMEBIT MICKEY BOARD M: Simon Glass S: Maintained +F: arch/arm/dts/rk3288-veyron-mickey.dts +F: arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h F: configs/chromebit_mickey_defconfig @@ -15,6 +19,8 @@ F: configs/chromebit_mickey_defconfig CHROMEBOOK MINNIE BOARD M: Simon Glass S: Maintained +F: arch/arm/dts/rk3288-veyron-minnie.dts +F: arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h F: configs/chromebook_minnie_defconfig @@ -22,6 +28,17 @@ F: configs/chromebook_minnie_defconfig CHROMEBOOK SPEEDY BOARD M: Simon Glass S: Maintained +F: arch/arm/dts/rk3288-veyron-speedy.dts +F: arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h F: configs/chromebook_speedy_defconfig + +CHROMEBOOK VEYRON COMMON FILES +M: Simon Glass +S: Maintained +F: arch/arm/dts/rk3288-veyron.dtsi +F: arch/arm/dts/rk3288-veyron-analog-audio.dtsi +F: arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi +F: arch/arm/dts/rk3288-veyron-chromebook.dtsi +F: arch/arm/dts/rk3288-veyron-edp.dtsi From 8f4741446602228a40c2b9ebaa842db84bdfb81d Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:45 +0200 Subject: [PATCH 46/48] board: rk3288: add more DT files to MAINTAINERS A number of rk3229/rk3288 DT files are synced from Linux. Add a maintainer to look after them and to help with review and testing. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- board/chipspark/popmetal_rk3288/MAINTAINERS | 2 ++ board/mqmaker/miqi_rk3288/MAINTAINERS | 2 ++ board/phytec/phycore_rk3288/MAINTAINERS | 3 +++ board/radxa/rock2/MAINTAINERS | 3 +++ board/rockchip/evb_rk3229/MAINTAINERS | 2 ++ board/rockchip/evb_rk3288/MAINTAINERS | 3 +++ board/rockchip/tinker_rk3288/MAINTAINERS | 5 +++++ 7 files changed, 20 insertions(+) diff --git a/board/chipspark/popmetal_rk3288/MAINTAINERS b/board/chipspark/popmetal_rk3288/MAINTAINERS index 1a6a1bb2c61..e12f128dcd7 100644 --- a/board/chipspark/popmetal_rk3288/MAINTAINERS +++ b/board/chipspark/popmetal_rk3288/MAINTAINERS @@ -1,6 +1,8 @@ POPMETAL-RK3288 M: Lin Huang S: Maintained +F: arch/arm/dts/rk3288-popmetal.dts +F: arch/arm/dts/rk3288-popmetal-u-boot.dtsi F: board/chipspark/popmetal_rk3288 F: include/configs/popmetal_rk3288.h F: configs/popmetal-rk3288_defconfig diff --git a/board/mqmaker/miqi_rk3288/MAINTAINERS b/board/mqmaker/miqi_rk3288/MAINTAINERS index 053a5e6028f..1cb5f790fe7 100644 --- a/board/mqmaker/miqi_rk3288/MAINTAINERS +++ b/board/mqmaker/miqi_rk3288/MAINTAINERS @@ -1,6 +1,8 @@ MIQI M: Jernej Skrabec S: Maintained +F: arch/arm/dts/rk3288-miqi.dts +F: arch/arm/dts/rk3288-miqi-u-boot.dtsi F: board/mqmaker/miqi_rk3288 F: include/configs/miqi_rk3288.h F: configs/miqi-rk3288_defconfig diff --git a/board/phytec/phycore_rk3288/MAINTAINERS b/board/phytec/phycore_rk3288/MAINTAINERS index 9c0de3cc81f..60471d478b4 100644 --- a/board/phytec/phycore_rk3288/MAINTAINERS +++ b/board/phytec/phycore_rk3288/MAINTAINERS @@ -1,6 +1,9 @@ phyCORE-RK3288 M: Wadim Egorov S: Maintained +F: arch/arm/dts/rk3288-phycore-rdk.dts +F: arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi +F: arch/arm/dts/rk3288-phycore-som.dtsi F: board/phytec/phycore_rk3288 F: include/configs/phycore_rk3288.h F: configs/phycore-rk3288_defconfig diff --git a/board/radxa/rock2/MAINTAINERS b/board/radxa/rock2/MAINTAINERS index a697e68281a..5328fd76014 100644 --- a/board/radxa/rock2/MAINTAINERS +++ b/board/radxa/rock2/MAINTAINERS @@ -1,6 +1,9 @@ FIREFLY M: Simon Glass S: Maintained +F: arch/arm/dts/rk3288-rock2-som.dtsi +F: arch/arm/dts/rk3288-rock2-square.dts +F: arch/arm/dts/rk3288-rock2-square-u-boot.dtsi F: board/radxa/rock2 F: include/configs/rock2.h F: configs/rock2_defconfig diff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS index dfa1090c3e3..4de97dbb0a4 100644 --- a/board/rockchip/evb_rk3229/MAINTAINERS +++ b/board/rockchip/evb_rk3229/MAINTAINERS @@ -1,6 +1,8 @@ EVB-RK3229 M: Kever Yang S: Maintained +F: arch/arm/dts/rk3229-evb.dts +F: arch/arm/dts/rk3229-evb-u-boot.dtsi F: board/rockchip/evb_rk3229 F: include/configs/evb_rk3229.h F: configs/evb-rk3229_defconfig diff --git a/board/rockchip/evb_rk3288/MAINTAINERS b/board/rockchip/evb_rk3288/MAINTAINERS index 9bd6b1e8a4c..9857ae33575 100644 --- a/board/rockchip/evb_rk3288/MAINTAINERS +++ b/board/rockchip/evb_rk3288/MAINTAINERS @@ -1,6 +1,9 @@ EVB-RK3288 M: Lin Huang S: Maintained +F: arch/arm/dts/rk3288-evb.dts +F: arch/arm/dts/rk3288-evb.dtsi +F: arch/arm/dts/rk3288-evb-u-boot.dtsi F: board/rockchip/evb_rk3288 F: include/configs/evb_rk3288.h F: configs/evb-rk3288_defconfig diff --git a/board/rockchip/tinker_rk3288/MAINTAINERS b/board/rockchip/tinker_rk3288/MAINTAINERS index ed5de682c97..3869d5dc853 100644 --- a/board/rockchip/tinker_rk3288/MAINTAINERS +++ b/board/rockchip/tinker_rk3288/MAINTAINERS @@ -1,6 +1,11 @@ TINKER-RK3288 M: Lin Huang S: Maintained +F: arch/arm/dts/rk3288-tinker.dts +F: arch/arm/dts/rk3288-tinker.dtsi +F: arch/arm/dts/rk3288-tinker-s.dts +F: arch/arm/dts/rk3288-tinker-s-u-boot.dtsi +F: arch/arm/dts/rk3288-tinker-u-boot.dtsi F: board/rockchip/tinker_rk3288 F: include/configs/tinker_rk3288.h F: configs/tinker-rk3288_defconfig From 0944e77fde179de28db9a2ad7e6b975b8fedfc19 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 09:45:56 +0200 Subject: [PATCH 47/48] rockchip: video: rk_edp: add more rk3288 edp node options The rk3288 DT synced from Linux contains some different properties in the edp node then origanal used in U-boot. Allow both options to be backwards compatible and to be able to handle recent rk3288.dtsi files. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/video/rockchip/rk_edp.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 0ddf5e02d69..3697d582510 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -1070,8 +1070,11 @@ static int rk_edp_probe(struct udevice *dev) ret = reset_get_by_name(dev, "dp", &dp_rst); if (ret) { - dev_err(dev, "failed to get dp reset (ret=%d)\n", ret); - return ret; + ret = reset_get_by_name(dev, "edp", &dp_rst); + if (ret) { + dev_err(dev, "failed to get dp reset (ret=%d)\n", ret); + return ret; + } } ret = reset_assert(&dp_rst); @@ -1156,6 +1159,7 @@ static const struct rockchip_dp_data rk3288_dp = { }; static const struct udevice_id rockchip_dp_ids[] = { + { .compatible = "rockchip,rk3288-dp", .data = (ulong)&rk3288_dp }, { .compatible = "rockchip,rk3288-edp", .data = (ulong)&rk3288_dp }, { .compatible = "rockchip,rk3399-edp", .data = (ulong)&rk3399_edp }, { } From dcaaefdc0a7b3052e513b0e5dd2b00be4436386b Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 10:25:16 +0200 Subject: [PATCH 48/48] rockchip: video: mipi: add more compatible strings for rk3288/rk3399 The rk3288/RK3399 DT synced from Linux contains some different compatible strings in the mipi node then origanal used in U-boot. Allow both options to be backwards compatible and to be able to handle recent rk3288.dtsi and rk3399.dtsi files. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/video/rockchip/rk3288_mipi.c | 1 + drivers/video/rockchip/rk3399_mipi.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index 7e48dd83466..c0dffa3cba2 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -174,6 +174,7 @@ static const struct dm_display_ops rk_mipi_dsi_ops = { }; static const struct udevice_id rk_mipi_dsi_ids[] = { + { .compatible = "rockchip,rk3288-mipi-dsi" }, { .compatible = "rockchip,rk3288_mipi_dsi" }, { } }; diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index 91733504831..7fc79ba9045 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -165,6 +165,7 @@ static const struct dm_display_ops rk_mipi_dsi_ops = { }; static const struct udevice_id rk_mipi_dsi_ids[] = { + { .compatible = "rockchip,rk3399-mipi-dsi" }, { .compatible = "rockchip,rk3399_mipi_dsi" }, { } };