colin/u-boot
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

imx: mx6ul/sx: fix mmdc_ch0 clk calculation

Browse Source 
Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.

Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
2016-01-06 11:06:31 +08:00
committed by Stefano Babic
parent 234dc63301
commit 9ba18ff8ef
2 changed files with 69 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/include/asm/arch-mx6/crm_regs.h
View File

@@ -1227,4 +1227,16 @@ struct mxc_ccm_reg {
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
#define BP_PMU_MISC2_AUDIO_DIV_MSB 23
#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15)
#define BP_PMU_MISC2_AUDIO_DIV_LSB 15
#define PMU_MISC2_AUDIO_DIV(v) \
(((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
(BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \
((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \
BP_PMU_MISC2_AUDIO_DIV_LSB))
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */