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Convert CONFIG_SPL_NAND_LOAD et al to Kconfig

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This converts the following to Kconfig:
   CONFIG_SPL_NAND_LOAD
   CONFIG_SYS_NAND_BLOCK_SIZE
   CONFIG_SYS_NAND_PAGE_SIZE
   CONFIG_SYS_NAND_OOBSIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2021-09-22 14:50:29 -04:00
parent ccdc7cfbdc
commit a0de075392
134 changed files with 185 additions and 195 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/configs/P1010RDB.h
View File

@@ -309,7 +309,6 @@ extern unsigned long get_sdram_size(void);
| CSOR_NAND_PGS_512 /* Page Size = 512b */ \
| CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
#elif defined(CONFIG_TARGET_P1010RDB_PB)
#define CONFIG_SYS_NAND_ONFI_DETECTION
@@ -320,7 +319,6 @@ extern unsigned long get_sdram_size(void);
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }

3
include/configs/P2041RDB.h
View File

@@ -171,7 +171,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -379,7 +378,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing

10
include/configs/T102xRDB.h
View File

@@ -264,7 +264,6 @@ unsigned long get_board_sys_clk(void);
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
@@ -273,7 +272,6 @@ unsigned long get_board_sys_clk(void);
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#endif
#define CONFIG_SYS_NAND_ONFI_DETECTION
@@ -520,14 +518,6 @@ unsigned long get_board_sys_clk(void);
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
#elif defined(CONFIG_MTD_RAW_NAND)
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
#endif
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing

6
include/configs/T104xRDB.h
View File

@@ -275,8 +275,6 @@
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
@@ -520,8 +518,6 @@
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
@@ -530,8 +526,6 @@
#define CONFIG_SYS_QE_FW_ADDR 0x130000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
#elif defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
#endif

3
include/configs/T208xQDS.h
View File

@@ -252,7 +252,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
@@ -500,8 +499,6 @@ unsigned long get_board_sys_clk(void);
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing

3
include/configs/T208xRDB.h
View File

@@ -226,7 +226,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
@@ -454,8 +453,6 @@ unsigned long get_board_sys_clk(void);
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing

4
include/configs/T4240RDB.h
View File

@@ -325,8 +325,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
@@ -475,8 +473,6 @@ unsigned long get_board_sys_clk(void);
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif

5
include/configs/am335x_evm.h
View File

@@ -183,9 +183,6 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
@@ -261,8 +258,6 @@
/* SPL related */
#elif defined(CONFIG_EMMC_BOOT)
#define CONFIG_SYS_MMC_MAX_DEVICE 2
#elif defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#endif
/* Network. */

3
include/configs/am335x_guardian.h
View File

@@ -110,9 +110,6 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 4096
#define CONFIG_SYS_NAND_OOBSIZE 256
#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \

3
include/configs/am335x_igep003x.h
View File

@@ -109,9 +109,6 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \

3
include/configs/am3517_evm.h
View File

@@ -21,9 +21,6 @@
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
11, 12, 13, 14, 16, 17, 18, 19, 20, \

3
include/configs/am43xx_evm.h
View File

@@ -157,9 +157,6 @@
/* NAND support */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
#define CONFIG_SYS_NAND_PAGE_SIZE 4096
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE

3
include/configs/at91sam9m10g45ek.h
View File

@@ -97,13 +97,10 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }

3
include/configs/at91sam9n12ek.h
View File

@@ -116,10 +116,7 @@
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif

3
include/configs/at91sam9x5ek.h
View File

@@ -99,10 +99,7 @@
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif

3
include/configs/baltos.h
View File

@@ -212,9 +212,6 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \

3
include/configs/brppt1.h
View File

@@ -147,11 +147,8 @@ NANDTGTS \
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \

3
include/configs/chiliboard.h
View File

@@ -126,9 +126,6 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \

3
include/configs/cm_t335.h
View File

@@ -88,9 +88,6 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \

3
include/configs/cm_t43.h
View File

@@ -24,9 +24,6 @@
/* NAND support */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14

3
include/configs/corenet_ds.h
View File

@@ -172,7 +172,6 @@
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -382,7 +381,7 @@
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing

3
include/configs/corvus.h
View File

@@ -99,14 +99,11 @@
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }

4
include/configs/da850evm.h
View File

@@ -122,8 +122,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
@@ -141,8 +139,6 @@
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 10
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SPL_NAND_LOAD
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_SELF_INIT

3
include/configs/devkit3250.h
View File

@@ -64,9 +64,6 @@
#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
/*
* USB
*/

3
include/configs/devkit8000.h
View File

@@ -135,9 +135,6 @@
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}

3
include/configs/dra7xx_evm.h
View File

@@ -80,9 +80,6 @@
/* NAND support */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE

6
include/configs/etamin.h
View File

@@ -14,9 +14,6 @@
#include "siemens-am33x-common.h"
/* NAND specific changes for etamin due to different page size */
#undef CONFIG_SYS_NAND_PAGE_SIZE
#undef CONFIG_SYS_NAND_OOBSIZE
#undef CONFIG_SYS_NAND_BLOCK_SIZE
#undef CONFIG_SYS_NAND_ECCPOS
#undef CONFIG_SYS_NAND_U_BOOT_OFFS
#undef CONFIG_SYS_ENV_SECT_SIZE
@@ -24,9 +21,6 @@
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */
#define CONFIG_SYS_NAND_PAGE_SIZE 4096
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \

3
include/configs/gardena-smart-gateway-at91sam.h
View File

@@ -61,10 +61,7 @@
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS

2
include/configs/ids8313.h
View File

@@ -131,8 +131,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define NAND_CACHE_PAGES 64

1
include/configs/km/pg-wcom-ls102xa.h
View File

@@ -141,7 +141,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* QRIO FPGA Definitions */
#define CONFIG_SYS_QRIO_BASE 0x70000000

3
include/configs/ls1021aqds.h
View File

@@ -47,7 +47,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
@@ -163,8 +162,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#endif
/*

5
include/configs/ls1043a_common.h
View File

@@ -174,10 +174,7 @@
#else
#ifdef CONFIG_NAND_BOOT
/* Store Fman ucode at offeset 0x900000(72 blocks). */
#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
#if defined(CONFIG_SD_BOOT)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* about 1MB (2040 blocks), Env is stored after the image, and the env size is

2
include/configs/ls1043aqds.h
View File

@@ -149,8 +149,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#endif
#ifdef CONFIG_NAND_BOOT

2
include/configs/ls1043ardb.h
View File

@@ -112,8 +112,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO

2
include/configs/ls1046a_common.h
View File

@@ -166,7 +166,7 @@
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_FMAN_FW_ADDR (36 * (256 * 1024))
#else
#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
#endif

2
include/configs/ls1046afrwy.h
View File

@@ -60,8 +60,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* IFC Timing Params */
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR

2
include/configs/ls1046aqds.h
View File

@@ -164,8 +164,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
#endif
#ifdef CONFIG_NAND_BOOT

2
include/configs/ls1046ardb.h
View File

@@ -72,8 +72,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/*
* CPLD
*/

2
include/configs/ls1088aqds.h
View File

@@ -134,8 +134,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_FSL_QIXIS
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6

2
include/configs/ls1088ardb.h
View File

@@ -113,8 +113,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#ifndef SPL_NO_QIXIS
#define CONFIG_FSL_QIXIS
#endif

2
include/configs/ls2080aqds.h
View File

@@ -139,8 +139,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f

1
include/configs/ls2080ardb.h
View File

@@ -147,7 +147,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#define CONFIG_FSL_QIXIS /* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH 0x06
#define QIXIS_LBMAP_MASK 0x0f

3
include/configs/m53menlo.h
View File

@@ -140,9 +140,6 @@
#define CONFIG_SPL_STACK 0x70004000
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)

3
include/configs/omap3_beagle.h
View File

@@ -24,9 +24,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}

3
include/configs/omap3_evm.h
View File

@@ -29,9 +29,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}

3
include/configs/omap3_igep00x0.h
View File

@@ -77,9 +77,6 @@
/* NAND config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \

3
include/configs/omap3_logic.h
View File

@@ -20,9 +20,6 @@
/* NAND devices */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
13, 14, 16, 17, 18, 19, 20, 21, 22, \

4
include/configs/omapl138_lcdk.h
View File

@@ -123,8 +123,6 @@
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
@@ -141,8 +139,6 @@
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 10
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SPL_NAND_LOAD
#endif
/*

5
include/configs/p1_p2_rdb_pc.h
View File

@@ -290,11 +290,6 @@
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#else
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
#endif
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \

5
include/configs/phycore_am335x_r2.h
View File

@@ -88,9 +88,6 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
@@ -116,8 +113,6 @@
#ifdef CONFIG_SPI_BOOT
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#elif defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#endif
#endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */

3
include/configs/pm9g45.h
View File

@@ -87,13 +87,10 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }

3
include/configs/sama5d3_xplained.h
View File

@@ -71,10 +71,7 @@
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
/* Falcon boot support on raw MMC */

3
include/configs/sama5d3xek.h
View File

@@ -83,10 +83,7 @@
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif

3
include/configs/sama5d4_xplained.h
View File

@@ -47,10 +47,7 @@
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif

3
include/configs/sama5d4ek.h
View File

@@ -47,10 +47,7 @@
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif

3
include/configs/siemens-am33x-common.h
View File

@@ -76,9 +76,6 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \

3
include/configs/smartweb.h
View File

@@ -169,14 +169,11 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_SIZE (SZ_256M)
#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }

3
include/configs/tam3517-common.h
View File

@@ -127,9 +127,6 @@
/* NAND boot config */
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\

3
include/configs/taurus.h
View File

@@ -171,14 +171,11 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }

4
include/configs/ti816x_evm.h
View File

@@ -60,9 +60,6 @@
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
@@ -78,7 +75,6 @@
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
/* SPL */
/* Defines for SPL */