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arm: dts: k3-am64: Update DDR Configurations

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Update the DDR Configurations for AM64x EVM according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
This commit is contained in:
Santhosh Kumar K
2025-02-26 12:09:19 +05:30
committed by Tom Rini
parent 57bbc4de75
commit a11f351ed4
1 changed files with 9 additions and 7 deletions
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16
arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
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@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40
* Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time)
* AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:01:31 GMT+0530 (India Standard Time)
* DDR Type: DDR4
* Frequency = 800MHz (1600MTs)
* Density: 16Gb
@@ -12,6 +12,8 @@
#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 15
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -178,7 +180,7 @@
#define DDRSS_CTL_162_DATA 0x0E0A0907
#define DDRSS_CTL_163_DATA 0x0A090000
#define DDRSS_CTL_164_DATA 0x0A090701
#define DDRSS_CTL_165_DATA 0x0000000E
#define DDRSS_CTL_165_DATA 0x0000080E
#define DDRSS_CTL_166_DATA 0x00040003
#define DDRSS_CTL_167_DATA 0x00000007
#define DDRSS_CTL_168_DATA 0x00000000
@@ -334,7 +336,7 @@
#define DDRSS_CTL_318_DATA 0x3FFF0000
#define DDRSS_CTL_319_DATA 0x000FFF00
#define DDRSS_CTL_320_DATA 0xFFFFFFFF
#define DDRSS_CTL_321_DATA 0x000FFF00
#define DDRSS_CTL_321_DATA 0x00FFFF00
#define DDRSS_CTL_322_DATA 0x0A000000
#define DDRSS_CTL_323_DATA 0x0001FFFF
#define DDRSS_CTL_324_DATA 0x01010101
@@ -901,7 +903,7 @@
#define DDRSS_PHY_117_DATA 0x00800080
#define DDRSS_PHY_118_DATA 0x00800080
#define DDRSS_PHY_119_DATA 0x01000080
#define DDRSS_PHY_120_DATA 0x01A00000
#define DDRSS_PHY_120_DATA 0x01000000
#define DDRSS_PHY_121_DATA 0x00000000
#define DDRSS_PHY_122_DATA 0x00000000
#define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1159,7 @@
#define DDRSS_PHY_373_DATA 0x00800080
#define DDRSS_PHY_374_DATA 0x00800080
#define DDRSS_PHY_375_DATA 0x01000080
#define DDRSS_PHY_376_DATA 0x01A00000
#define DDRSS_PHY_376_DATA 0x01000000
#define DDRSS_PHY_377_DATA 0x00000000
#define DDRSS_PHY_378_DATA 0x00000000
#define DDRSS_PHY_379_DATA 0x00080200
@@ -2152,7 +2154,7 @@
#define DDRSS_PHY_1368_DATA 0x00000002
#define DDRSS_PHY_1369_DATA 0x00000100
#define DDRSS_PHY_1370_DATA 0x00000000
#define DDRSS_PHY_1371_DATA 0x0001F7C0
#define DDRSS_PHY_1371_DATA 0x0001F7C2
#define DDRSS_PHY_1372_DATA 0x00020002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142