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Move arch/ppc to arch/powerpc

Browse Source 
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.

Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Stefan Roese
2010-04-15 16:07:28 +02:00
committed by Wolfgang Denk
parent 254ab7bd46
commit a47a12becf
579 changed files with 879 additions and 877 deletions
Download Patch File Download Diff File Expand all files Collapse all files

60
arch/powerpc/include/asm/4xx_pci.h Normal file
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@@ -0,0 +1,60 @@
#ifndef _405GP_PCI_H
#define _405GP_PCI_H
#include <pci.h>
/*----------------------------------------------------------------------------+
| 405GP PCI core memory map defines.
+----------------------------------------------------------------------------*/
#define MIN_PCI_MEMADDR1 0x80000000
#define MIN_PCI_MEMADDR2 0x00000000
#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */
#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */
#define MAX_PCI_DEVICES 32
/*----------------------------------------------------------------------------+
| Defines for the 405GP PCI Config address and data registers followed by
| defines for the standard PCI device configuration header.
+----------------------------------------------------------------------------*/
#define PCICFGADR 0xEEC00000
#define PCICFGDATA 0xEEC00004
#define PCIBUSNUM 0x40 /* 405GP specific parameters */
#define PCISUBBUSNUM 0x41
#define PCIDISCOUNT 0x42
#define PCIBRDGOPT1 0x4A
#define PCIBRDGOPT2 0x60
/*----------------------------------------------------------------------------+
| Defines for 405GP PCI Master local configuration regs.
+----------------------------------------------------------------------------*/
#define PMM0LA 0xEF400000
#define PMM0MA 0xEF400004
#define PMM0PCILA 0xEF400008
#define PMM0PCIHA 0xEF40000C
#define PMM1LA 0xEF400010
#define PMM1MA 0xEF400014
#define PMM1PCILA 0xEF400018
#define PMM1PCIHA 0xEF40001C
#define PMM2LA 0xEF400020
#define PMM2MA 0xEF400024
#define PMM2PCILA 0xEF400028
#define PMM2PCIHA 0xEF40002C
/*----------------------------------------------------------------------------+
| Defines for 405GP PCI Target local configuration regs.
+----------------------------------------------------------------------------*/
#define PTM1MS 0xEF400030
#define PTM1LA 0xEF400034
#define PTM2MS 0xEF400038
#define PTM2LA 0xEF40003C
#define PCIDEVID_405GP 0x0
void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
int pci_arbiter_enabled(void);
int __pci_pre_init(struct pci_controller *hose);
void __pci_target_init(struct pci_controller *hose);
void __pci_master_init(struct pci_controller *hose);
#endif

417
arch/powerpc/include/asm/4xx_pcie.h Normal file
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/*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
* Roland Dreier <rolandd@cisco.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __4XX_PCIE_H
#define __4XX_PCIE_H
#include <ppc4xx.h>
#include <pci.h>
#define DCRN_SDR0_CFGADDR 0x00e
#define DCRN_SDR0_CFGDATA 0x00f
#if defined(CONFIG_440SPE)
#define CONFIG_SYS_PCIE_NR_PORTS 3
#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
#define DCRN_PCIE2_BASE 0x140
#define PCIE0_SDR 0x300
#define PCIE1_SDR 0x340
#define PCIE2_SDR 0x370
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define CONFIG_SYS_PCIE_NR_PORTS 2
#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
#define PCIE0_SDR 0x300
#define PCIE1_SDR 0x340
#endif
#if defined(CONFIG_405EX)
#define CONFIG_SYS_PCIE_NR_PORTS 2
#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000
#define DCRN_PCIE0_BASE 0x040
#define DCRN_PCIE1_BASE 0x060
#define PCIE0_SDR 0x400
#define PCIE1_SDR 0x440
#endif
#define PCIE0 DCRN_PCIE0_BASE
#define PCIE1 DCRN_PCIE1_BASE
#define PCIE2 DCRN_PCIE2_BASE
#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
#define DCRN_PEGPL_CFG(base) (base + 0x16)
/*
* System DCRs (SDRs)
*/
#define PESDR0_PLLLCT1 0x03a0
#define PESDR0_PLLLCT2 0x03a1
#define PESDR0_PLLLCT3 0x03a2
/* common regs, at for all 4xx with PCIe core */
#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02)
#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03)
#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04)
#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05)
#if defined(CONFIG_440SPE)
#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06)
#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07)
#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08)
#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09)
#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a)
#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b)
#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c)
#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d)
#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e)
#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f)
#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10)
#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11)
#define PESDR0_UTLSET1 0x0300
#define PESDR0_UTLSET2 0x0301
#define PESDR0_DLPSET 0x0302
#define PESDR0_LOOP 0x0303
#define PESDR0_RCSSET 0x0304
#define PESDR0_RCSSTS 0x0305
#define PESDR0_HSSL0SET1 0x0306
#define PESDR0_HSSL0SET2 0x0307
#define PESDR0_HSSL0STS 0x0308
#define PESDR0_HSSL1SET1 0x0309
#define PESDR0_HSSL1SET2 0x030a
#define PESDR0_HSSL1STS 0x030b
#define PESDR0_HSSL2SET1 0x030c
#define PESDR0_HSSL2SET2 0x030d
#define PESDR0_HSSL2STS 0x030e
#define PESDR0_HSSL3SET1 0x030f
#define PESDR0_HSSL3SET2 0x0310
#define PESDR0_HSSL3STS 0x0311
#define PESDR0_HSSL4SET1 0x0312
#define PESDR0_HSSL4SET2 0x0313
#define PESDR0_HSSL4STS 0x0314
#define PESDR0_HSSL5SET1 0x0315
#define PESDR0_HSSL5SET2 0x0316
#define PESDR0_HSSL5STS 0x0317
#define PESDR0_HSSL6SET1 0x0318
#define PESDR0_HSSL6SET2 0x0319
#define PESDR0_HSSL6STS 0x031a
#define PESDR0_HSSL7SET1 0x031b
#define PESDR0_HSSL7SET2 0x031c
#define PESDR0_HSSL7STS 0x031d
#define PESDR0_HSSCTLSET 0x031e
#define PESDR0_LANE_ABCD 0x031f
#define PESDR0_LANE_EFGH 0x0320
#define PESDR1_UTLSET1 0x0340
#define PESDR1_UTLSET2 0x0341
#define PESDR1_DLPSET 0x0342
#define PESDR1_LOOP 0x0343
#define PESDR1_RCSSET 0x0344
#define PESDR1_RCSSTS 0x0345
#define PESDR1_HSSL0SET1 0x0346
#define PESDR1_HSSL0SET2 0x0347
#define PESDR1_HSSL0STS 0x0348
#define PESDR1_HSSL1SET1 0x0349
#define PESDR1_HSSL1SET2 0x034a
#define PESDR1_HSSL1STS 0x034b
#define PESDR1_HSSL2SET1 0x034c
#define PESDR1_HSSL2SET2 0x034d
#define PESDR1_HSSL2STS 0x034e
#define PESDR1_HSSL3SET1 0x034f
#define PESDR1_HSSL3SET2 0x0350
#define PESDR1_HSSL3STS 0x0351
#define PESDR1_HSSCTLSET 0x0352
#define PESDR1_LANE_ABCD 0x0353
#define PESDR2_UTLSET1 0x0370
#define PESDR2_UTLSET2 0x0371
#define PESDR2_DLPSET 0x0372
#define PESDR2_LOOP 0x0373
#define PESDR2_RCSSET 0x0374
#define PESDR2_RCSSTS 0x0375
#define PESDR2_HSSL0SET1 0x0376
#define PESDR2_HSSL0SET2 0x0377
#define PESDR2_HSSL0STS 0x0378
#define PESDR2_HSSL1SET1 0x0379
#define PESDR2_HSSL1SET2 0x037a
#define PESDR2_HSSL1STS 0x037b
#define PESDR2_HSSL2SET1 0x037c
#define PESDR2_HSSL2SET2 0x037d
#define PESDR2_HSSL2STS 0x037e
#define PESDR2_HSSL3SET1 0x037f
#define PESDR2_HSSL3SET2 0x0380
#define PESDR2_HSSL3STS 0x0381
#define PESDR2_HSSCTLSET 0x0382
#define PESDR2_LANE_ABCD 0x0383
#elif defined(CONFIG_405EX)
#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06)
#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07)
#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08)
#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b)
#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c)
#define PESDR0_UTLSET1 0x0400
#define PESDR0_UTLSET2 0x0401
#define PESDR0_DLPSET 0x0402
#define PESDR0_LOOP 0x0403
#define PESDR0_RCSSET 0x0404
#define PESDR0_RCSSTS 0x0405
#define PESDR0_PHYSET1 0x0406
#define PESDR0_PHYSET2 0x0407
#define PESDR0_BIST 0x0408
#define PESDR0_LPB 0x040B
#define PESDR0_PHYSTA 0x040C
#define PESDR1_UTLSET1 0x0440
#define PESDR1_UTLSET2 0x0441
#define PESDR1_DLPSET 0x0442
#define PESDR1_LOOP 0x0443
#define PESDR1_RCSSET 0x0444
#define PESDR1_RCSSTS 0x0445
#define PESDR1_PHYSET1 0x0446
#define PESDR1_PHYSET2 0x0447
#define PESDR1_BIST 0x0448
#define PESDR1_LPB 0x044B
#define PESDR1_PHYSTA 0x044C
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define PESDR0_L0BIST 0x0308 /* PE0 L0 built in self test */
#define PESDR0_L0BISTSTS 0x0309 /* PE0 L0 built in self test status */
#define PESDR0_L0CDRCTL 0x030A /* PE0 L0 CDR control */
#define PESDR0_L0DRV 0x030B /* PE0 L0 drive */
#define PESDR0_L0REC 0x030C /* PE0 L0 receiver */
#define PESDR0_L0LPB 0x030D /* PE0 L0 loopback */
#define PESDR0_L0CLK 0x030E /* PE0 L0 clocking */
#define PESDR0_PHY_CTL_RST 0x030F /* PE0 PHY control reset */
#define PESDR0_RSTSTA 0x0310 /* PE0 reset status */
#define PESDR0_OBS 0x0311 /* PE0 observation register */
#define PESDR0_L0ERRC 0x0320 /* PE0 L0 error counter */
#define PESDR1_L0BIST 0x0348 /* PE1 L0 built in self test */
#define PESDR1_L1BIST 0x0349 /* PE1 L1 built in self test */
#define PESDR1_L2BIST 0x034A /* PE1 L2 built in self test */
#define PESDR1_L3BIST 0x034B /* PE1 L3 built in self test */
#define PESDR1_L0BISTSTS 0x034C /* PE1 L0 built in self test status */
#define PESDR1_L1BISTSTS 0x034D /* PE1 L1 built in self test status */
#define PESDR1_L2BISTSTS 0x034E /* PE1 L2 built in self test status */
#define PESDR1_L3BISTSTS 0x034F /* PE1 L3 built in self test status */
#define PESDR1_L0CDRCTL 0x0350 /* PE1 L0 CDR control */
#define PESDR1_L1CDRCTL 0x0351 /* PE1 L1 CDR control */
#define PESDR1_L2CDRCTL 0x0352 /* PE1 L2 CDR control */
#define PESDR1_L3CDRCTL 0x0353 /* PE1 L3 CDR control */
#define PESDR1_L0DRV 0x0354 /* PE1 L0 drive */
#define PESDR1_L1DRV 0x0355 /* PE1 L1 drive */
#define PESDR1_L2DRV 0x0356 /* PE1 L2 drive */
#define PESDR1_L3DRV 0x0357 /* PE1 L3 drive */
#define PESDR1_L0REC 0x0358 /* PE1 L0 receiver */
#define PESDR1_L1REC 0x0359 /* PE1 L1 receiver */
#define PESDR1_L2REC 0x035A /* PE1 L2 receiver */
#define PESDR1_L3REC 0x035B /* PE1 L3 receiver */
#define PESDR1_L0LPB 0x035C /* PE1 L0 loopback */
#define PESDR1_L1LPB 0x035D /* PE1 L1 loopback */
#define PESDR1_L2LPB 0x035E /* PE1 L2 loopback */
#define PESDR1_L3LPB 0x035F /* PE1 L3 loopback */
#define PESDR1_L0CLK 0x0360 /* PE1 L0 clocking */
#define PESDR1_L1CLK 0x0361 /* PE1 L1 clocking */
#define PESDR1_L2CLK 0x0362 /* PE1 L2 clocking */
#define PESDR1_L3CLK 0x0363 /* PE1 L3 clocking */
#define PESDR1_PHY_CTL_RST 0x0364 /* PE1 PHY control reset */
#define PESDR1_RSTSTA 0x0365 /* PE1 reset status */
#define PESDR1_OBS 0x0366 /* PE1 observation register */
#define PESDR1_L0ERRC 0x0368 /* PE1 L0 error counter */
#define PESDR1_L1ERRC 0x0369 /* PE1 L1 error counter */
#define PESDR1_L2ERRC 0x036A /* PE1 L2 error counter */
#define PESDR1_L3ERRC 0x036B /* PE1 L3 error counter */
#define PESDR0_IHS1 0x036C /* PE interrupt handler interfact setting 1 */
#define PESDR0_IHS2 0x036D /* PE interrupt handler interfact setting 2 */
#endif
/* SDR Bit Mappings */
#define PESDRx_RCSSET_HLDPLB 0x10000000
#define PESDRx_RCSSET_RSTGU 0x01000000
#define PESDRx_RCSSET_RDY 0x00100000
#define PESDRx_RCSSET_RSTDL 0x00010000
#define PESDRx_RCSSET_RSTPYN 0x00001000
#define PESDRx_RCSSTS_PLBIDL 0x10000000
#define PESDRx_RCSSTS_HRSTRQ 0x01000000
#define PESDRx_RCSSTS_PGRST 0x00100000
#define PESDRx_RCSSTS_VC0ACT 0x00010000
#define PESDRx_RCSSTS_BMEN 0x00000100
/*
* UTL register offsets
*/
#define PEUTL_PBCTL 0x00
#define PEUTL_PBBSZ 0x20
#define PEUTL_OPDBSZ 0x68
#define PEUTL_IPHBSZ 0x70
#define PEUTL_IPDBSZ 0x78
#define PEUTL_OUTTR 0x90
#define PEUTL_INTR 0x98
#define PEUTL_PCTL 0xa0
#define PEUTL_RCSTA 0xb0
#define PEUTL_RCIRQEN 0xb8
/*
* Config space register offsets
*/
#define PECFG_BAR0LMPA 0x210
#define PECFG_BAR0HMPA 0x214
#define PECFG_BAR1MPA 0x218
#define PECFG_BAR2LMPA 0x220
#define PECFG_BAR2HMPA 0x224
#define PECFG_PIMEN 0x33c
#define PECFG_PIM0LAL 0x340
#define PECFG_PIM0LAH 0x344
#define PECFG_PIM1LAL 0x348
#define PECFG_PIM1LAH 0x34c
#define PECFG_PIM01SAL 0x350
#define PECFG_PIM01SAH 0x354
#define PECFG_POM0LAL 0x380
#define PECFG_POM0LAH 0x384
#define SDR_READ(offset) ({\
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mfdcr(DCRN_SDR0_CFGDATA);})
#define SDR_WRITE(offset, data) ({\
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mtdcr(DCRN_SDR0_CFGDATA,data);})
#define GPL_DMER_MASK_DISA 0x02000000
#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
/*
* Prototypes
*/
int ppc4xx_init_pcie(void);
int ppc4xx_init_pcie_rootport(int port);
int ppc4xx_init_pcie_endport(int port);
void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
int pcie_hose_scan(struct pci_controller *hose, int bus);
/*
* Function to determine root port or endport from env variable.
*/
static inline int is_end_point(int port)
{
char s[10], *tk;
char *pcie_mode = getenv("pcie_mode");
if (pcie_mode == NULL)
return 0;
strcpy(s, pcie_mode);
tk = strtok(s, ":");
switch (port) {
case 0:
if (tk != NULL) {
if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
return 1;
else
return 0;
}
else
return 0;
case 1:
tk = strtok(NULL, ":");
if (tk != NULL) {
if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
return 1;
else
return 0;
}
else
return 0;
case 2:
tk = strtok(NULL, ":");
if (tk != NULL)
tk = strtok(NULL, ":");
if (tk != NULL) {
if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
return 1;
else
return 0;
}
else
return 0;
}
return 0;
}
static inline void mdelay(int n)
{
u32 ms = n;
while (ms--)
udelay(1000);
}
#if defined(PCIE0_SDR)
static inline u32 sdr_base(int port)
{
switch (port) {
default: /* to satisfy compiler */
case 0:
return PCIE0_SDR;
case 1:
return PCIE1_SDR;
#if CONFIG_SYS_PCIE_NR_PORTS > 2
case 2:
return PCIE2_SDR;
#endif
}
}
#endif /* defined(PCIE0_SDR) */
#endif /* __4XX_PCIE_H */

439
arch/powerpc/include/asm/5xx_immap.h Normal file
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/*
* (C) Copyright 2003
* Martin Winistoerfer, martinwinistoerfer@gmx.ch.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation,
*/
/*
* File: 5xx_immap.h
*
* Discription: MPC555 Internal Memory Map
*
*/
#ifndef __IMMAP_5XX__
#define __IMMAP_5XX__
/* System Configuration Registers.
*/
typedef struct sys_conf {
uint sc_siumcr;
uint sc_sypcr;
char res1[6];
ushort sc_swsr;
uint sc_sipend;
uint sc_simask;
uint sc_siel;
uint sc_sivec;
uint sc_tesr;
uint sc_sgpiodt1;
uint sc_sgpiodt2;
uint sc_sgpiocr;
uint sc_emcr;
uint sc_res1aa;
uint sc_res1ab;
uint sc_pdmcr;
char res3[192];
} sysconf5xx_t;
/* Memory Controller Registers.
*/
typedef struct mem_ctlr {
uint memc_br0;
uint memc_or0;
uint memc_br1;
uint memc_or1;
uint memc_br2;
uint memc_or2;
uint memc_br3;
uint memc_or3;
char res1[32];
uint memc_dmbr;
uint memc_dmor;
char res2[48];
ushort memc_mstat;
ushort memc_res4a;
char res3[132];
} memctl5xx_t;
/* System Integration Timers.
*/
typedef struct sys_int_timers {
ushort sit_tbscr;
char res1[2];
uint sit_tbref0;
uint sit_tbref1;
char res2[20];
ushort sit_rtcsc;
char res3[2];
uint sit_rtc;
uint sit_rtsec;
uint sit_rtcal;
char res4[16];
ushort sit_piscr;
char res5[2];
uint sit_pitc;
uint sit_pitr;
char res6[52];
} sit5xx_t;
/* Clocks and Reset
*/
typedef struct clk_and_reset {
uint car_sccr;
uint car_plprcr;
ushort car_rsr;
ushort car_res7a;
ushort car_colir;
ushort car_res7b;
ushort car_vsrmcr;
ushort car_res7c;
char res1[108];
} car5xx_t;
#define TBSCR_TBE ((ushort)0x0001)
/* System Integration Timer Keys
*/
typedef struct sitk {
uint sitk_tbscrk;
uint sitk_tbref0k;
uint sitk_tbref1k;
uint sitk_tbk;
char res1[16];
uint sitk_rtcsck;
uint sitk_rtck;
uint sitk_rtseck;
uint sitk_rtcalk;
char res2[16];
uint sitk_piscrk;
uint sitk_pitck;
char res3[56];
} sitk5xx_t;
/* Clocks and Reset Keys.
*/
typedef struct cark {
uint cark_sccrk;
uint cark_plprcrk;
uint cark_rsrk;
char res1[1140];
} cark8xx_t;
/* The key to unlock registers maintained by keep-alive power.
*/
#define KAPWR_KEY ((unsigned int)0x55ccaa33)
/* Flash Configuration
*/
typedef struct fl {
uint fl_cmfmcr;
uint fl_cmftst;
uint fl_cmfctl;
char res1[52];
} fl5xx_t;
/* Dpram Control
*/
typedef struct dprc {
ushort dprc_dptmcr;
ushort dprc_ramtst;
ushort dprc_rambar;
ushort dprc_misrh;
ushort dprc_misrl;
ushort dprc_miscnt;
} dprc5xx_t;
/* Time Processor Unit
*/
typedef struct tpu {
ushort tpu_tpumcr;
ushort tpu_tcr;
ushort tpu_dscr;
ushort tpu_dssr;
ushort tpu_ticr;
ushort tpu_cier;
ushort tpu_cfsr0;
ushort tpu_cfsr1;
ushort tpu_cfsr2;
ushort tpu_cfsr3;
ushort tpu_hsqr0;
ushort tpu_hsqr1;
ushort tpu_hsrr0;
ushort tpu_hsrr1;
ushort tpu_cpr0;
ushort tpu_cpr1;
ushort tpu_cisr;
ushort tpu_lr;
ushort tpu_sglr;
ushort tpu_dcnr;
ushort tpu_tpumcr2;
ushort tpu_tpumcr3;
ushort tpu_isdr;
ushort tpu_iscr;
char res1[208];
char tpu[16][16];
char res2[512];
} tpu5xx_t;
/* QADC
*/
typedef struct qadc {
ushort qadc_64mcr;
ushort qadc_64test;
ushort qadc_64int;
u_char qadc_portqa;
u_char qadc_portqb;
ushort qadc_ddrqa;
ushort qadc_qacr0;
ushort qadc_qacr1;
ushort qadc_qacr2;
ushort qadc_qasr0;
ushort qadc_qasr1;
char res1[492];
/* command convertion word table */
ushort qadc_ccw[64];
/* result word table, unsigned right justified */
ushort qadc_rjurr[64];
/* result word table, signed left justified */
ushort qadc_ljsrr[64];
/* result word table, unsigned left justified */
ushort qadc_ljurr[64];
} qadc5xx_t;
/* QSMCM
*/
typedef struct qsmcm {
ushort qsmcm_qsmcr;
ushort qsmcm_qtest;
ushort qsmcm_qdsci_il;
ushort qsmcm_qspi_il;
ushort qsmcm_scc1r0;
ushort qsmcm_scc1r1;
ushort qsmcm_sc1sr;
ushort qsmcm_sc1dr;
char res1[2];
char res2[2];
ushort qsmcm_portqs;
u_char qsmcm_pqspar;
u_char qsmcm_ddrqs;
ushort qsmcm_spcr0;
ushort qsmcm_spcr1;
ushort qsmcm_spcr2;
u_char qsmcm_spcr3;
u_char qsmcm_spsr;
ushort qsmcm_scc2r0;
ushort qsmcm_scc2r1;
ushort qsmcm_sc2sr;
ushort qsmcm_sc2dr;
ushort qsmcm_qsci1cr;
ushort qsmcm_qsci1sr;
ushort qsmcm_sctq[16];
ushort qsmcm_scrq[16];
char res3[212];
ushort qsmcm_recram[32];
ushort qsmcm_tranram[32];
u_char qsmcm_comdram[32];
char res[3616];
} qsmcm5xx_t;
/* MIOS
*/
typedef struct mios {
ushort mios_mpwmsm0perr; /* mpwmsm0 */
ushort mios_mpwmsm0pulr;
ushort mios_mpwmsm0cntr;
ushort mios_mpwmsm0scr;
ushort mios_mpwmsm1perr; /* mpwmsm1 */
ushort mios_mpwmsm1pulr;
ushort mios_mpwmsm1cntr;
ushort mios_mpwmsm1scr;
ushort mios_mpwmsm2perr; /* mpwmsm2 */
ushort mios_mpwmsm2pulr;
ushort mios_mpwmsm2cntr;
ushort mios_mpwmsm2scr;
ushort mios_mpwmsm3perr; /* mpwmsm3 */
ushort mios_mpwmsm3pulr;
ushort mios_mpwmsm3cntr;
ushort mios_mpwmsm3scr;
char res1[16];
ushort mios_mmcsm6cnt; /* mmcsm6 */
ushort mios_mmcsm6mlr;
ushort mios_mmcsm6scrd, mmcsm6scr;
char res2[32];
ushort mios_mdasm11ar; /* mdasm11 */
ushort mios_mdasm11br;
ushort mios_mdasm11scrd, mdasm11scr;
ushort mios_mdasm12ar; /* mdasm12 */
ushort mios_mdasm12br;
ushort mios_mdasm12scrd, mdasm12scr;
ushort mios_mdasm13ar; /* mdasm13 */
ushort mios_mdasm13br;
ushort mios_mdasm13scrd, mdasm13scr;
ushort mios_mdasm14ar; /* mdasm14 */
ushort mios_mdasm14br;
ushort mios_mdasm14scrd, mdasm14scr;
ushort mios_mdasm15ar; /* mdasm15 */
ushort mios_mdasm15br;
ushort mios_mdasm15scrd, mdasm15scr;
ushort mios_mpwmsm16perr; /* mpwmsm16 */
ushort mios_mpwmsm16pulr;
ushort mios_mpwmsm16cntr;
ushort mios_mpwmsm16scr;
ushort mios_mpwmsm17perr; /* mpwmsm17 */
ushort mios_mpwmsm17pulr;
ushort mios_mpwmsm17cntr;
ushort mios_mpwmsm17scr;
ushort mios_mpwmsm18perr; /* mpwmsm18 */
ushort mios_mpwmsm18pulr;
ushort mios_mpwmsm18cntr;
ushort mios_mpwmsm18scr;
ushort mios_mpwmsm19perr; /* mpwmsm19 */
ushort mios_mpwmsm19pulr;
ushort mios_mpwmsm19cntr;
ushort mios_mpwmsm19scr;
char res3[16];
ushort mios_mmcsm22cnt; /* mmcsm22 */
ushort mios_mmcsm22mlr;
ushort mios_mmcsm22scrd, mmcsm22scr;
char res4[32];
ushort mios_mdasm27ar; /* mdasm27 */
ushort mios_mdasm27br;
ushort mios_mdasm27scrd, mdasm27scr;
ushort mios_mdasm28ar; /*mdasm28 */
ushort mios_mdasm28br;
ushort mios_mdasm28scrd, mdasm28scr;
ushort mios_mdasm29ar; /* mdasm29 */
ushort mios_mdasm29br;
ushort mios_mdasm29scrd, mdasm29scr;
ushort mios_mdasm30ar; /* mdasm30 */
ushort mios_mdasm30br;
ushort mios_mdasm30scrd, mdasm30scr;
ushort mios_mdasm31ar; /* mdasm31 */
ushort mios_mdasm31br;
ushort mios_mdasm31scrd, mdasm31scr;
ushort mios_mpiosm32dr;
ushort mios_mpiosm32ddr;
char res5[1788];
ushort mios_mios1tpcr;
char mios_res13[2];
ushort mios_mios1vnr;
ushort mios_mios1mcr;
char res6[12];
ushort mios_res42z;
ushort mios_mcpsmscr;
char res7[1000];
ushort mios_mios1sr0;
char res12[2];
ushort mios_mios1er0;
ushort mios_mios1rpr0;
char res8[40];
ushort mios_mios1lvl0;
char res9[14];
ushort mios_mios1sr1;
char res10[2];
ushort mios_mios1er1;
ushort mios_mios1rpr1;
char res11[40];
ushort mios_mios1lvl1;
char res13[1038];
} mios5xx_t;
/* Toucan Module
*/
typedef struct tcan {
ushort tcan_tcnmcr;
ushort tcan_cantcr;
ushort tcan_canicr;
u_char tcan_canctrl0;
u_char tcan_canctrl1;
u_char tcan_presdiv;
u_char tcan_canctrl2;
ushort tcan_timer;
char res1[4];
ushort tcan_rxgmskhi;
ushort tcan_rxgmsklo;
ushort tcan_rx14mskhi;
ushort tcan_rx14msklo;
ushort tcan_rx15mskhi;
ushort tcan_rx15msklo;
char res2[4];
ushort tcan_estat;
ushort tcan_imask;
ushort tcan_iflag;
u_char tcan_rxectr;
u_char tcan_txectr;
char res3[88];
struct {
ushort scr;
ushort id_high;
ushort id_low;
u_char data[8];
char res4[2];
} tcan_mbuff[16];
char res5[640];
} tcan5xx_t;
/* UIMB
*/
typedef struct uimb {
uint uimb_umcr;
char res1[12];
uint uimb_utstcreg;
char res2[12];
uint uimb_uipend;
} uimb5xx_t;
/* Internal Memory Map MPC555
*/
typedef struct immap {
char res1[262144]; /* CMF Flash A 256 Kbytes */
char res2[196608]; /* CMF Flash B 192 Kbytes */
char res3[2670592]; /* Reserved for Flash */
sysconf5xx_t im_siu_conf; /* SIU Configuration */
memctl5xx_t im_memctl; /* Memory Controller */
sit5xx_t im_sit; /* System Integration Timers */
car5xx_t im_clkrst; /* Clocks and Reset */
sitk5xx_t im_sitk; /* System Integration Timer Keys*/
cark8xx_t im_clkrstk; /* Clocks and Resert Keys */
fl5xx_t im_fla; /* Flash Module A */
fl5xx_t im_flb; /* Flash Module B */
char res4[14208]; /* Reserved for SIU */
dprc5xx_t im_dprc; /* Dpram Control Register */
char res5[8180]; /* Reserved */
char dptram[6144]; /* Dptram */
char res6[2048]; /* Reserved */
tpu5xx_t im_tpua; /* Time Proessing Unit A */
tpu5xx_t im_tpub; /* Time Processing Unit B */
qadc5xx_t im_qadca; /* QADC A */
qadc5xx_t im_qadcb; /* QADC B */
qsmcm5xx_t im_qsmcm; /* SCI and SPI */
mios5xx_t im_mios; /* MIOS */
tcan5xx_t im_tcana; /* Toucan A */
tcan5xx_t im_tcanb; /* Toucan B */
char res7[1792]; /* Reserved */
uimb5xx_t im_uimb; /* UIMB */
} immap_t;
#endif /* __IMMAP_5XX__ */

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arch/powerpc/include/asm/8xx_immap.h Normal file
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/*
* MPC8xx Internal Memory Map
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* The I/O on the MPC860 is comprised of blocks of special registers
* and the dual port ram for the Communication Processor Module.
* Within this space are functional units such as the SIU, memory
* controller, system timers, and other control functions. It is
* a combination that I found difficult to separate into logical
* functional files.....but anyone else is welcome to try. -- Dan
*/
#ifndef __IMMAP_8XX__
#define __IMMAP_8XX__
/* System configuration registers.
*/
typedef struct sys_conf {
uint sc_siumcr;
uint sc_sypcr;
uint sc_swt;
char res1[2];
ushort sc_swsr;
uint sc_sipend;
uint sc_simask;
uint sc_siel;
uint sc_sivec;
uint sc_tesr;
char res2[0xc];
uint sc_sdcr;
char res3[0x4c];
} sysconf8xx_t;
/* PCMCIA configuration registers.
*/
typedef struct pcmcia_conf {
uint pcmc_pbr0;
uint pcmc_por0;
uint pcmc_pbr1;
uint pcmc_por1;
uint pcmc_pbr2;
uint pcmc_por2;
uint pcmc_pbr3;
uint pcmc_por3;
uint pcmc_pbr4;
uint pcmc_por4;
uint pcmc_pbr5;
uint pcmc_por5;
uint pcmc_pbr6;
uint pcmc_por6;
uint pcmc_pbr7;
uint pcmc_por7;
char res1[0x20];
uint pcmc_pgcra;
uint pcmc_pgcrb;
uint pcmc_pscr;
char res2[4];
uint pcmc_pipr;
char res3[4];
uint pcmc_per;
char res4[4];
} pcmconf8xx_t;
/* Memory controller registers.
*/
typedef struct mem_ctlr {
uint memc_br0;
uint memc_or0;
uint memc_br1;
uint memc_or1;
uint memc_br2;
uint memc_or2;
uint memc_br3;
uint memc_or3;
uint memc_br4;
uint memc_or4;
uint memc_br5;
uint memc_or5;
uint memc_br6;
uint memc_or6;
uint memc_br7;
uint memc_or7;
char res1[0x24];
uint memc_mar;
uint memc_mcr;
char res2[4];
uint memc_mamr;
uint memc_mbmr;
ushort memc_mstat;
ushort memc_mptpr;
uint memc_mdr;
char res3[0x80];
} memctl8xx_t;
/* System Integration Timers.
*/
typedef struct sys_int_timers {
ushort sit_tbscr;
char res0[0x02];
uint sit_tbreff0;
uint sit_tbreff1;
char res1[0x14];
ushort sit_rtcsc;
char res2[0x02];
uint sit_rtc;
uint sit_rtsec;
uint sit_rtcal;
char res3[0x10];
ushort sit_piscr;
char res4[2];
uint sit_pitc;
uint sit_pitr;
char res5[0x34];
} sit8xx_t;
#define TBSCR_TBIRQ_MASK ((ushort)0xff00)
#define TBSCR_REFA ((ushort)0x0080)
#define TBSCR_REFB ((ushort)0x0040)
#define TBSCR_REFAE ((ushort)0x0008)
#define TBSCR_REFBE ((ushort)0x0004)
#define TBSCR_TBF ((ushort)0x0002)
#define TBSCR_TBE ((ushort)0x0001)
#define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
#define RTCSC_SEC ((ushort)0x0080)
#define RTCSC_ALR ((ushort)0x0040)
#define RTCSC_38K ((ushort)0x0010)
#define RTCSC_SIE ((ushort)0x0008)
#define RTCSC_ALE ((ushort)0x0004)
#define RTCSC_RTF ((ushort)0x0002)
#define RTCSC_RTE ((ushort)0x0001)
#define PISCR_PIRQ_MASK ((ushort)0xff00)
#define PISCR_PS ((ushort)0x0080)
#define PISCR_PIE ((ushort)0x0004)
#define PISCR_PTF ((ushort)0x0002)
#define PISCR_PTE ((ushort)0x0001)
/* Clocks and Reset.
*/
typedef struct clk_and_reset {
uint car_sccr;
uint car_plprcr;
uint car_rsr;
char res[0x74]; /* Reserved area */
} car8xx_t;
/* System Integration Timers keys.
*/
typedef struct sitk {
uint sitk_tbscrk;
uint sitk_tbreff0k;
uint sitk_tbreff1k;
uint sitk_tbk;
char res1[0x10];
uint sitk_rtcsck;
uint sitk_rtck;
uint sitk_rtseck;
uint sitk_rtcalk;
char res2[0x10];
uint sitk_piscrk;
uint sitk_pitck;
char res3[0x38];
} sitk8xx_t;
/* Clocks and reset keys.
*/
typedef struct cark {
uint cark_sccrk;
uint cark_plprcrk;
uint cark_rsrk;
char res[0x474];
} cark8xx_t;
/* The key to unlock registers maintained by keep-alive power.
*/
#define KAPWR_KEY ((unsigned int)0x55ccaa33)
/* Video interface. MPC823 Only.
*/
typedef struct vid823 {
ushort vid_vccr;
ushort res1;
u_char vid_vsr;
u_char res2;
u_char vid_vcmr;
u_char res3;
uint vid_vbcb;
uint res4;
uint vid_vfcr0;
uint vid_vfaa0;
uint vid_vfba0;
uint vid_vfcr1;
uint vid_vfaa1;
uint vid_vfba1;
u_char res5[0x18];
} vid823_t;
/* LCD interface. 823 Only.
*/
typedef struct lcd {
uint lcd_lccr;
uint lcd_lchcr;
uint lcd_lcvcr;
char res1[4];
uint lcd_lcfaa;
uint lcd_lcfba;
char lcd_lcsr;
char res2[0x7];
} lcd823_t;
/* I2C
*/
typedef struct i2c {
u_char i2c_i2mod;
char res1[3];
u_char i2c_i2add;
char res2[3];
u_char i2c_i2brg;
char res3[3];
u_char i2c_i2com;
char res4[3];
u_char i2c_i2cer;
char res5[3];
u_char i2c_i2cmr;
char res6[0x8b];
} i2c8xx_t;
/* DMA control/status registers.
*/
typedef struct sdma_csr {
char res1[4];
uint sdma_sdar;
u_char sdma_sdsr;
char res3[3];
u_char sdma_sdmr;
char res4[3];
u_char sdma_idsr1;
char res5[3];
u_char sdma_idmr1;
char res6[3];
u_char sdma_idsr2;
char res7[3];
u_char sdma_idmr2;
char res8[0x13];
} sdma8xx_t;
/* Communication Processor Module Interrupt Controller.
*/
typedef struct cpm_ic {
ushort cpic_civr;
char res[0xe];
uint cpic_cicr;
uint cpic_cipr;
uint cpic_cimr;
uint cpic_cisr;
} cpic8xx_t;
/* Input/Output Port control/status registers.
*/
typedef struct io_port {
ushort iop_padir;
ushort iop_papar;
ushort iop_paodr;
ushort iop_padat;
char res1[8];
ushort iop_pcdir;
ushort iop_pcpar;
ushort iop_pcso;
ushort iop_pcdat;
ushort iop_pcint;
char res2[6];
ushort iop_pddir;
ushort iop_pdpar;
char res3[2];
ushort iop_pddat;
uint utmode;
char res4[4];
} iop8xx_t;
/* Communication Processor Module Timers
*/
typedef struct cpm_timers {
ushort cpmt_tgcr;
char res1[0xe];
ushort cpmt_tmr1;
ushort cpmt_tmr2;
ushort cpmt_trr1;
ushort cpmt_trr2;
ushort cpmt_tcr1;
ushort cpmt_tcr2;
ushort cpmt_tcn1;
ushort cpmt_tcn2;
ushort cpmt_tmr3;
ushort cpmt_tmr4;
ushort cpmt_trr3;
ushort cpmt_trr4;
ushort cpmt_tcr3;
ushort cpmt_tcr4;
ushort cpmt_tcn3;
ushort cpmt_tcn4;
ushort cpmt_ter1;
ushort cpmt_ter2;
ushort cpmt_ter3;
ushort cpmt_ter4;
char res2[8];
} cpmtimer8xx_t;
/* Finally, the Communication Processor stuff.....
*/
typedef struct scc { /* Serial communication channels */
uint scc_gsmrl;
uint scc_gsmrh;
ushort scc_psmr;
char res1[2];
ushort scc_todr;
ushort scc_dsr;
ushort scc_scce;
char res2[2];
ushort scc_sccm;
char res3;
u_char scc_sccs;
char res4[8];
} scc_t;
typedef struct smc { /* Serial management channels */
char res1[2];
ushort smc_smcmr;
char res2[2];
u_char smc_smce;
char res3[3];
u_char smc_smcm;
char res4[5];
} smc_t;
/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
* it fits within the address space.
*/
typedef struct fec {
uint fec_addr_low; /* lower 32 bits of station address */
ushort fec_addr_high; /* upper 16 bits of station address */
ushort res1; /* reserved */
uint fec_hash_table_high; /* upper 32-bits of hash table */
uint fec_hash_table_low; /* lower 32-bits of hash table */
uint fec_r_des_start; /* beginning of Rx descriptor ring */
uint fec_x_des_start; /* beginning of Tx descriptor ring */
uint fec_r_buff_size; /* Rx buffer size */
uint res2[9]; /* reserved */
uint fec_ecntrl; /* ethernet control register */
uint fec_ievent; /* interrupt event register */
uint fec_imask; /* interrupt mask register */
uint fec_ivec; /* interrupt level and vector status */
uint fec_r_des_active; /* Rx ring updated flag */
uint fec_x_des_active; /* Tx ring updated flag */
uint res3[10]; /* reserved */
uint fec_mii_data; /* MII data register */
uint fec_mii_speed; /* MII speed control register */
uint res4[17]; /* reserved */
uint fec_r_bound; /* end of RAM (read-only) */
uint fec_r_fstart; /* Rx FIFO start address */
uint res5[6]; /* reserved */
uint fec_x_fstart; /* Tx FIFO start address */
uint res6[17]; /* reserved */
uint fec_fun_code; /* fec SDMA function code */
uint res7[3]; /* reserved */
uint fec_r_cntrl; /* Rx control register */
uint fec_r_hash; /* Rx hash register */
uint res8[14]; /* reserved */
uint fec_x_cntrl; /* Tx control register */
uint res9[0x1e]; /* reserved */
} fec_t;
/* The FEC and LCD color map share the same address space....
* I guess we will never see an 823T :-).
*/
union fec_lcd {
fec_t fl_un_fec;
u_char fl_un_cmap[0x200];
};
typedef struct comm_proc {
/* General control and status registers.
*/
ushort cp_cpcr;
u_char res1[2];
ushort cp_rccr;
u_char res2;
u_char cp_rmds;
u_char res3[4];
ushort cp_cpmcr1;
ushort cp_cpmcr2;
ushort cp_cpmcr3;
ushort cp_cpmcr4;
u_char res4[2];
ushort cp_rter;
u_char res5[2];
ushort cp_rtmr;
u_char res6[0x14];
/* Baud rate generators.
*/
uint cp_brgc1;
uint cp_brgc2;
uint cp_brgc3;
uint cp_brgc4;
/* Serial Communication Channels.
*/
scc_t cp_scc[4];
/* Serial Management Channels.
*/
smc_t cp_smc[2];
/* Serial Peripheral Interface.
*/
ushort cp_spmode;
u_char res7[4];
u_char cp_spie;
u_char res8[3];
u_char cp_spim;
u_char res9[2];
u_char cp_spcom;
u_char res10[2];
/* Parallel Interface Port.
*/
u_char res11[2];
ushort cp_pipc;
u_char res12[2];
ushort cp_ptpr;
uint cp_pbdir;
uint cp_pbpar;
u_char res13[2];
ushort cp_pbodr;
uint cp_pbdat;
/* Port E - MPC87x/88x only.
*/
uint cp_pedir;
uint cp_pepar;
uint cp_peso;
uint cp_peodr;
uint cp_pedat;
/* Communications Processor Timing Register -
Contains RMII Timing for the FECs on MPC87x/88x only.
*/
uint cp_cptr;
/* Serial Interface and Time Slot Assignment.
*/
uint cp_simode;
u_char cp_sigmr;
u_char res15;
u_char cp_sistr;
u_char cp_sicmr;
u_char res16[4];
uint cp_sicr;
uint cp_sirp;
u_char res17[0xc];
/* 256 bytes of MPC823 video controller RAM array.
*/
u_char cp_vcram[0x100];
u_char cp_siram[0x200];
/* The fast ethernet controller is not really part of the CPM,
* but it resides in the address space.
* The LCD color map is also here.
*/
union fec_lcd fl_un;
#define cp_fec fl_un.fl_un_fec
#define lcd_cmap fl_un.fl_un_cmap
char res18[0xE00];
/* The MPC885 family has a second FEC here */
fec_t cp_fec2;
#define cp_fec1 cp_fec /* consistency macro */
/* Dual Ported RAM follows.
* There are many different formats for this memory area
* depending upon the devices used and options chosen.
* Some processors don't have all of it populated.
*/
u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
u_char cp_dparam[0x400]; /* Parameter RAM */
} cpm8xx_t;
/* Internal memory map.
*/
typedef struct immap {
sysconf8xx_t im_siu_conf; /* SIU Configuration */
pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
memctl8xx_t im_memctl; /* Memory Controller */
sit8xx_t im_sit; /* System integration timers */
car8xx_t im_clkrst; /* Clocks and reset */
sitk8xx_t im_sitk; /* Sys int timer keys */
cark8xx_t im_clkrstk; /* Clocks and reset keys */
vid823_t im_vid; /* Video (823 only) */
lcd823_t im_lcd; /* LCD (823 only) */
i2c8xx_t im_i2c; /* I2C control/status */
sdma8xx_t im_sdma; /* SDMA control/status */
cpic8xx_t im_cpic; /* CPM Interrupt Controller */
iop8xx_t im_ioport; /* IO Port control/status */
cpmtimer8xx_t im_cpmtimer; /* CPM timers */
cpm8xx_t im_cpm; /* Communication processor */
} immap_t;
#endif /* __IMMAP_8XX__ */

95
arch/powerpc/include/asm/atomic.h Normal file
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/*
* PowerPC atomic operations
*/
#ifndef _ASM_PPC_ATOMIC_H_
#define _ASM_PPC_ATOMIC_H_
#include <linux/config.h>
#ifdef CONFIG_SMP
typedef struct { volatile int counter; } atomic_t;
#else
typedef struct { int counter; } atomic_t;
#endif
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) ((v)->counter)
#define atomic_set(v,i) (((v)->counter) = (i))
extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
extern void atomic_set_mask(unsigned long mask, unsigned long *addr);
extern __inline__ int atomic_add_return(int a, atomic_t *v)
{
int t;
__asm__ __volatile__("\n\
1: lwarx %0,0,%3\n\
add %0,%2,%0\n\
stwcx. %0,0,%3\n\
bne- 1b"
: "=&r" (t), "=m" (*v)
: "r" (a), "r" (v), "m" (*v)
: "cc");
return t;
}
extern __inline__ int atomic_sub_return(int a, atomic_t *v)
{
int t;
__asm__ __volatile__("\n\
1: lwarx %0,0,%3\n\
subf %0,%2,%0\n\
stwcx. %0,0,%3\n\
bne- 1b"
: "=&r" (t), "=m" (*v)
: "r" (a), "r" (v), "m" (*v)
: "cc");
return t;
}
extern __inline__ int atomic_inc_return(atomic_t *v)
{
int t;
__asm__ __volatile__("\n\
1: lwarx %0,0,%2\n\
addic %0,%0,1\n\
stwcx. %0,0,%2\n\
bne- 1b"
: "=&r" (t), "=m" (*v)
: "r" (v), "m" (*v)
: "cc");
return t;
}
extern __inline__ int atomic_dec_return(atomic_t *v)
{
int t;
__asm__ __volatile__("\n\
1: lwarx %0,0,%2\n\
addic %0,%0,-1\n\
stwcx. %0,0,%2\n\
bne 1b"
: "=&r" (t), "=m" (*v)
: "r" (v), "m" (*v)
: "cc");
return t;
}
#define atomic_add(a, v) ((void) atomic_add_return((a), (v)))
#define atomic_sub(a, v) ((void) atomic_sub_return((a), (v)))
#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
#define atomic_inc(v) ((void) atomic_inc_return((v)))
#define atomic_dec(v) ((void) atomic_dec_return((v)))
#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
#endif /* _ASM_PPC_ATOMIC_H_ */

387
arch/powerpc/include/asm/bitops.h Normal file
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/*
* bitops.h: Bit string operations on the ppc
*/
#ifndef _PPC_BITOPS_H
#define _PPC_BITOPS_H
#include <linux/config.h>
#include <asm/byteorder.h>
extern void set_bit(int nr, volatile void *addr);
extern void clear_bit(int nr, volatile void *addr);
extern void change_bit(int nr, volatile void *addr);
extern int test_and_set_bit(int nr, volatile void *addr);
extern int test_and_clear_bit(int nr, volatile void *addr);
extern int test_and_change_bit(int nr, volatile void *addr);
/*
* Arguably these bit operations don't imply any memory barrier or
* SMP ordering, but in fact a lot of drivers expect them to imply
* both, since they do on x86 cpus.
*/
#ifdef CONFIG_SMP
#define SMP_WMB "eieio\n"
#define SMP_MB "\nsync"
#else
#define SMP_WMB
#define SMP_MB
#endif /* CONFIG_SMP */
#define __INLINE_BITOPS 1
#if __INLINE_BITOPS
/*
* These used to be if'd out here because using : "cc" as a constraint
* resulted in errors from egcs. Things may be OK with gcc-2.95.
*/
extern __inline__ void set_bit(int nr, volatile void * addr)
{
unsigned long old;
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
__asm__ __volatile__(SMP_WMB "\
1: lwarx %0,0,%3\n\
or %0,%0,%2\n\
stwcx. %0,0,%3\n\
bne 1b"
SMP_MB
: "=&r" (old), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc" );
}
extern __inline__ void clear_bit(int nr, volatile void *addr)
{
unsigned long old;
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
__asm__ __volatile__(SMP_WMB "\
1: lwarx %0,0,%3\n\
andc %0,%0,%2\n\
stwcx. %0,0,%3\n\
bne 1b"
SMP_MB
: "=&r" (old), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc");
}
extern __inline__ void change_bit(int nr, volatile void *addr)
{
unsigned long old;
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
__asm__ __volatile__(SMP_WMB "\
1: lwarx %0,0,%3\n\
xor %0,%0,%2\n\
stwcx. %0,0,%3\n\
bne 1b"
SMP_MB
: "=&r" (old), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc");
}
extern __inline__ int test_and_set_bit(int nr, volatile void *addr)
{
unsigned int old, t;
unsigned int mask = 1 << (nr & 0x1f);
volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
__asm__ __volatile__(SMP_WMB "\
1: lwarx %0,0,%4\n\
or %1,%0,%3\n\
stwcx. %1,0,%4\n\
bne 1b"
SMP_MB
: "=&r" (old), "=&r" (t), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc");
return (old & mask) != 0;
}
extern __inline__ int test_and_clear_bit(int nr, volatile void *addr)
{
unsigned int old, t;
unsigned int mask = 1 << (nr & 0x1f);
volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
__asm__ __volatile__(SMP_WMB "\
1: lwarx %0,0,%4\n\
andc %1,%0,%3\n\
stwcx. %1,0,%4\n\
bne 1b"
SMP_MB
: "=&r" (old), "=&r" (t), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc");
return (old & mask) != 0;
}
extern __inline__ int test_and_change_bit(int nr, volatile void *addr)
{
unsigned int old, t;
unsigned int mask = 1 << (nr & 0x1f);
volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
__asm__ __volatile__(SMP_WMB "\
1: lwarx %0,0,%4\n\
xor %1,%0,%3\n\
stwcx. %1,0,%4\n\
bne 1b"
SMP_MB
: "=&r" (old), "=&r" (t), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc");
return (old & mask) != 0;
}
#endif /* __INLINE_BITOPS */
extern __inline__ int test_bit(int nr, __const__ volatile void *addr)
{
__const__ unsigned int *p = (__const__ unsigned int *) addr;
return ((p[nr >> 5] >> (nr & 0x1f)) & 1) != 0;
}
/* Return the bit position of the most significant 1 bit in a word */
/* - the result is undefined when x == 0 */
extern __inline__ int __ilog2(unsigned int x)
{
int lz;
asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
return 31 - lz;
}
extern __inline__ int ffz(unsigned int x)
{
if ((x = ~x) == 0)
return 32;
return __ilog2(x & -x);
}
/*
* fls: find last (most-significant) bit set.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*
* On powerpc, __ilog2(0) returns -1, but this is not safe in general
*/
static __inline__ int fls(unsigned int x)
{
return __ilog2(x) + 1;
}
#define PLATFORM_FLS
/**
* fls64 - find last set bit in a 64-bit word
* @x: the word to search
*
* This is defined in a similar way as the libc and compiler builtin
* ffsll, but returns the position of the most significant set bit.
*
* fls64(value) returns 0 if value is 0 or the position of the last
* set bit if value is nonzero. The last (most significant) bit is
* at position 64.
*/
#if BITS_PER_LONG == 32
static inline int fls64(__u64 x)
{
__u32 h = x >> 32;
if (h)
return fls(h) + 32;
return fls(x);
}
#elif BITS_PER_LONG == 64
static inline int fls64(__u64 x)
{
if (x == 0)
return 0;
return __ilog2(x) + 1;
}
#else
#error BITS_PER_LONG not 32 or 64
#endif
static inline int __ilog2_u64(u64 n)
{
return fls64(n) - 1;
}
static inline int ffs64(u64 x)
{
return __ilog2_u64(x & -x) + 1ull;
}
#ifdef __KERNEL__
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
extern __inline__ int ffs(int x)
{
return __ilog2(x & -x) + 1;
}
#define PLATFORM_FFS
/*
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
*/
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
#endif /* __KERNEL__ */
/*
* This implementation of find_{first,next}_zero_bit was stolen from
* Linus' asm-alpha/bitops.h.
*/
#define find_first_zero_bit(addr, size) \
find_next_zero_bit((addr), (size), 0)
extern __inline__ unsigned long find_next_zero_bit(void * addr,
unsigned long size, unsigned long offset)
{
unsigned int * p = ((unsigned int *) addr) + (offset >> 5);
unsigned int result = offset & ~31UL;
unsigned int tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *p++;
tmp |= ~0UL >> (32-offset);
if (size < 32)
goto found_first;
if (tmp != ~0U)
goto found_middle;
size -= 32;
result += 32;
}
while (size >= 32) {
if ((tmp = *p++) != ~0U)
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp |= ~0UL << size;
found_middle:
return result + ffz(tmp);
}
#define _EXT2_HAVE_ASM_BITOPS_
#ifdef __KERNEL__
/*
* test_and_{set,clear}_bit guarantee atomicity without
* disabling interrupts.
*/
#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 0x18, addr)
#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 0x18, addr)
#else
extern __inline__ int ext2_set_bit(int nr, void * addr)
{
int mask;
unsigned char *ADDR = (unsigned char *) addr;
int oldbit;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
oldbit = (*ADDR & mask) ? 1 : 0;
*ADDR |= mask;
return oldbit;
}
extern __inline__ int ext2_clear_bit(int nr, void * addr)
{
int mask;
unsigned char *ADDR = (unsigned char *) addr;
int oldbit;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
oldbit = (*ADDR & mask) ? 1 : 0;
*ADDR = *ADDR & ~mask;
return oldbit;
}
#endif /* __KERNEL__ */
extern __inline__ int ext2_test_bit(int nr, __const__ void * addr)
{
__const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
return (ADDR[nr >> 3] >> (nr & 7)) & 1;
}
/*
* This implementation of ext2_find_{first,next}_zero_bit was stolen from
* Linus' asm-alpha/bitops.h and modified for a big-endian machine.
*/
#define ext2_find_first_zero_bit(addr, size) \
ext2_find_next_zero_bit((addr), (size), 0)
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
unsigned long size, unsigned long offset)
{
unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
unsigned int result = offset & ~31UL;
unsigned int tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = cpu_to_le32p(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
goto found_first;
if (tmp != ~0U)
goto found_middle;
size -= 32;
result += 32;
}
while (size >= 32) {
if ((tmp = cpu_to_le32p(p++)) != ~0U)
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = cpu_to_le32p(p);
found_first:
tmp |= ~0U << size;
found_middle:
return result + ffz(tmp);
}
/* Bitmap functions for the minix filesystem. */
#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr)
#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr)
#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size)
#endif /* _PPC_BITOPS_H */

84
arch/powerpc/include/asm/byteorder.h Normal file
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#ifndef _PPC_BYTEORDER_H
#define _PPC_BYTEORDER_H
#include <asm/types.h>
#ifdef __GNUC__
extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
{
unsigned val;
__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
return val;
}
extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
{
__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
}
extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
{
unsigned val;
__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
return val;
}
extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
{
__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
}
/* alas, egcs sounds like it has a bug in this code that doesn't use the
inline asm correctly, and can cause file corruption. Until I hear that
it's fixed, I can live without the extra speed. I hope. */
#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
#if 0
# define __arch_swab16(x) ld_le16(&x)
# define __arch_swab32(x) ld_le32(&x)
#else
static __inline__ __attribute__((const)) __u16 ___arch__swab16(__u16 value)
{
__u16 result;
__asm__("rlwimi %0,%1,8,16,23"
: "=r" (result)
: "r" (value), "0" (value >> 8));
return result;
}
static __inline__ __attribute__((const)) __u32 ___arch__swab32(__u32 value)
{
__u32 result;
__asm__("rlwimi %0,%1,24,16,23\n\t"
"rlwimi %0,%1,8,8,15\n\t"
"rlwimi %0,%1,24,0,7"
: "=r" (result)
: "r" (value), "0" (value >> 24));
return result;
}
#define __arch__swab32(x) ___arch__swab32(x)
#define __arch__swab16(x) ___arch__swab16(x)
#endif /* 0 */
#endif
/* The same, but returns converted value from the location pointer by addr. */
#define __arch__swab16p(addr) ld_le16(addr)
#define __arch__swab32p(addr) ld_le32(addr)
/* The same, but do the conversion in situ, ie. put the value back to addr. */
#define __arch__swab16s(addr) st_le16(addr,*addr)
#define __arch__swab32s(addr) st_le32(addr,*addr)
#endif /* __GNUC__ */
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
#define __BYTEORDER_HAS_U64__
#endif
#include <linux/byteorder/big_endian.h>
#endif /* _PPC_BYTEORDER_H */

101
arch/powerpc/include/asm/cache.h Normal file
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/*
* include/asm-ppc/cache.h
*/
#ifndef __ARCH_PPC_CACHE_H
#define __ARCH_PPC_CACHE_H
#include <linux/config.h>
#include <asm/processor.h>
/* bytes per L1 cache line */
#if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
#elif defined(CONFIG_E500MC)
#define L1_CACHE_SHIFT 6
#else
#define L1_CACHE_SHIFT 5
#endif
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
* For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
*/
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
#endif
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#ifdef MODULE
#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
#else
#define __cacheline_aligned \
__attribute__((__aligned__(L1_CACHE_BYTES), \
__section__(".data.cacheline_aligned")))
#endif
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache(void);
extern void invalidate_dcache(void);
extern void invalidate_icache(void);
#ifdef CONFIG_SYS_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
#endif /* CONFIG_SYS_INIT_RAM_LOCK */
#endif /* __ASSEMBLY__ */
/* prep registers for L2 */
#define CACHECRBA 0x80000823 /* Cache configuration register address */
#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
#define L2CACHE_512KB 0x00 /* 512KB */
#define L2CACHE_256KB 0x01 /* 256KB */
#define L2CACHE_1MB 0x02 /* 1MB */
#define L2CACHE_NONE 0x03 /* NONE */
#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
#ifdef CONFIG_8xx
/* Cache control on the MPC8xx is provided through some additional
* special purpose registers.
*/
#define IC_CST 560 /* Instruction cache control/status */
#define IC_ADR 561 /* Address needed for some commands */
#define IC_DAT 562 /* Read-only data register */
#define DC_CST 568 /* Data cache control/status */
#define DC_ADR 569 /* Address needed for some commands */
#define DC_DAT 570 /* Read-only data register */
/* Commands. Only the first few are available to the instruction cache.
*/
#define IDC_ENABLE 0x02000000 /* Cache enable */
#define IDC_DISABLE 0x04000000 /* Cache disable */
#define IDC_LDLCK 0x06000000 /* Load and lock */
#define IDC_UNLINE 0x08000000 /* Unlock line */
#define IDC_UNALL 0x0a000000 /* Unlock all */
#define IDC_INVALL 0x0c000000 /* Invalidate all */
#define DC_FLINE 0x0e000000 /* Flush data cache line */
#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
#define DC_SLES 0x05000000 /* Set little endian swap mode */
#define DC_CLES 0x07000000 /* Clear little endian swap mode */
/* Status.
*/
#define IDC_ENABLED 0x80000000 /* Cache is enabled */
#define IDC_CERR1 0x00200000 /* Cache error 1 */
#define IDC_CERR2 0x00100000 /* Cache error 2 */
#define IDC_CERR3 0x00080000 /* Cache error 3 */
#define DC_DFWT 0x40000000 /* Data cache is forced write through */
#define DC_LES 0x20000000 /* Caches are little endian mode */
#endif /* CONFIG_8xx */
#endif

79
arch/powerpc/include/asm/config.h Normal file
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/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_LMB
#ifndef CONFIG_MAX_MEM_MAPPED
#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#else
#define CONFIG_MAX_MEM_MAPPED (256 << 20)
#endif
#endif
/* Check if boards need to enable FSL DMA engine for SDRAM init */
#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
#define CONFIG_FSL_DMA
#endif
#endif
#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
#define CONFIG_MAX_CPUS 2
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
#else
#define CONFIG_MAX_CPUS 1
#endif
/*
* Provide a default boot page translation virtual address that lines up with
* Freescale's default e500 reset page.
*/
#if (defined(CONFIG_E500) && defined(CONFIG_MP))
#ifndef CONFIG_BPTR_VIRT_ADDR
#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
#endif
#endif
/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
#if defined(CONFIG_TSEC_ENET) && \
(defined(CONFIG_P1020) || defined(CONFIG_P1011))
#define CONFIG_TSECV2
#endif
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
#define CONFIG_SYS_NUM_TLBCAMS 64
#elif defined(CONFIG_E500)
#define CONFIG_SYS_NUM_TLBCAMS 16
#endif
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS
#endif /* _ASM_CONFIG_H_ */

796
arch/powerpc/include/asm/cpm_8260.h Normal file
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/*
* MPC8260 Communication Processor Module.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
*
* This file contains structures and information for the communication
* processor channels found in the dual port RAM or parameter RAM.
* All CPM control and status is available through the MPC8260 internal
* memory map. See immap.h for details.
*/
#ifndef __CPM_82XX__
#define __CPM_82XX__
#include <asm/immap_8260.h>
/* CPM Command register.
*/
#define CPM_CR_RST ((uint)0x80000000)
#define CPM_CR_PAGE ((uint)0x7c000000)
#define CPM_CR_SBLOCK ((uint)0x03e00000)
#define CPM_CR_FLG ((uint)0x00010000)
#define CPM_CR_MCN ((uint)0x00003fc0)
#define CPM_CR_OPCODE ((uint)0x0000000f)
/* Device sub-block and page codes.
*/
#define CPM_CR_SCC1_SBLOCK (0x04)
#define CPM_CR_SCC2_SBLOCK (0x05)
#define CPM_CR_SCC3_SBLOCK (0x06)
#define CPM_CR_SCC4_SBLOCK (0x07)
#define CPM_CR_SMC1_SBLOCK (0x08)
#define CPM_CR_SMC2_SBLOCK (0x09)
#define CPM_CR_SPI_SBLOCK (0x0a)
#define CPM_CR_I2C_SBLOCK (0x0b)
#define CPM_CR_TIMER_SBLOCK (0x0f)
#define CPM_CR_RAND_SBLOCK (0x0e)
#define CPM_CR_FCC1_SBLOCK (0x10)
#define CPM_CR_FCC2_SBLOCK (0x11)
#define CPM_CR_FCC3_SBLOCK (0x12)
#define CPM_CR_IDMA1_SBLOCK (0x14)
#define CPM_CR_IDMA2_SBLOCK (0x15)
#define CPM_CR_IDMA3_SBLOCK (0x16)
#define CPM_CR_IDMA4_SBLOCK (0x17)
#define CPM_CR_MCC1_SBLOCK (0x1c)
#define CPM_CR_SCC1_PAGE (0x00)
#define CPM_CR_SCC2_PAGE (0x01)
#define CPM_CR_SCC3_PAGE (0x02)
#define CPM_CR_SCC4_PAGE (0x03)
#define CPM_CR_SMC1_PAGE (0x07)
#define CPM_CR_SMC2_PAGE (0x08)
#define CPM_CR_SPI_PAGE (0x09)
#define CPM_CR_I2C_PAGE (0x0a)
#define CPM_CR_TIMER_PAGE (0x0a)
#define CPM_CR_RAND_PAGE (0x0a)
#define CPM_CR_FCC1_PAGE (0x04)
#define CPM_CR_FCC2_PAGE (0x05)
#define CPM_CR_FCC3_PAGE (0x06)
#define CPM_CR_IDMA1_PAGE (0x07)
#define CPM_CR_IDMA2_PAGE (0x08)
#define CPM_CR_IDMA3_PAGE (0x09)
#define CPM_CR_IDMA4_PAGE (0x0a)
#define CPM_CR_MCC1_PAGE (0x07)
#define CPM_CR_MCC2_PAGE (0x08)
/* Some opcodes (there are more...later)
*/
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define mk_cr_cmd(PG, SBC, MCN, OP) \
((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
/* Dual Port RAM addresses. The first 16K is available for almost
* any CPM use, so we put the BDs there. The first 128 bytes are
* used for SMC1 and SMC2 parameter RAM, so we start allocating
* BDs above that. All of this must change when we start
* downloading RAM microcode.
*/
#define CPM_DATAONLY_BASE ((uint)128)
#define CPM_DP_NOSPACE ((uint)0x7fffffff)
#ifndef CONFIG_MPC8272_FAMILY
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
#else /* 8247/48/71/72 */
#define CPM_DATAONLY_SIZE ((uint)(4 * 1024) - CPM_DATAONLY_BASE)
#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
#endif /* !CONFIG_MPC8272_FAMILY */
/* The number of pages of host memory we allocate for CPM. This is
* done early in kernel initialization to get physically contiguous
* pages.
*/
#define NUM_CPM_HOST_PAGES 2
/* Export the base address of the communication processor registers
* and dual port ram.
*/
extern cpm8260_t *cpmp; /* Pointer to comm processor */
uint m8260_cpm_dpalloc(uint size, uint align);
uint m8260_cpm_hostalloc(uint size, uint align);
void m8260_cpm_setbrg(uint brg, uint rate);
void m8260_cpm_fastbrg(uint brg, uint rate, int div16);
void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
/* Buffer descriptors used by many of the CPM protocols.
*/
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* ?? */
/* Function code bits, usually generic to devices.
*/
#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
/* Parameter RAM offsets from the base.
*/
#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
#else
#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
#endif
#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
#else
#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
#endif
#define PROFF_SCC1 ((uint)0x8000)
#define PROFF_SCC2 ((uint)0x8100)
#define PROFF_SCC3 ((uint)0x8200)
#define PROFF_SCC4 ((uint)0x8300)
#define PROFF_FCC1 ((uint)0x8400)
#define PROFF_FCC2 ((uint)0x8500)
#define PROFF_FCC3 ((uint)0x8600)
#define PROFF_MCC1 ((uint)0x8700)
#define PROFF_SMC1_BASE ((uint)0x87fc)
#define PROFF_IDMA1_BASE ((uint)0x87fe)
#define PROFF_MCC2 ((uint)0x8800)
#define PROFF_SMC2_BASE ((uint)0x88fc)
#define PROFF_IDMA2_BASE ((uint)0x88fe)
#define PROFF_SPI_BASE ((uint)0x89fc)
#define PROFF_IDMA3_BASE ((uint)0x89fe)
#define PROFF_TIMERS ((uint)0x8ae0)
#define PROFF_REVNUM ((uint)0x8af0)
#define PROFF_RAND ((uint)0x8af8)
#define PROFF_I2C_BASE ((uint)0x8afc)
#define PROFF_IDMA4_BASE ((uint)0x8afe)
/* The SMCs are relocated to any of the first eight DPRAM pages.
* We will fix these at the first locations of DPRAM, until we
* get some microcode patches :-).
* The parameter ram space for the SMCs is fifty-some bytes, and
* they are required to start on a 64 byte boundary.
*/
#define PROFF_SMC1 (0)
#define PROFF_SMC2 (64)
#define PROFF_SPI ((16*1024) - 128)
/* Define enough so I can at least use the serial port as a UART.
*/
typedef struct smc_uart {
ushort smc_rbase; /* Rx Buffer descriptor base address */
ushort smc_tbase; /* Tx Buffer descriptor base address */
u_char smc_rfcr; /* Rx function code */
u_char smc_tfcr; /* Tx function code */
ushort smc_mrblr; /* Max receive buffer length */
uint smc_rstate; /* Internal */
uint smc_idp; /* Internal */
ushort smc_rbptr; /* Internal */
ushort smc_ibc; /* Internal */
uint smc_rxtmp; /* Internal */
uint smc_tstate; /* Internal */
uint smc_tdp; /* Internal */
ushort smc_tbptr; /* Internal */
ushort smc_tbc; /* Internal */
uint smc_txtmp; /* Internal */
ushort smc_maxidl; /* Maximum idle characters */
ushort smc_tmpidl; /* Temporary idle counter */
ushort smc_brklen; /* Last received break length */
ushort smc_brkec; /* rcv'd break condition counter */
ushort smc_brkcr; /* xmt break count register */
ushort smc_rmask; /* Temporary bit mask */
uint smc_stmp; /* SDMA Temp */
} smc_uart_t;
/* SMC uart mode register (Internal memory map).
*/
#define SMCMR_REN ((ushort)0x0001)
#define SMCMR_TEN ((ushort)0x0002)
#define SMCMR_DM ((ushort)0x000c)
#define SMCMR_SM_GCI ((ushort)0x0000)
#define SMCMR_SM_UART ((ushort)0x0020)
#define SMCMR_SM_TRANS ((ushort)0x0030)
#define SMCMR_SM_MASK ((ushort)0x0030)
#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
#define SMCMR_REVD SMCMR_PM_EVEN
#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
#define SMCMR_BS SMCMR_PEN
#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
/* SMC Event and Mask register.
*/
#define SMCM_TXE ((unsigned char)0x10)
#define SMCM_BSY ((unsigned char)0x04)
#define SMCM_TX ((unsigned char)0x02)
#define SMCM_RX ((unsigned char)0x01)
/* Baud rate generators.
*/
#define CPM_BRG_RST ((uint)0x00020000)
#define CPM_BRG_EN ((uint)0x00010000)
#define CPM_BRG_EXTC_INT ((uint)0x00000000)
#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
#define CPM_BRG_ATB ((uint)0x00002000)
#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
#define CPM_BRG_DIV16 ((uint)0x00000001)
/* SCCs.
*/
#define SCC_GSMRH_IRP ((uint)0x00040000)
#define SCC_GSMRH_GDE ((uint)0x00010000)
#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
#define SCC_GSMRH_REVD ((uint)0x00002000)
#define SCC_GSMRH_TRX ((uint)0x00001000)
#define SCC_GSMRH_TTX ((uint)0x00000800)
#define SCC_GSMRH_CDP ((uint)0x00000400)
#define SCC_GSMRH_CTSP ((uint)0x00000200)
#define SCC_GSMRH_CDS ((uint)0x00000100)
#define SCC_GSMRH_CTSS ((uint)0x00000080)
#define SCC_GSMRH_TFL ((uint)0x00000040)
#define SCC_GSMRH_RFW ((uint)0x00000020)
#define SCC_GSMRH_TXSY ((uint)0x00000010)
#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
#define SCC_GSMRH_RTSM ((uint)0x00000002)
#define SCC_GSMRH_RSYN ((uint)0x00000001)
#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
#define SCC_GSMRL_TCI ((uint)0x10000000)
#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
#define SCC_GSMRL_RINV ((uint)0x02000000)
#define SCC_GSMRL_TINV ((uint)0x01000000)
#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
#define SCC_GSMRL_TEND ((uint)0x00040000)
#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
#define SCC_GSMRL_ENR ((uint)0x00000020)
#define SCC_GSMRL_ENT ((uint)0x00000010)
#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
#define SCC_TODR_TOD ((ushort)0x8000)
/* SCC Event and Mask register.
*/
#define SCCM_TXE ((unsigned char)0x10)
#define SCCM_BSY ((unsigned char)0x04)
#define SCCM_TX ((unsigned char)0x02)
#define SCCM_RX ((unsigned char)0x01)
typedef struct scc_param {
ushort scc_rbase; /* Rx Buffer descriptor base address */
ushort scc_tbase; /* Tx Buffer descriptor base address */
u_char scc_rfcr; /* Rx function code */
u_char scc_tfcr; /* Tx function code */
ushort scc_mrblr; /* Max receive buffer length */
uint scc_rstate; /* Internal */
uint scc_idp; /* Internal */
ushort scc_rbptr; /* Internal */
ushort scc_ibc; /* Internal */
uint scc_rxtmp; /* Internal */
uint scc_tstate; /* Internal */
uint scc_tdp; /* Internal */
ushort scc_tbptr; /* Internal */
ushort scc_tbc; /* Internal */
uint scc_txtmp; /* Internal */
uint scc_rcrc; /* Internal */
uint scc_tcrc; /* Internal */
} sccp_t;
/* CPM Ethernet through SCC1.
*/
typedef struct scc_enet {
sccp_t sen_genscc;
uint sen_cpres; /* Preset CRC */
uint sen_cmask; /* Constant mask for CRC */
uint sen_crcec; /* CRC Error counter */
uint sen_alec; /* alignment error counter */
uint sen_disfc; /* discard frame counter */
ushort sen_pads; /* Tx short frame pad character */
ushort sen_retlim; /* Retry limit threshold */
ushort sen_retcnt; /* Retry limit counter */
ushort sen_maxflr; /* maximum frame length register */
ushort sen_minflr; /* minimum frame length register */
ushort sen_maxd1; /* maximum DMA1 length */
ushort sen_maxd2; /* maximum DMA2 length */
ushort sen_maxd; /* Rx max DMA */
ushort sen_dmacnt; /* Rx DMA counter */
ushort sen_maxb; /* Max BD byte count */
ushort sen_gaddr1; /* Group address filter */
ushort sen_gaddr2;
ushort sen_gaddr3;
ushort sen_gaddr4;
uint sen_tbuf0data0; /* Save area 0 - current frame */
uint sen_tbuf0data1; /* Save area 1 - current frame */
uint sen_tbuf0rba; /* Internal */
uint sen_tbuf0crc; /* Internal */
ushort sen_tbuf0bcnt; /* Internal */
ushort sen_paddrh; /* physical address (MSB) */
ushort sen_paddrm;
ushort sen_paddrl; /* physical address (LSB) */
ushort sen_pper; /* persistence */
ushort sen_rfbdptr; /* Rx first BD pointer */
ushort sen_tfbdptr; /* Tx first BD pointer */
ushort sen_tlbdptr; /* Tx last BD pointer */
uint sen_tbuf1data0; /* Save area 0 - current frame */
uint sen_tbuf1data1; /* Save area 1 - current frame */
uint sen_tbuf1rba; /* Internal */
uint sen_tbuf1crc; /* Internal */
ushort sen_tbuf1bcnt; /* Internal */
ushort sen_txlen; /* Tx Frame length counter */
ushort sen_iaddr1; /* Individual address filter */
ushort sen_iaddr2;
ushort sen_iaddr3;
ushort sen_iaddr4;
ushort sen_boffcnt; /* Backoff counter */
/* NOTE: Some versions of the manual have the following items
* incorrectly documented. Below is the proper order.
*/
ushort sen_taddrh; /* temp address (MSB) */
ushort sen_taddrm;
ushort sen_taddrl; /* temp address (LSB) */
} scc_enet_t;
/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* SCC Mode Register (PSMR) as used by Ethernet.
*/
#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
/* Buffer descriptor control/status used by Ethernet receive.
* Common to SCC and FCC.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
* Common to SCC and FCC.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
#define BD_ENET_TX_UN ((ushort)0x0002)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
/* SCC as UART
*/
typedef struct scc_uart {
sccp_t scc_genscc;
uint scc_res1; /* Reserved */
uint scc_res2; /* Reserved */
ushort scc_maxidl; /* Maximum idle chars */
ushort scc_idlc; /* temp idle counter */
ushort scc_brkcr; /* Break count register */
ushort scc_parec; /* receive parity error counter */
ushort scc_frmec; /* receive framing error counter */
ushort scc_nosec; /* receive noise counter */
ushort scc_brkec; /* receive break condition counter */
ushort scc_brkln; /* last received break length */
ushort scc_uaddr1; /* UART address character 1 */
ushort scc_uaddr2; /* UART address character 2 */
ushort scc_rtemp; /* Temp storage */
ushort scc_toseq; /* Transmit out of sequence char */
ushort scc_char1; /* control character 1 */
ushort scc_char2; /* control character 2 */
ushort scc_char3; /* control character 3 */
ushort scc_char4; /* control character 4 */
ushort scc_char5; /* control character 5 */
ushort scc_char6; /* control character 6 */
ushort scc_char7; /* control character 7 */
ushort scc_char8; /* control character 8 */
ushort scc_rccm; /* receive control character mask */
ushort scc_rccr; /* receive control character register */
ushort scc_rlbc; /* receive last break character */
} scc_uart_t;
/* SCC Event and Mask registers when it is used as a UART.
*/
#define UART_SCCM_GLR ((ushort)0x1000)
#define UART_SCCM_GLT ((ushort)0x0800)
#define UART_SCCM_AB ((ushort)0x0200)
#define UART_SCCM_IDL ((ushort)0x0100)
#define UART_SCCM_GRA ((ushort)0x0080)
#define UART_SCCM_BRKE ((ushort)0x0040)
#define UART_SCCM_BRKS ((ushort)0x0020)
#define UART_SCCM_CCR ((ushort)0x0008)
#define UART_SCCM_BSY ((ushort)0x0004)
#define UART_SCCM_TX ((ushort)0x0002)
#define UART_SCCM_RX ((ushort)0x0001)
/* The SCC PSMR when used as a UART.
*/
#define SCU_PSMR_FLC ((ushort)0x8000)
#define SCU_PSMR_SL ((ushort)0x4000)
#define SCU_PSMR_CL ((ushort)0x3000)
#define SCU_PSMR_UM ((ushort)0x0c00)
#define SCU_PSMR_FRZ ((ushort)0x0200)
#define SCU_PSMR_RZS ((ushort)0x0100)
#define SCU_PSMR_SYN ((ushort)0x0080)
#define SCU_PSMR_DRT ((ushort)0x0040)
#define SCU_PSMR_PEN ((ushort)0x0010)
#define SCU_PSMR_RPM ((ushort)0x000c)
#define SCU_PSMR_REVP ((ushort)0x0008)
#define SCU_PSMR_TPM ((ushort)0x0003)
#define SCU_PSMR_TEVP ((ushort)0x0003)
/* CPM Transparent mode SCC.
*/
typedef struct scc_trans {
sccp_t st_genscc;
uint st_cpres; /* Preset CRC */
uint st_cmask; /* Constant mask for CRC */
} scc_trans_t;
#define BD_SCC_TX_LAST ((ushort)0x0800)
/* SCC as HDLC controller - taken from commproc.h
*/
typedef struct scc_hdlc {
sccp_t sh_genscc;
/*
* HDLC specific parameter RAM
*/
uchar res[4]; /* reserved */
ulong sh_cmask; /* CRC constant */
ulong sh_cpres; /* CRC preset */
ushort sh_disfc; /* discarded frame counter */
ushort sh_crcec; /* CRC error counter */
ushort sh_abtsc; /* abort sequence counter */
ushort sh_nmarc; /* nonmatching address rx cnt */
ushort sh_retrc; /* frame retransmission cnt */
ushort sh_mflr; /* maximum frame length reg */
ushort sh_maxcnt; /* maximum length counter */
ushort sh_rfthr; /* received frames threshold */
ushort sh_rfcnt; /* received frames count */
ushort sh_hmask; /* user defined frm addr mask */
ushort sh_haddr1; /* user defined frm address 1 */
ushort sh_haddr2; /* user defined frm address 2 */
ushort sh_haddr3; /* user defined frm address 3 */
ushort sh_haddr4; /* user defined frm address 4 */
ushort tmp; /* temp */
ushort tmp_mb; /* temp */
} scc_hdlc_t;
/* How about some FCCs.....
*/
#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
#define FCC_GFMR_TCI ((uint)0x20000000)
#define FCC_GFMR_TRX ((uint)0x10000000)
#define FCC_GFMR_TTX ((uint)0x08000000)
#define FCC_GFMR_TTX ((uint)0x08000000)
#define FCC_GFMR_CDP ((uint)0x04000000)
#define FCC_GFMR_CTSP ((uint)0x02000000)
#define FCC_GFMR_CDS ((uint)0x01000000)
#define FCC_GFMR_CTSS ((uint)0x00800000)
#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
#define FCC_GFMR_RTSM ((uint)0x00002000)
#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
#define FCC_GFMR_REVD ((uint)0x00000400)
#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
#define FCC_GFMR_ENR ((uint)0x00000020)
#define FCC_GFMR_ENT ((uint)0x00000010)
#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
/* Generic FCC parameter ram.
*/
typedef struct fcc_param {
ushort fcc_riptr; /* Rx Internal temp pointer */
ushort fcc_tiptr; /* Tx Internal temp pointer */
ushort fcc_res1;
ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
uint fcc_rstate; /* Upper byte is Func code, must be set */
uint fcc_rbase; /* Receive BD base */
ushort fcc_rbdstat; /* RxBD status */
ushort fcc_rbdlen; /* RxBD down counter */
uint fcc_rdptr; /* RxBD internal data pointer */
uint fcc_tstate; /* Upper byte is Func code, must be set */
uint fcc_tbase; /* Transmit BD base */
ushort fcc_tbdstat; /* TxBD status */
ushort fcc_tbdlen; /* TxBD down counter */
uint fcc_tdptr; /* TxBD internal data pointer */
uint fcc_rbptr; /* Rx BD Internal buf pointer */
uint fcc_tbptr; /* Tx BD Internal buf pointer */
uint fcc_rcrc; /* Rx temp CRC */
uint fcc_res2;
uint fcc_tcrc; /* Tx temp CRC */
} fccp_t;
/* Ethernet controller through FCC.
*/
typedef struct fcc_enet {
fccp_t fen_genfcc;
uint fen_statbuf; /* Internal status buffer */
uint fen_camptr; /* CAM address */
uint fen_cmask; /* Constant mask for CRC */
uint fen_cpres; /* Preset CRC */
uint fen_crcec; /* CRC Error counter */
uint fen_alec; /* alignment error counter */
uint fen_disfc; /* discard frame counter */
ushort fen_retlim; /* Retry limit */
ushort fen_retcnt; /* Retry counter */
ushort fen_pper; /* Persistence */
ushort fen_boffcnt; /* backoff counter */
uint fen_gaddrh; /* Group address filter, high 32-bits */
uint fen_gaddrl; /* Group address filter, low 32-bits */
ushort fen_tfcstat; /* out of sequence TxBD */
ushort fen_tfclen;
uint fen_tfcptr;
ushort fen_mflr; /* Maximum frame length (1518) */
ushort fen_paddrh; /* MAC address */
ushort fen_paddrm;
ushort fen_paddrl;
ushort fen_ibdcount; /* Internal BD counter */
ushort fen_idbstart; /* Internal BD start pointer */
ushort fen_ibdend; /* Internal BD end pointer */
ushort fen_txlen; /* Internal Tx frame length counter */
uint fen_ibdbase[8]; /* Internal use */
uint fen_iaddrh; /* Individual address filter */
uint fen_iaddrl;
ushort fen_minflr; /* Minimum frame length (64) */
ushort fen_taddrh; /* Filter transfer MAC address */
ushort fen_taddrm;
ushort fen_taddrl;
ushort fen_padptr; /* Pointer to pad byte buffer */
ushort fen_cftype; /* control frame type */
ushort fen_cfrange; /* control frame range */
ushort fen_maxb; /* maximum BD count */
ushort fen_maxd1; /* Max DMA1 length (1520) */
ushort fen_maxd2; /* Max DMA2 length (1520) */
ushort fen_maxd; /* internal max DMA count */
ushort fen_dmacnt; /* internal DMA counter */
uint fen_octc; /* Total octect counter */
uint fen_colc; /* Total collision counter */
uint fen_broc; /* Total broadcast packet counter */
uint fen_mulc; /* Total multicast packet count */
uint fen_uspc; /* Total packets < 64 bytes */
uint fen_frgc; /* Total packets < 64 bytes with errors */
uint fen_ospc; /* Total packets > 1518 */
uint fen_jbrc; /* Total packets > 1518 with errors */
uint fen_p64c; /* Total packets == 64 bytes */
uint fen_p65c; /* Total packets 64 < bytes <= 127 */
uint fen_p128c; /* Total packets 127 < bytes <= 255 */
uint fen_p256c; /* Total packets 256 < bytes <= 511 */
uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
uint fen_cambuf; /* Internal CAM buffer poiner */
ushort fen_rfthr; /* Received frames threshold */
ushort fen_rfcnt; /* Received frames count */
} fcc_enet_t;
/* FCC Event/Mask register as used by Ethernet.
*/
#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* FCC Mode Register (FPSMR) as used by Ethernet.
*/
#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
/* IIC parameter RAM.
*/
typedef struct iic {
ushort iic_rbase; /* Rx Buffer descriptor base address */
ushort iic_tbase; /* Tx Buffer descriptor base address */
u_char iic_rfcr; /* Rx function code */
u_char iic_tfcr; /* Tx function code */
ushort iic_mrblr; /* Max receive buffer length */
uint iic_rstate; /* Internal */
uint iic_rdp; /* Internal */
ushort iic_rbptr; /* Internal */
ushort iic_rbc; /* Internal */
uint iic_rxtmp; /* Internal */
uint iic_tstate; /* Internal */
uint iic_tdp; /* Internal */
ushort iic_tbptr; /* Internal */
ushort iic_tbc; /* Internal */
uint iic_txtmp; /* Internal */
} iic_t;
/* SPI parameter RAM.
*/
typedef struct spi {
ushort spi_rbase; /* Rx Buffer descriptor base address */
ushort spi_tbase; /* Tx Buffer descriptor base address */
u_char spi_rfcr; /* Rx function code */
u_char spi_tfcr; /* Tx function code */
ushort spi_mrblr; /* Max receive buffer length */
uint spi_rstate; /* Internal */
uint spi_rdp; /* Internal */
ushort spi_rbptr; /* Internal */
ushort spi_rbc; /* Internal */
uint spi_rxtmp; /* Internal */
uint spi_tstate; /* Internal */
uint spi_tdp; /* Internal */
ushort spi_tbptr; /* Internal */
ushort spi_tbc; /* Internal */
uint spi_txtmp; /* Internal */
uint spi_res; /* Tx temp. */
uint spi_res1[4]; /* SDMA temp. */
} spi_t;
/* SPI Mode register.
*/
#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
#define SPMODE_EN ((ushort)0x0100) /* Enable */
#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
#define SPMODE_PM(x) ((x) &0xF)
/* SPI Event/Mask register.
*/
#define SPI_EMASK 0x37 /* Event Mask */
#define SPI_MME 0x20 /* Multi-Master Error */
#define SPI_TXE 0x10 /* Transmit Error */
#define SPI_BSY 0x04 /* Busy */
#define SPI_TXB 0x02 /* Tx Buffer Empty */
#define SPI_RXB 0x01 /* RX Buffer full/closed */
#define SPI_STR 0x80 /* SPCOM: Start transmit */
#define SPI_EB ((u_char)0x10) /* big endian byte order */
#define BD_IIC_START ((ushort)0x0400)
#endif /* __CPM_82XX__ */

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arch/powerpc/include/asm/cpm_85xx.h Normal file
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/*
* MPC85xx Communication Processor Module
* Copyright (c) 2003,Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
* MPC8260 Communication Processor Module.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
*
* This file contains structures and information for the communication
* processor channels found in the dual port RAM or parameter RAM.
* All CPM control and status is available through the MPC8260 internal
* memory map. See immap.h for details.
*/
#ifndef __CPM_85XX__
#define __CPM_85XX__
#include <asm/immap_85xx.h>
/* CPM Command register.
*/
#define CPM_CR_RST ((uint)0x80000000)
#define CPM_CR_PAGE ((uint)0x7c000000)
#define CPM_CR_SBLOCK ((uint)0x03e00000)
#define CPM_CR_FLG ((uint)0x00010000)
#define CPM_CR_MCN ((uint)0x00003fc0)
#define CPM_CR_OPCODE ((uint)0x0000000f)
/* Device sub-block and page codes.
*/
#define CPM_CR_SCC1_SBLOCK (0x04)
#define CPM_CR_SCC2_SBLOCK (0x05)
#define CPM_CR_SCC3_SBLOCK (0x06)
#define CPM_CR_SCC4_SBLOCK (0x07)
#define CPM_CR_SMC1_SBLOCK (0x08)
#define CPM_CR_SMC2_SBLOCK (0x09)
#define CPM_CR_SPI_SBLOCK (0x0a)
#define CPM_CR_I2C_SBLOCK (0x0b)
#define CPM_CR_TIMER_SBLOCK (0x0f)
#define CPM_CR_RAND_SBLOCK (0x0e)
#define CPM_CR_FCC1_SBLOCK (0x10)
#define CPM_CR_FCC2_SBLOCK (0x11)
#define CPM_CR_FCC3_SBLOCK (0x12)
#define CPM_CR_MCC1_SBLOCK (0x1c)
#define CPM_CR_SCC1_PAGE (0x00)
#define CPM_CR_SCC2_PAGE (0x01)
#define CPM_CR_SCC3_PAGE (0x02)
#define CPM_CR_SCC4_PAGE (0x03)
#define CPM_CR_SPI_PAGE (0x09)
#define CPM_CR_I2C_PAGE (0x0a)
#define CPM_CR_TIMER_PAGE (0x0a)
#define CPM_CR_RAND_PAGE (0x0a)
#define CPM_CR_FCC1_PAGE (0x04)
#define CPM_CR_FCC2_PAGE (0x05)
#define CPM_CR_FCC3_PAGE (0x06)
#define CPM_CR_MCC1_PAGE (0x07)
#define CPM_CR_MCC2_PAGE (0x08)
/* Some opcodes (there are more...later)
*/
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define mk_cr_cmd(PG, SBC, MCN, OP) \
((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
/* Dual Port RAM addresses. The first 16K is available for almost
* any CPM use, so we put the BDs there. The first 128 bytes are
* used for SMC1 and SMC2 parameter RAM, so we start allocating
* BDs above that. All of this must change when we start
* downloading RAM microcode.
*/
#define CPM_DATAONLY_BASE ((uint)128)
#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
#else /* MPC8540, MPC8560 */
#define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000)
#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
#endif
/* The number of pages of host memory we allocate for CPM. This is
* done early in kernel initialization to get physically contiguous
* pages.
*/
#define NUM_CPM_HOST_PAGES 2
/* Export the base address of the communication processor registers
* and dual port ram.
*/
/*extern cpm8560_t *cpmp; Pointer to comm processor */
uint m8560_cpm_dpalloc(uint size, uint align);
uint m8560_cpm_hostalloc(uint size, uint align);
void m8560_cpm_setbrg(uint brg, uint rate);
void m8560_cpm_fastbrg(uint brg, uint rate, int div16);
void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
/* Buffer descriptors used by many of the CPM protocols.
*/
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* ?? */
/* Function code bits, usually generic to devices.
*/
#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
/* Parameter RAM offsets from the base.
*/
#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
#define PROFF_SCC1 ((uint)0x8000)
#define PROFF_SCC2 ((uint)0x8100)
#define PROFF_SCC3 ((uint)0x8200)
#define PROFF_SCC4 ((uint)0x8300)
#define PROFF_FCC1 ((uint)0x8400)
#define PROFF_FCC2 ((uint)0x8500)
#define PROFF_FCC3 ((uint)0x8600)
#define PROFF_MCC1 ((uint)0x8700)
#define PROFF_MCC2 ((uint)0x8800)
#define PROFF_SPI_BASE ((uint)0x89fc)
#define PROFF_TIMERS ((uint)0x8ae0)
#define PROFF_REVNUM ((uint)0x8af0)
#define PROFF_RAND ((uint)0x8af8)
#define PROFF_I2C_BASE ((uint)0x8afc)
/* Baud rate generators.
*/
#define CPM_BRG_RST ((uint)0x00020000)
#define CPM_BRG_EN ((uint)0x00010000)
#define CPM_BRG_EXTC_INT ((uint)0x00000000)
#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
#define CPM_BRG_ATB ((uint)0x00002000)
#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
#define CPM_BRG_DIV16 ((uint)0x00000001)
/* SCCs.
*/
#define SCC_GSMRH_IRP ((uint)0x00040000)
#define SCC_GSMRH_GDE ((uint)0x00010000)
#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
#define SCC_GSMRH_REVD ((uint)0x00002000)
#define SCC_GSMRH_TRX ((uint)0x00001000)
#define SCC_GSMRH_TTX ((uint)0x00000800)
#define SCC_GSMRH_CDP ((uint)0x00000400)
#define SCC_GSMRH_CTSP ((uint)0x00000200)
#define SCC_GSMRH_CDS ((uint)0x00000100)
#define SCC_GSMRH_CTSS ((uint)0x00000080)
#define SCC_GSMRH_TFL ((uint)0x00000040)
#define SCC_GSMRH_RFW ((uint)0x00000020)
#define SCC_GSMRH_TXSY ((uint)0x00000010)
#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
#define SCC_GSMRH_RTSM ((uint)0x00000002)
#define SCC_GSMRH_RSYN ((uint)0x00000001)
#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
#define SCC_GSMRL_TCI ((uint)0x10000000)
#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
#define SCC_GSMRL_RINV ((uint)0x02000000)
#define SCC_GSMRL_TINV ((uint)0x01000000)
#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
#define SCC_GSMRL_TEND ((uint)0x00040000)
#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
#define SCC_GSMRL_ENR ((uint)0x00000020)
#define SCC_GSMRL_ENT ((uint)0x00000010)
#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
#define SCC_TODR_TOD ((ushort)0x8000)
/* SCC Event and Mask register.
*/
#define SCCM_TXE ((unsigned char)0x10)
#define SCCM_BSY ((unsigned char)0x04)
#define SCCM_TX ((unsigned char)0x02)
#define SCCM_RX ((unsigned char)0x01)
typedef struct scc_param {
ushort scc_rbase; /* Rx Buffer descriptor base address */
ushort scc_tbase; /* Tx Buffer descriptor base address */
u_char scc_rfcr; /* Rx function code */
u_char scc_tfcr; /* Tx function code */
ushort scc_mrblr; /* Max receive buffer length */
uint scc_rstate; /* Internal */
uint scc_idp; /* Internal */
ushort scc_rbptr; /* Internal */
ushort scc_ibc; /* Internal */
uint scc_rxtmp; /* Internal */
uint scc_tstate; /* Internal */
uint scc_tdp; /* Internal */
ushort scc_tbptr; /* Internal */
ushort scc_tbc; /* Internal */
uint scc_txtmp; /* Internal */
uint scc_rcrc; /* Internal */
uint scc_tcrc; /* Internal */
} sccp_t;
/* CPM Ethernet through SCC1.
*/
typedef struct scc_enet {
sccp_t sen_genscc;
uint sen_cpres; /* Preset CRC */
uint sen_cmask; /* Constant mask for CRC */
uint sen_crcec; /* CRC Error counter */
uint sen_alec; /* alignment error counter */
uint sen_disfc; /* discard frame counter */
ushort sen_pads; /* Tx short frame pad character */
ushort sen_retlim; /* Retry limit threshold */
ushort sen_retcnt; /* Retry limit counter */
ushort sen_maxflr; /* maximum frame length register */
ushort sen_minflr; /* minimum frame length register */
ushort sen_maxd1; /* maximum DMA1 length */
ushort sen_maxd2; /* maximum DMA2 length */
ushort sen_maxd; /* Rx max DMA */
ushort sen_dmacnt; /* Rx DMA counter */
ushort sen_maxb; /* Max BD byte count */
ushort sen_gaddr1; /* Group address filter */
ushort sen_gaddr2;
ushort sen_gaddr3;
ushort sen_gaddr4;
uint sen_tbuf0data0; /* Save area 0 - current frame */
uint sen_tbuf0data1; /* Save area 1 - current frame */
uint sen_tbuf0rba; /* Internal */
uint sen_tbuf0crc; /* Internal */
ushort sen_tbuf0bcnt; /* Internal */
ushort sen_paddrh; /* physical address (MSB) */
ushort sen_paddrm;
ushort sen_paddrl; /* physical address (LSB) */
ushort sen_pper; /* persistence */
ushort sen_rfbdptr; /* Rx first BD pointer */
ushort sen_tfbdptr; /* Tx first BD pointer */
ushort sen_tlbdptr; /* Tx last BD pointer */
uint sen_tbuf1data0; /* Save area 0 - current frame */
uint sen_tbuf1data1; /* Save area 1 - current frame */
uint sen_tbuf1rba; /* Internal */
uint sen_tbuf1crc; /* Internal */
ushort sen_tbuf1bcnt; /* Internal */
ushort sen_txlen; /* Tx Frame length counter */
ushort sen_iaddr1; /* Individual address filter */
ushort sen_iaddr2;
ushort sen_iaddr3;
ushort sen_iaddr4;
ushort sen_boffcnt; /* Backoff counter */
/* NOTE: Some versions of the manual have the following items
* incorrectly documented. Below is the proper order.
*/
ushort sen_taddrh; /* temp address (MSB) */
ushort sen_taddrm;
ushort sen_taddrl; /* temp address (LSB) */
} scc_enet_t;
/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* SCC Mode Register (PSMR) as used by Ethernet.
*/
#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
/* Buffer descriptor control/status used by Ethernet receive.
* Common to SCC and FCC.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
* Common to SCC and FCC.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
#define BD_ENET_TX_UN ((ushort)0x0002)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
/* SCC as UART
*/
typedef struct scc_uart {
sccp_t scc_genscc;
uint scc_res1; /* Reserved */
uint scc_res2; /* Reserved */
ushort scc_maxidl; /* Maximum idle chars */
ushort scc_idlc; /* temp idle counter */
ushort scc_brkcr; /* Break count register */
ushort scc_parec; /* receive parity error counter */
ushort scc_frmec; /* receive framing error counter */
ushort scc_nosec; /* receive noise counter */
ushort scc_brkec; /* receive break condition counter */
ushort scc_brkln; /* last received break length */
ushort scc_uaddr1; /* UART address character 1 */
ushort scc_uaddr2; /* UART address character 2 */
ushort scc_rtemp; /* Temp storage */
ushort scc_toseq; /* Transmit out of sequence char */
ushort scc_char1; /* control character 1 */
ushort scc_char2; /* control character 2 */
ushort scc_char3; /* control character 3 */
ushort scc_char4; /* control character 4 */
ushort scc_char5; /* control character 5 */
ushort scc_char6; /* control character 6 */
ushort scc_char7; /* control character 7 */
ushort scc_char8; /* control character 8 */
ushort scc_rccm; /* receive control character mask */
ushort scc_rccr; /* receive control character register */
ushort scc_rlbc; /* receive last break character */
} scc_uart_t;
/* SCC Event and Mask registers when it is used as a UART.
*/
#define UART_SCCM_GLR ((ushort)0x1000)
#define UART_SCCM_GLT ((ushort)0x0800)
#define UART_SCCM_AB ((ushort)0x0200)
#define UART_SCCM_IDL ((ushort)0x0100)
#define UART_SCCM_GRA ((ushort)0x0080)
#define UART_SCCM_BRKE ((ushort)0x0040)
#define UART_SCCM_BRKS ((ushort)0x0020)
#define UART_SCCM_CCR ((ushort)0x0008)
#define UART_SCCM_BSY ((ushort)0x0004)
#define UART_SCCM_TX ((ushort)0x0002)
#define UART_SCCM_RX ((ushort)0x0001)
/* The SCC PSMR when used as a UART.
*/
#define SCU_PSMR_FLC ((ushort)0x8000)
#define SCU_PSMR_SL ((ushort)0x4000)
#define SCU_PSMR_CL ((ushort)0x3000)
#define SCU_PSMR_UM ((ushort)0x0c00)
#define SCU_PSMR_FRZ ((ushort)0x0200)
#define SCU_PSMR_RZS ((ushort)0x0100)
#define SCU_PSMR_SYN ((ushort)0x0080)
#define SCU_PSMR_DRT ((ushort)0x0040)
#define SCU_PSMR_PEN ((ushort)0x0010)
#define SCU_PSMR_RPM ((ushort)0x000c)
#define SCU_PSMR_REVP ((ushort)0x0008)
#define SCU_PSMR_TPM ((ushort)0x0003)
#define SCU_PSMR_TEVP ((ushort)0x0003)
/* CPM Transparent mode SCC.
*/
typedef struct scc_trans {
sccp_t st_genscc;
uint st_cpres; /* Preset CRC */
uint st_cmask; /* Constant mask for CRC */
} scc_trans_t;
#define BD_SCC_TX_LAST ((ushort)0x0800)
/* How about some FCCs.....
*/
#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
#define FCC_GFMR_TCI ((uint)0x20000000)
#define FCC_GFMR_TRX ((uint)0x10000000)
#define FCC_GFMR_TTX ((uint)0x08000000)
#define FCC_GFMR_TTX ((uint)0x08000000)
#define FCC_GFMR_CDP ((uint)0x04000000)
#define FCC_GFMR_CTSP ((uint)0x02000000)
#define FCC_GFMR_CDS ((uint)0x01000000)
#define FCC_GFMR_CTSS ((uint)0x00800000)
#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
#define FCC_GFMR_RTSM ((uint)0x00002000)
#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
#define FCC_GFMR_REVD ((uint)0x00000400)
#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
#define FCC_GFMR_ENR ((uint)0x00000020)
#define FCC_GFMR_ENT ((uint)0x00000010)
#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
/* Generic FCC parameter ram.
*/
typedef struct fcc_param {
ushort fcc_riptr; /* Rx Internal temp pointer */
ushort fcc_tiptr; /* Tx Internal temp pointer */
ushort fcc_res1;
ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
uint fcc_rstate; /* Upper byte is Func code, must be set */
uint fcc_rbase; /* Receive BD base */
ushort fcc_rbdstat; /* RxBD status */
ushort fcc_rbdlen; /* RxBD down counter */
uint fcc_rdptr; /* RxBD internal data pointer */
uint fcc_tstate; /* Upper byte is Func code, must be set */
uint fcc_tbase; /* Transmit BD base */
ushort fcc_tbdstat; /* TxBD status */
ushort fcc_tbdlen; /* TxBD down counter */
uint fcc_tdptr; /* TxBD internal data pointer */
uint fcc_rbptr; /* Rx BD Internal buf pointer */
uint fcc_tbptr; /* Tx BD Internal buf pointer */
uint fcc_rcrc; /* Rx temp CRC */
uint fcc_res2;
uint fcc_tcrc; /* Tx temp CRC */
} fccp_t;
/* Ethernet controller through FCC.
*/
typedef struct fcc_enet {
fccp_t fen_genfcc;
uint fen_statbuf; /* Internal status buffer */
uint fen_camptr; /* CAM address */
uint fen_cmask; /* Constant mask for CRC */
uint fen_cpres; /* Preset CRC */
uint fen_crcec; /* CRC Error counter */
uint fen_alec; /* alignment error counter */
uint fen_disfc; /* discard frame counter */
ushort fen_retlim; /* Retry limit */
ushort fen_retcnt; /* Retry counter */
ushort fen_pper; /* Persistence */
ushort fen_boffcnt; /* backoff counter */
uint fen_gaddrh; /* Group address filter, high 32-bits */
uint fen_gaddrl; /* Group address filter, low 32-bits */
ushort fen_tfcstat; /* out of sequence TxBD */
ushort fen_tfclen;
uint fen_tfcptr;
ushort fen_mflr; /* Maximum frame length (1518) */
ushort fen_paddrh; /* MAC address */
ushort fen_paddrm;
ushort fen_paddrl;
ushort fen_ibdcount; /* Internal BD counter */
ushort fen_ibdstart; /* Internal BD start pointer */
ushort fen_ibdend; /* Internal BD end pointer */
ushort fen_txlen; /* Internal Tx frame length counter */
uint fen_ibdbase[8]; /* Internal use */
uint fen_iaddrh; /* Individual address filter */
uint fen_iaddrl;
ushort fen_minflr; /* Minimum frame length (64) */
ushort fen_taddrh; /* Filter transfer MAC address */
ushort fen_taddrm;
ushort fen_taddrl;
ushort fen_padptr; /* Pointer to pad byte buffer */
ushort fen_cftype; /* control frame type */
ushort fen_cfrange; /* control frame range */
ushort fen_maxb; /* maximum BD count */
ushort fen_maxd1; /* Max DMA1 length (1520) */
ushort fen_maxd2; /* Max DMA2 length (1520) */
ushort fen_maxd; /* internal max DMA count */
ushort fen_dmacnt; /* internal DMA counter */
uint fen_octc; /* Total octect counter */
uint fen_colc; /* Total collision counter */
uint fen_broc; /* Total broadcast packet counter */
uint fen_mulc; /* Total multicast packet count */
uint fen_uspc; /* Total packets < 64 bytes */
uint fen_frgc; /* Total packets < 64 bytes with errors */
uint fen_ospc; /* Total packets > 1518 */
uint fen_jbrc; /* Total packets > 1518 with errors */
uint fen_p64c; /* Total packets == 64 bytes */
uint fen_p65c; /* Total packets 64 < bytes <= 127 */
uint fen_p128c; /* Total packets 127 < bytes <= 255 */
uint fen_p256c; /* Total packets 256 < bytes <= 511 */
uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
uint fen_cambuf; /* Internal CAM buffer poiner */
ushort fen_rfthr; /* Received frames threshold */
ushort fen_rfcnt; /* Received frames count */
} fcc_enet_t;
/* FCC Event/Mask register as used by Ethernet.
*/
#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* FCC Mode Register (FPSMR) as used by Ethernet.
*/
#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
/* IIC parameter RAM.
*/
typedef struct iic {
ushort iic_rbase; /* Rx Buffer descriptor base address */
ushort iic_tbase; /* Tx Buffer descriptor base address */
u_char iic_rfcr; /* Rx function code */
u_char iic_tfcr; /* Tx function code */
ushort iic_mrblr; /* Max receive buffer length */
uint iic_rstate; /* Internal */
uint iic_rdp; /* Internal */
ushort iic_rbptr; /* Internal */
ushort iic_rbc; /* Internal */
uint iic_rxtmp; /* Internal */
uint iic_tstate; /* Internal */
uint iic_tdp; /* Internal */
ushort iic_tbptr; /* Internal */
ushort iic_tbc; /* Internal */
uint iic_txtmp; /* Internal */
} iic_t;
/* SPI parameter RAM.
*/
typedef struct spi {
ushort spi_rbase; /* Rx Buffer descriptor base address */
ushort spi_tbase; /* Tx Buffer descriptor base address */
u_char spi_rfcr; /* Rx function code */
u_char spi_tfcr; /* Tx function code */
ushort spi_mrblr; /* Max receive buffer length */
uint spi_rstate; /* Internal */
uint spi_rdp; /* Internal */
ushort spi_rbptr; /* Internal */
ushort spi_rbc; /* Internal */
uint spi_rxtmp; /* Internal */
uint spi_tstate; /* Internal */
uint spi_tdp; /* Internal */
ushort spi_tbptr; /* Internal */
ushort spi_tbc; /* Internal */
uint spi_txtmp; /* Internal */
uint spi_res; /* Tx temp. */
uint spi_res1[4]; /* SDMA temp. */
} spi_t;
/* SPI Mode register.
*/
#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
#define SPMODE_EN ((ushort)0x0100) /* Enable */
#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
#define SPMODE_PM(x) ((x) &0xF)
#define SPI_EB ((u_char)0x10) /* big endian byte order */
#define BD_IIC_START ((ushort)0x0400)
/*-----------------------------------------------------------------------
* CMXFCR - CMX FCC Clock Route Register 15-12
*/
#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
/*-----------------------------------------------------------------------
* CMXSCR - CMX SCC Clock Route Register 15-14
*/
#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
#endif /* __CPM_85XX__ */

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/*
* Copyright 2004 Freescale Semiconductor, Inc.
* Liberty Eran (liberty@freescale.com)
*/
#ifndef __E300_H__
#define __E300_H__
#define PVR_E300C1 0x80830000
#define PVR_E300C2 0x80840000
#define PVR_E300C3 0x80850000
#define PVR_E300C4 0x80860000
/*
* Hardware Implementation-Dependent Register 0 (HID0)
*/
/* #define HID0 1008 already defined in processor.h */
#define HID0_MASK_MACHINE_CHECK 0x00000000
#define HID0_ENABLE_MACHINE_CHECK 0x80000000
#define HID0_DISABLE_CACHE_PARITY 0x00000000
#define HID0_ENABLE_CACHE_PARITY 0x40000000
#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
#define HID0_ENABLE_ADDRESS_PARITY 0x20000000
#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */
#define HID0_ENABLE_DATE_PARITY 0x10000000
#define HID0_CORE_CLK_OUT 0x00000000
#define HID0_CORE_CLK_OUT_DIV_2 0x08000000
#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */
#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000
#define HID0_DISABLE_DOSE_MODE 0x00000000
#define HID0_ENABLE_DOSE_MODE 0x00800000
#define HID0_DISABLE_NAP_MODE 0x00000000
#define HID0_ENABLE_NAP_MODE 0x00400000
#define HID0_DISABLE_SLEEP_MODE 0x00000000
#define HID0_ENABLE_SLEEP_MODE 0x00200000
#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000
#define HID0_SOFT_RESET 0x00010000
#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000
#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000
#define HID0_DISABLE_DATA_CACHE 0x00000000
#define HID0_ENABLE_DATA_CACHE 0x00004000
#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000
#define HID0_LOCK_DATA_CACHE 0x00001000
#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800
#define HID0_INVALIDATE_DATA_CACHE 0x00000400
#define HID0_DISABLE_M_BIT 0x00000000
#define HID0_ENABLE_M_BIT 0x00000080
#define HID0_FBIOB 0x00000010
#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000
#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008
#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000
#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
/*
* Hardware Implementation-Dependent Register 2 (HID2)
*/
#define HID2 1011
#define HID2_LET 0x08000000
#define HID2_HBE 0x00040000
#define HID2_IWLCK_000 0x00000000 /* no ways locked */
#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
#endif /* __E300_H__ */

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#include <asm-generic/errno.h>

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/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#ifndef DDR2_DIMM_PARAMS_H
#define DDR2_DIMM_PARAMS_H
/* Parameters for a DDR2 dimm computed from the SPD */
typedef struct dimm_params_s {
/* DIMM organization parameters */
char mpart[19]; /* guaranteed null terminated */
unsigned int n_ranks;
unsigned long long rank_density;
unsigned long long capacity;
unsigned int data_width;
unsigned int primary_sdram_width;
unsigned int ec_sdram_width;
unsigned int registered_dimm;
/* SDRAM device parameters */
unsigned int n_row_addr;
unsigned int n_col_addr;
unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
unsigned int n_banks_per_sdram_device;
unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
unsigned int row_density;
/* used in computing base address of DIMMs */
unsigned long long base_address;
/* mirrored DIMMs */
unsigned int mirrored_dimm; /* only for ddr3 */
/* DIMM timing parameters */
unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */
unsigned int tFAW_ps; /* four active window delay, only for ddr3 */
/*
* SDRAM clock periods
* The range for these are 1000-10000 so a short should be sufficient
*/
unsigned int tCKmin_X_ps;
unsigned int tCKmin_X_minus_1_ps;
unsigned int tCKmin_X_minus_2_ps;
unsigned int tCKmax_ps;
/* SPD-defined CAS latencies */
unsigned int caslat_X;
unsigned int caslat_X_minus_1;
unsigned int caslat_X_minus_2;
unsigned int caslat_lowest_derated; /* Derated CAS latency */
/* basic timing parameters */
unsigned int tRCD_ps;
unsigned int tRP_ps;
unsigned int tRAS_ps;
unsigned int tWR_ps; /* maximum = 63750 ps */
unsigned int tWTR_ps; /* maximum = 63750 ps */
unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns
= 511750 ps */
unsigned int tRRD_ps; /* maximum = 63750 ps */
unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
unsigned int refresh_rate_ps;
/* DDR3 doesn't need these as below */
unsigned int tIS_ps; /* byte 32, spd->ca_setup */
unsigned int tIH_ps; /* byte 33, spd->ca_hold */
unsigned int tDS_ps; /* byte 34, spd->data_setup */
unsigned int tDH_ps; /* byte 35, spd->data_hold */
unsigned int tRTP_ps; /* byte 38, spd->trtp */
unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
unsigned int tQHS_ps; /* byte 45, spd->tqhs */
} dimm_params_t;
extern unsigned int ddr_compute_dimm_parameters(
const generic_spd_eeprom_t *spd,
dimm_params_t *pdimm,
unsigned int dimm_number);
#endif

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#ifndef FSL_DDR_MEMCTL_H
#define FSL_DDR_MEMCTL_H
/*
* Pick a basic DDR Technology.
*/
#include <ddr_spd.h>
#define SDRAM_TYPE_DDR1 2
#define SDRAM_TYPE_DDR2 3
#define SDRAM_TYPE_LPDDR1 6
#define SDRAM_TYPE_DDR3 7
#define DDR_BL4 4 /* burst length 4 */
#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
#define DDR_BL8 8 /* burst length 8 */
#if defined(CONFIG_FSL_DDR1)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
#endif
#elif defined(CONFIG_FSL_DDR2)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
#endif
#elif defined(CONFIG_FSL_DDR3)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
#endif
#endif /* #if defined(CONFIG_FSL_DDR1) */
/* define bank(chip select) interleaving mode */
#define FSL_DDR_CS0_CS1 0x40
#define FSL_DDR_CS2_CS3 0x20
#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
/* define memory controller interleaving mode */
#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
#define FSL_DDR_PAGE_INTERLEAVING 0x1
#define FSL_DDR_BANK_INTERLEAVING 0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
#define SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG_SREN 0x40000000
#define SDRAM_CFG_ECC_EN 0x20000000
#define SDRAM_CFG_RD_EN 0x10000000
#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_32_BE 0x00080000
#define SDRAM_CFG_8_BE 0x00040000
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_BI 0x00000001
#if defined(CONFIG_P4080)
#define RD_TO_PRE_MASK 0xf
#define RD_TO_PRE_SHIFT 13
#define WR_DATA_DELAY_MASK 0xf
#define WR_DATA_DELAY_SHIFT 9
#else
#define RD_TO_PRE_MASK 0x7
#define RD_TO_PRE_SHIFT 13
#define WR_DATA_DELAY_MASK 0x7
#define WR_DATA_DELAY_SHIFT 10
#endif
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {
unsigned int bnds;
unsigned int config;
unsigned int config_2;
} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
unsigned int timing_cfg_3;
unsigned int timing_cfg_0;
unsigned int timing_cfg_1;
unsigned int timing_cfg_2;
unsigned int ddr_sdram_cfg;
unsigned int ddr_sdram_cfg_2;
unsigned int ddr_sdram_mode;
unsigned int ddr_sdram_mode_2;
unsigned int ddr_sdram_md_cntl;
unsigned int ddr_sdram_interval;
unsigned int ddr_data_init;
unsigned int ddr_sdram_clk_cntl;
unsigned int ddr_init_addr;
unsigned int ddr_init_ext_addr;
unsigned int timing_cfg_4;
unsigned int timing_cfg_5;
unsigned int ddr_zq_cntl;
unsigned int ddr_wrlvl_cntl;
unsigned int ddr_sr_cntr;
unsigned int ddr_sdram_rcw_1;
unsigned int ddr_sdram_rcw_2;
} fsl_ddr_cfg_regs_t;
typedef struct memctl_options_partial_s {
unsigned int all_DIMMs_ECC_capable;
unsigned int all_DIMMs_tCKmax_ps;
unsigned int all_DIMMs_burst_lengths_bitmask;
unsigned int all_DIMMs_registered;
unsigned int all_DIMMs_unbuffered;
/* unsigned int lowest_common_SPD_caslat; */
unsigned int all_DIMMs_minimum_tRCD_ps;
} memctl_options_partial_t;
/*
* Generalized parameters for memory controller configuration,
* might be a little specific to the FSL memory controller
*/
typedef struct memctl_options_s {
/*
* Memory organization parameters
*
* if DIMM is present in the system
* where DIMMs are with respect to chip select
* where chip selects are with respect to memory boundaries
*/
unsigned int registered_dimm_en; /* use registered DIMM support */
/* Options local to a Chip Select */
struct cs_local_opts_s {
unsigned int auto_precharge;
unsigned int odt_rd_cfg;
unsigned int odt_wr_cfg;
} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
/* Special configurations for chip select */
unsigned int memctl_interleaving;
unsigned int memctl_interleaving_mode;
unsigned int ba_intlv_ctl;
/* Operational mode parameters */
unsigned int ECC_mode; /* Use ECC? */
/* Initialize ECC using memory controller? */
unsigned int ECC_init_using_memctl;
unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
/* SREN - self-refresh during sleep */
unsigned int self_refresh_in_sleep;
unsigned int dynamic_power; /* DYN_PWR */
/* memory data width to use (16-bit, 32-bit, 64-bit) */
unsigned int data_bus_width;
unsigned int burst_length; /* BL4, OTF and BL8 */
/* On-The-Fly Burst Chop enable */
unsigned int OTF_burst_chop_en;
/* mirrior DIMMs for DDR3 */
unsigned int mirrored_dimm;
/* Global Timing Parameters */
unsigned int cas_latency_override;
unsigned int cas_latency_override_value;
unsigned int use_derated_caslat;
unsigned int additive_latency_override;
unsigned int additive_latency_override_value;
unsigned int clk_adjust; /* */
unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
unsigned int half_strength_driver_enable;
unsigned int twoT_en;
unsigned int threeT_en;
unsigned int bstopre;
unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
/* Rtt impedance */
unsigned int rtt_override; /* rtt_override enable */
unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
/* Automatic self refresh */
unsigned int auto_self_refresh_en;
unsigned int sr_it;
/* ZQ calibration */
unsigned int zq_en;
/* Write leveling */
unsigned int wrlvl_en;
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
#endif

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/*
* Freescale DMA Controller
*
* Copyright 2006 Freescale Semiconductor, Inc.
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_FSL_DMA_H_
#define _ASM_FSL_DMA_H_
#include <asm/types.h>
#ifdef CONFIG_MPC83xx
typedef struct fsl_dma {
uint mr; /* DMA mode register */
#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
#define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
#define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
#define FSL_DMA_MR_IRQS 0x00080000 /* Interrupt steer */
#define FSL_DMA_MR_DMSEN 0x00100000 /* Direct mode snooping en */
#define FSL_DMA_MR_BWC_MASK 0x00e00000 /* Bandwidth/pause ctl */
#define FSL_DMA_MR_DRCNT 0x0f000000 /* DMA request count */
uint sr; /* DMA status register */
#define FSL_DMA_SR_EOCDI 0x00000001 /* End-of-chain/direct interrupt */
#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
uint cdar; /* DMA current descriptor address register */
char res0[4];
uint sar; /* DMA source address register */
char res1[4];
uint dar; /* DMA destination address register */
char res2[4];
uint bcr; /* DMA byte count register */
uint ndar; /* DMA next descriptor address register */
uint gsr; /* DMA general status register (DMA3 ONLY!) */
char res3[84];
} fsl_dma_t;
#else
typedef struct fsl_dma {
uint mr; /* DMA mode register */
#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
#define FSL_DMA_MR_CA 0x00000008 /* Channel abort */
#define FSL_DMA_MR_CDSM 0x00000010
#define FSL_DMA_MR_XFE 0x00000020 /* Extended features en */
#define FSL_DMA_MR_EIE 0x00000040 /* Error interrupt en */
#define FSL_DMA_MR_EOLSIE 0x00000080 /* End-of-lists interrupt en */
#define FSL_DMA_MR_EOLNIE 0x00000100 /* End-of-links interrupt en */
#define FSL_DMA_MR_EOSIE 0x00000200 /* End-of-seg interrupt en */
#define FSL_DMA_MR_SRW 0x00000400 /* Single register write */
#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
#define FSL_DMA_MR_EMP_EN 0x00200000 /* Ext master pause en */
#define FSL_DMA_MR_BWC_MASK 0x0f000000 /* Bandwidth/pause ctl */
#define FSL_DMA_MR_BWC_DIS 0x0f000000 /* Bandwidth/pause ctl disable */
uint sr; /* DMA status register */
#define FSL_DMA_SR_EOLSI 0x00000001 /* End-of-list interrupt */
#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
#define FSL_DMA_SR_EOLNI 0x00000008 /* End-of-links interrupt */
#define FSL_DMA_SR_PE 0x00000010 /* Programming error */
#define FSL_DMA_SR_CH 0x00000020 /* Channel halted */
#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
char res0[4];
uint clndar; /* DMA current link descriptor address register */
uint satr; /* DMA source attributes register */
#define FSL_DMA_SATR_ESAD_MASK 0x000001ff /* Extended source addr */
#define FSL_DMA_SATR_SREAD_NO_SNOOP 0x00040000 /* Read, don't snoop */
#define FSL_DMA_SATR_SREAD_SNOOP 0x00050000 /* Read, snoop */
#define FSL_DMA_SATR_SREAD_UNLOCK 0x00070000 /* Read, unlock l2 */
#define FSL_DMA_SATR_STRAN_MASK 0x00f00000 /* Source interface */
#define FSL_DMA_SATR_SSME 0x01000000 /* Source stride en */
#define FSL_DMA_SATR_SPCIORDER 0x02000000 /* PCI transaction order */
#define FSL_DMA_SATR_STFLOWLVL_MASK 0x0c000000 /* RIO flow level */
#define FSL_DMA_SATR_SBPATRMU 0x20000000 /* Bypass ATMU */
uint sar; /* DMA source address register */
uint datr; /* DMA destination attributes register */
#define FSL_DMA_DATR_EDAD_MASK 0x000001ff /* Extended dest addr */
#define FSL_DMA_DATR_DWRITE_NO_SNOOP 0x00040000 /* Write, don't snoop */
#define FSL_DMA_DATR_DWRITE_SNOOP 0x00050000 /* Write, snoop */
#define FSL_DMA_DATR_DWRITE_ALLOC 0x00060000 /* Write, alloc l2 */
#define FSL_DMA_DATR_DWRITE_LOCK 0x00070000 /* Write, lock l2 */
#define FSL_DMA_DATR_DTRAN_MASK 0x00f00000 /* Dest interface */
#define FSL_DMA_DATR_DSME 0x01000000 /* Dest stride en */
#define FSL_DMA_DATR_DPCIORDER 0x02000000 /* PCI transaction order */
#define FSL_DMA_DATR_DTFLOWLVL_MASK 0x0c000000 /* RIO flow level */
#define FSL_DMA_DATR_DBPATRMU 0x20000000 /* Bypass ATMU */
uint dar; /* DMA destination address register */
uint bcr; /* DMA byte count register */
char res1[4];
uint nlndar; /* DMA next link descriptor address register */
char res2[8];
uint clabdar; /* DMA current List - alternate base descriptor address Register */
char res3[4];
uint nlsdar; /* DMA next list descriptor address register */
uint ssr; /* DMA source stride register */
uint dsr; /* DMA destination stride register */
char res4[56];
} fsl_dma_t;
#endif /* !CONFIG_MPC83xx */
#ifdef CONFIG_FSL_DMA
void dma_init(void);
int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
void dma_meminit(uint val, uint size);
#endif
#endif
#endif /* _ASM_DMA_H_ */

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arch/powerpc/include/asm/fsl_i2c.h Normal file
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/*
* Freescale I2C Controller
*
* Copyright 2006 Freescale Semiconductor, Inc.
*
* Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
* Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
* and Jeff Brown.
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_FSL_I2C_H_
#define _ASM_FSL_I2C_H_
#include <asm/types.h>
typedef struct fsl_i2c {
u8 adr; /* I2C slave address */
u8 res0[3];
#define I2C_ADR 0xFE
#define I2C_ADR_SHIFT 1
#define I2C_ADR_RES ~(I2C_ADR)
u8 fdr; /* I2C frequency divider register */
u8 res1[3];
#define IC2_FDR 0x3F
#define IC2_FDR_SHIFT 0
#define IC2_FDR_RES ~(IC2_FDR)
u8 cr; /* I2C control redister */
u8 res2[3];
#define I2C_CR_MEN 0x80
#define I2C_CR_MIEN 0x40
#define I2C_CR_MSTA 0x20
#define I2C_CR_MTX 0x10
#define I2C_CR_TXAK 0x08
#define I2C_CR_RSTA 0x04
#define I2C_CR_BCST 0x01
u8 sr; /* I2C status register */
u8 res3[3];
#define I2C_SR_MCF 0x80
#define I2C_SR_MAAS 0x40
#define I2C_SR_MBB 0x20
#define I2C_SR_MAL 0x10
#define I2C_SR_BCSTM 0x08
#define I2C_SR_SRW 0x04
#define I2C_SR_MIF 0x02
#define I2C_SR_RXAK 0x01
u8 dr; /* I2C data register */
u8 res4[3];
#define I2C_DR 0xFF
#define I2C_DR_SHIFT 0
#define I2C_DR_RES ~(I2C_DR)
u8 dfsrr; /* I2C digital filter sampling rate register */
u8 res5[3];
#define I2C_DFSRR 0x3F
#define I2C_DFSRR_SHIFT 0
#define I2C_DFSRR_RES ~(I2C_DR)
/* Fill out the reserved block */
u8 res6[0xE8];
} fsl_i2c_t;
#endif /* _ASM_I2C_H_ */

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#ifndef _FSL_LAW_H_
#define _FSL_LAW_H_
#include <asm/io.h>
#define LAW_EN 0x80000000
#define SET_LAW_ENTRY(idx, a, sz, trgt) \
{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
#define SET_LAW(a, sz, trgt) \
{ .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
enum law_size {
LAW_SIZE_4K = 0xb,
LAW_SIZE_8K,
LAW_SIZE_16K,
LAW_SIZE_32K,
LAW_SIZE_64K,
LAW_SIZE_128K,
LAW_SIZE_256K,
LAW_SIZE_512K,
LAW_SIZE_1M,
LAW_SIZE_2M,
LAW_SIZE_4M,
LAW_SIZE_8M,
LAW_SIZE_16M,
LAW_SIZE_32M,
LAW_SIZE_64M,
LAW_SIZE_128M,
LAW_SIZE_256M,
LAW_SIZE_512M,
LAW_SIZE_1G,
LAW_SIZE_2G,
LAW_SIZE_4G,
LAW_SIZE_8G,
LAW_SIZE_16G,
LAW_SIZE_32G,
};
#define law_size_bits(sz) (__ilog2_u64(sz) - 1)
#ifdef CONFIG_FSL_CORENET
enum law_trgt_if {
LAW_TRGT_IF_PCIE_1 = 0x00,
LAW_TRGT_IF_PCIE_2 = 0x01,
LAW_TRGT_IF_PCIE_3 = 0x02,
LAW_TRGT_IF_RIO_1 = 0x08,
LAW_TRGT_IF_RIO_2 = 0x09,
LAW_TRGT_IF_DDR_1 = 0x10,
LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
LAW_TRGT_IF_DDR_INTRLV = 0x14,
LAW_TRGT_IF_BMAN = 0x18,
LAW_TRGT_IF_DCSR = 0x1d,
LAW_TRGT_IF_LBC = 0x1f,
LAW_TRGT_IF_QMAN = 0x3c,
};
#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
#else
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
#ifndef CONFIG_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
LAW_TRGT_IF_LBC = 0x04,
LAW_TRGT_IF_CCSR = 0x08,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
LAW_TRGT_IF_RIO_2 = 0x0d,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
};
#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
#ifdef CONFIG_MPC8641
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
#endif
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
#endif /* CONFIG_FSL_CORENET */
struct law_entry {
int index;
phys_addr_t addr;
enum law_size size;
enum law_trgt_if trgt_id;
};
extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
extern struct law_entry find_law(phys_addr_t addr);
extern void disable_law(u8 idx);
extern void init_laws(void);
extern void print_laws(void);
/* define in board code */
extern struct law_entry law_table[];
extern int num_law_entries;
#endif

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/*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __ASM_PPC_FSL_LBC_H
#define __ASM_PPC_FSL_LBC_H
#include <config.h>
/* BR - Base Registers
*/
#define BR0 0x5000 /* Register offset to immr */
#define BR1 0x5008
#define BR2 0x5010
#define BR3 0x5018
#define BR4 0x5020
#define BR5 0x5028
#define BR6 0x5030
#define BR7 0x5038
#define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15
#define BR_XBA 0x00006000
#define BR_XBA_SHIFT 13
#define BR_PS 0x00001800
#define BR_PS_SHIFT 11
#define BR_PS_8 0x00000800 /* Port Size 8 bit */
#define BR_PS_16 0x00001000 /* Port Size 16 bit */
#define BR_PS_32 0x00001800 /* Port Size 32 bit */
#define BR_DECC 0x00000600
#define BR_DECC_SHIFT 9
#define BR_DECC_OFF 0x00000000
#define BR_DECC_CHK 0x00000200
#define BR_DECC_CHK_GEN 0x00000400
#define BR_WP 0x00000100
#define BR_WP_SHIFT 8
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
#define BR_MS_FCM 0x00000020 /* FCM */
#ifdef CONFIG_MPC83xx
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#elif defined(CONFIG_MPC85xx)
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
#endif
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
#if !defined(CONFIG_MPC834x)
#define BR_ATOM 0x0000000C
#define BR_ATOM_SHIFT 2
#endif
#define BR_V 0x00000001
#define BR_V_SHIFT 0
#define UPMA 0
#define UPMB 1
#define UPMC 2
#if defined(CONFIG_MPC834x)
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
#else
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
#endif
/* Convert an address into the right format for the BR registers */
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
((x & 0x300000000ULL) >> 19)))
#else
#define BR_PHYS_ADDR(x) (x & 0xffff8000)
#endif
/* OR - Option Registers
*/
#define OR0 0x5004 /* Register offset to immr */
#define OR1 0x500C
#define OR2 0x5014
#define OR3 0x501C
#define OR4 0x5024
#define OR5 0x502C
#define OR6 0x5034
#define OR7 0x503C
#define OR_GPCM_AM 0xFFFF8000
#define OR_GPCM_AM_SHIFT 15
#define OR_GPCM_XAM 0x00006000
#define OR_GPCM_XAM_SHIFT 13
#define OR_GPCM_BCTLD 0x00001000
#define OR_GPCM_BCTLD_SHIFT 12
#define OR_GPCM_CSNT 0x00000800
#define OR_GPCM_CSNT_SHIFT 11
#define OR_GPCM_ACS 0x00000600
#define OR_GPCM_ACS_SHIFT 9
#define OR_GPCM_ACS_DIV2 0x00000600
#define OR_GPCM_ACS_DIV4 0x00000400
#define OR_GPCM_XACS 0x00000100
#define OR_GPCM_XACS_SHIFT 8
#define OR_GPCM_SCY 0x000000F0
#define OR_GPCM_SCY_SHIFT 4
#define OR_GPCM_SCY_1 0x00000010
#define OR_GPCM_SCY_2 0x00000020
#define OR_GPCM_SCY_3 0x00000030
#define OR_GPCM_SCY_4 0x00000040
#define OR_GPCM_SCY_5 0x00000050
#define OR_GPCM_SCY_6 0x00000060
#define OR_GPCM_SCY_7 0x00000070
#define OR_GPCM_SCY_8 0x00000080
#define OR_GPCM_SCY_9 0x00000090
#define OR_GPCM_SCY_10 0x000000a0
#define OR_GPCM_SCY_11 0x000000b0
#define OR_GPCM_SCY_12 0x000000c0
#define OR_GPCM_SCY_13 0x000000d0
#define OR_GPCM_SCY_14 0x000000e0
#define OR_GPCM_SCY_15 0x000000f0
#define OR_GPCM_SETA 0x00000008
#define OR_GPCM_SETA_SHIFT 3
#define OR_GPCM_TRLX 0x00000004
#define OR_GPCM_TRLX_SHIFT 2
#define OR_GPCM_EHTR 0x00000002
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
/* helpers to convert values into an OR address mask (GPCM mode) */
#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
#define OR_FCM_AM 0xFFFF8000
#define OR_FCM_AM_SHIFT 15
#define OR_FCM_XAM 0x00006000
#define OR_FCM_XAM_SHIFT 13
#define OR_FCM_BCTLD 0x00001000
#define OR_FCM_BCTLD_SHIFT 12
#define OR_FCM_PGS 0x00000400
#define OR_FCM_PGS_SHIFT 10
#define OR_FCM_CSCT 0x00000200
#define OR_FCM_CSCT_SHIFT 9
#define OR_FCM_CST 0x00000100
#define OR_FCM_CST_SHIFT 8
#define OR_FCM_CHT 0x00000080
#define OR_FCM_CHT_SHIFT 7
#define OR_FCM_SCY 0x00000070
#define OR_FCM_SCY_SHIFT 4
#define OR_FCM_SCY_1 0x00000010
#define OR_FCM_SCY_2 0x00000020
#define OR_FCM_SCY_3 0x00000030
#define OR_FCM_SCY_4 0x00000040
#define OR_FCM_SCY_5 0x00000050
#define OR_FCM_SCY_6 0x00000060
#define OR_FCM_SCY_7 0x00000070
#define OR_FCM_RST 0x00000008
#define OR_FCM_RST_SHIFT 3
#define OR_FCM_TRLX 0x00000004
#define OR_FCM_TRLX_SHIFT 2
#define OR_FCM_EHTR 0x00000002
#define OR_FCM_EHTR_SHIFT 1
#define OR_UPM_AM 0xFFFF8000
#define OR_UPM_AM_SHIFT 15
#define OR_UPM_XAM 0x00006000
#define OR_UPM_XAM_SHIFT 13
#define OR_UPM_BCTLD 0x00001000
#define OR_UPM_BCTLD_SHIFT 12
#define OR_UPM_BI 0x00000100
#define OR_UPM_BI_SHIFT 8
#define OR_UPM_TRLX 0x00000004
#define OR_UPM_TRLX_SHIFT 2
#define OR_UPM_EHTR 0x00000002
#define OR_UPM_EHTR_SHIFT 1
#define OR_UPM_EAD 0x00000001
#define OR_UPM_EAD_SHIFT 0
#define OR_SDRAM_AM 0xFFFF8000
#define OR_SDRAM_AM_SHIFT 15
#define OR_SDRAM_XAM 0x00006000
#define OR_SDRAM_XAM_SHIFT 13
#define OR_SDRAM_COLS 0x00001C00
#define OR_SDRAM_COLS_SHIFT 10
#define OR_SDRAM_ROWS 0x000001C0
#define OR_SDRAM_ROWS_SHIFT 6
#define OR_SDRAM_PMSEL 0x00000020
#define OR_SDRAM_PMSEL_SHIFT 5
#define OR_SDRAM_EAD 0x00000001
#define OR_SDRAM_EAD_SHIFT 0
#define OR_AM_32KB 0xFFFF8000
#define OR_AM_64KB 0xFFFF0000
#define OR_AM_128KB 0xFFFE0000
#define OR_AM_256KB 0xFFFC0000
#define OR_AM_512KB 0xFFF80000
#define OR_AM_1MB 0xFFF00000
#define OR_AM_2MB 0xFFE00000
#define OR_AM_4MB 0xFFC00000
#define OR_AM_8MB 0xFF800000
#define OR_AM_16MB 0xFF000000
#define OR_AM_32MB 0xFE000000
#define OR_AM_64MB 0xFC000000
#define OR_AM_128MB 0xF8000000
#define OR_AM_256MB 0xF0000000
#define OR_AM_512MB 0xE0000000
#define OR_AM_1GB 0xC0000000
#define OR_AM_2GB 0x80000000
#define OR_AM_4GB 0x00000000
/* MxMR - UPM Machine A/B/C Mode Registers
*/
#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
#define MxMR_WLFx_1X 0x00000400 /* executed 1 time */
#define MxMR_WLFx_2X 0x00000800 /* executed 2 times */
#define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */
#define MxMR_WLFx_4X 0x00001000 /* executed 4 times */
#define MxMR_WLFx_5X 0x00001400 /* executed 5 times */
#define MxMR_WLFx_6X 0x00001800 /* executed 6 times */
#define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */
#define MxMR_WLFx_8X 0x00002000 /* executed 8 times */
#define MxMR_WLFx_9X 0x00002400 /* executed 9 times */
#define MxMR_WLFx_10X 0x00002800 /* executed 10 times */
#define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */
#define MxMR_WLFx_12X 0x00003000 /* executed 12 times */
#define MxMR_WLFx_13X 0x00003400 /* executed 13 times */
#define MxMR_WLFx_14X 0x00003800 /* executed 14 times */
#define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */
#define MxMR_WLFx_16X 0x00000000 /* executed 16 times */
#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
#define MxMR_OP_WARR 0x10000000 /* Write to Array */
#define MxMR_OP_RARR 0x20000000 /* Read from Array */
#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
#define MxMR_RFEN 0x40000000 /* Refresh Enable */
#define MxMR_BSEL 0x80000000 /* Bus Select */
#define LBLAWAR_EN 0x80000000
#define LBLAWAR_4KB 0x0000000B
#define LBLAWAR_8KB 0x0000000C
#define LBLAWAR_16KB 0x0000000D
#define LBLAWAR_32KB 0x0000000E
#define LBLAWAR_64KB 0x0000000F
#define LBLAWAR_128KB 0x00000010
#define LBLAWAR_256KB 0x00000011
#define LBLAWAR_512KB 0x00000012
#define LBLAWAR_1MB 0x00000013
#define LBLAWAR_2MB 0x00000014
#define LBLAWAR_4MB 0x00000015
#define LBLAWAR_8MB 0x00000016
#define LBLAWAR_16MB 0x00000017
#define LBLAWAR_32MB 0x00000018
#define LBLAWAR_64MB 0x00000019
#define LBLAWAR_128MB 0x0000001A
#define LBLAWAR_256MB 0x0000001B
#define LBLAWAR_512MB 0x0000001C
#define LBLAWAR_1GB 0x0000001D
#define LBLAWAR_2GB 0x0000001E
/* LBCR - Local Bus Configuration Register
*/
#define LBCR_LDIS 0x80000000
#define LBCR_LDIS_SHIFT 31
#define LBCR_BCTLC 0x00C00000
#define LBCR_BCTLC_SHIFT 22
#define LBCR_LPBSE 0x00020000
#define LBCR_LPBSE_SHIFT 17
#define LBCR_EPAR 0x00010000
#define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8
/* LCRR - Clock Ratio Register
*/
#define LCRR_DBYP 0x80000000
#define LCRR_DBYP_SHIFT 31
#define LCRR_BUFCMDC 0x30000000
#define LCRR_BUFCMDC_SHIFT 28
#define LCRR_BUFCMDC_1 0x10000000
#define LCRR_BUFCMDC_2 0x20000000
#define LCRR_BUFCMDC_3 0x30000000
#define LCRR_BUFCMDC_4 0x00000000
#define LCRR_ECL 0x03000000
#define LCRR_ECL_SHIFT 24
#define LCRR_ECL_4 0x00000000
#define LCRR_ECL_5 0x01000000
#define LCRR_ECL_6 0x02000000
#define LCRR_ECL_7 0x03000000
#define LCRR_EADC 0x00030000
#define LCRR_EADC_SHIFT 16
#define LCRR_EADC_1 0x00010000
#define LCRR_EADC_2 0x00020000
#define LCRR_EADC_3 0x00030000
#define LCRR_EADC_4 0x00000000
/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
* should always be zero on older parts that have a four bit CLKDIV.
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
defined(CONFIG_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
#elif defined(CONFIG_FSL_CORENET)
#define LCRR_CLKDIV_8 0x00000002
#define LCRR_CLKDIV_16 0x00000004
#define LCRR_CLKDIV_32 0x00000008
#else
#define LCRR_CLKDIV_4 0x00000002
#define LCRR_CLKDIV_8 0x00000004
#define LCRR_CLKDIV_16 0x00000008
#endif
/* LTEDR - Transfer Error Check Disable Register
*/
#define LTEDR_BMD 0x80000000 /* Bus monitor disable */
#define LTEDR_PARD 0x20000000 /* Parity error checking disabled */
#define LTEDR_WPD 0x04000000 /* Write protect error checking diable */
#define LTEDR_WARA 0x00800000 /* Write-after-read-atomic error checking diable */
#define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
#define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
/* FMR - Flash Mode Register
*/
#define FMR_CWTO 0x0000F000
#define FMR_CWTO_SHIFT 12
#define FMR_BOOT 0x00000800
#define FMR_ECCM 0x00000100
#define FMR_AL 0x00000030
#define FMR_AL_SHIFT 4
#define FMR_OP 0x00000003
#define FMR_OP_SHIFT 0
/* FIR - Flash Instruction Register
*/
#define FIR_OP0 0xF0000000
#define FIR_OP0_SHIFT 28
#define FIR_OP1 0x0F000000
#define FIR_OP1_SHIFT 24
#define FIR_OP2 0x00F00000
#define FIR_OP2_SHIFT 20
#define FIR_OP3 0x000F0000
#define FIR_OP3_SHIFT 16
#define FIR_OP4 0x0000F000
#define FIR_OP4_SHIFT 12
#define FIR_OP5 0x00000F00
#define FIR_OP5_SHIFT 8
#define FIR_OP6 0x000000F0
#define FIR_OP6_SHIFT 4
#define FIR_OP7 0x0000000F
#define FIR_OP7_SHIFT 0
#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
#define FIR_OP_CA 0x1 /* Issue current column address */
#define FIR_OP_PA 0x2 /* Issue current block+page address */
#define FIR_OP_UA 0x3 /* Issue user defined address */
#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
/* FCR - Flash Command Register
*/
#define FCR_CMD0 0xFF000000
#define FCR_CMD0_SHIFT 24
#define FCR_CMD1 0x00FF0000
#define FCR_CMD1_SHIFT 16
#define FCR_CMD2 0x0000FF00
#define FCR_CMD2_SHIFT 8
#define FCR_CMD3 0x000000FF
#define FCR_CMD3_SHIFT 0
/* FBAR - Flash Block Address Register
*/
#define FBAR_BLK 0x00FFFFFF
/* FPAR - Flash Page Address Register
*/
#define FPAR_SP_PI 0x00007C00
#define FPAR_SP_PI_SHIFT 10
#define FPAR_SP_MS 0x00000200
#define FPAR_SP_CI 0x000001FF
#define FPAR_SP_CI_SHIFT 0
#define FPAR_LP_PI 0x0003F000
#define FPAR_LP_PI_SHIFT 12
#define FPAR_LP_MS 0x00000800
#define FPAR_LP_CI 0x000007FF
#define FPAR_LP_CI_SHIFT 0
/* LSDMR - SDRAM Machine Mode Register
*/
#define LSDMR_RFEN (1 << (31 - 1))
#define LSDMR_BSMA1516 (3 << (31 - 10))
#define LSDMR_BSMA1617 (4 << (31 - 10))
#define LSDMR_RFCR5 (3 << (31 - 16))
#define LSDMR_RFCR16 (7 << (31 - 16))
#define LSDMR_PRETOACT3 (3 << (31 - 19))
#define LSDMR_PRETOACT7 (7 << (31 - 19))
#define LSDMR_ACTTORW3 (3 << (31 - 22))
#define LSDMR_ACTTORW7 (7 << (31 - 22))
#define LSDMR_ACTTORW6 (6 << (31 - 22))
#define LSDMR_BL8 (1 << (31 - 23))
#define LSDMR_WRC2 (2 << (31 - 27))
#define LSDMR_WRC4 (0 << (31 - 27))
#define LSDMR_BUFCMD (1 << (31 - 29))
#define LSDMR_CL3 (3 << (31 - 31))
#define LSDMR_OP_NORMAL (0 << (31 - 4))
#define LSDMR_OP_ARFRSH (1 << (31 - 4))
#define LSDMR_OP_SRFRSH (2 << (31 - 4))
#define LSDMR_OP_MRW (3 << (31 - 4))
#define LSDMR_OP_PRECH (4 << (31 - 4))
#define LSDMR_OP_PCHALL (5 << (31 - 4))
#define LSDMR_OP_ACTBNK (6 << (31 - 4))
#define LSDMR_OP_RWINV (7 << (31 - 4))
/* LTESR - Transfer Error Status Register
*/
#define LTESR_BM 0x80000000
#define LTESR_FCT 0x40000000
#define LTESR_PAR 0x20000000
#define LTESR_WP 0x04000000
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000
#define LTESR_CS 0x00080000
#define LTESR_CC 0x00000001
#ifndef __ASSEMBLY__
/*
* Local Bus Controller Registers.
*/
typedef struct lbus_bank {
u32 br; /* Base Register */
u32 or; /* Option Register */
} lbus_bank_t;
typedef struct fsl_lbus {
lbus_bank_t bank[8];
u8 res0[0x28];
u32 mar; /* UPM Address Register */
u8 res1[0x4];
u32 mamr; /* UPMA Mode Register */
u32 mbmr; /* UPMB Mode Register */
u32 mcmr; /* UPMC Mode Register */
u8 res2[0x8];
u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
u32 mdr; /* UPM Data Register */
u8 res3[0x4];
u32 lsor; /* Special Operation Initiation Register */
u32 lsdmr; /* SDRAM Mode Register */
u8 res4[0x8];
u32 lurt; /* UPM Refresh Timer */
u32 lsrt; /* SDRAM Refresh Timer */
u8 res5[0x8];
u32 ltesr; /* Transfer Error Status Register */
u32 ltedr; /* Transfer Error Disable Register */
u32 lteir; /* Transfer Error Interrupt Register */
u32 lteatr; /* Transfer Error Attributes Register */
u32 ltear; /* Transfer Error Address Register */
u8 res6[0xC];
u32 lbcr; /* Configuration Register */
u32 lcrr; /* Clock Ratio Register */
u8 res7[0x8];
u32 fmr; /* Flash Mode Register */
u32 fir; /* Flash Instruction Register */
u32 fcr; /* Flash Command Register */
u32 fbar; /* Flash Block Addr Register */
u32 fpar; /* Flash Page Addr Register */
u32 fbcr; /* Flash Byte Count Register */
u8 res8[0xF08];
} fsl_lbus_t;
#endif /* __ASSEMBLY__ */
#endif /* __ASM_PPC_FSL_LBC_H */

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/*
* Copyright 2007,2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __FSL_PCI_H_
#define __FSL_PCI_H_
#include <asm/fsl_law.h>
int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel);
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
void fsl_pci_config_unlock(struct pci_controller *hose);
void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose);
/*
* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
*/
/*
* PCI Translation Registers
*/
typedef struct pci_outbound_window {
u32 potar; /* 0x00 - Address */
u32 potear; /* 0x04 - Address Extended */
u32 powbar; /* 0x08 - Window Base Address */
u32 res1;
u32 powar; /* 0x10 - Window Attributes */
#define POWAR_EN 0x80000000
#define POWAR_IO_READ 0x00080000
#define POWAR_MEM_READ 0x00040000
#define POWAR_IO_WRITE 0x00008000
#define POWAR_MEM_WRITE 0x00004000
u32 res2[3];
} pot_t;
typedef struct pci_inbound_window {
u32 pitar; /* 0x00 - Address */
u32 res1;
u32 piwbar; /* 0x08 - Window Base Address */
u32 piwbear; /* 0x0c - Window Base Address Extended */
u32 piwar; /* 0x10 - Window Attributes */
#define PIWAR_EN 0x80000000
#define PIWAR_PF 0x20000000
#define PIWAR_LOCAL 0x00f00000
#define PIWAR_READ_SNOOP 0x00050000
#define PIWAR_WRITE_SNOOP 0x00005000
u32 res2[3];
} pit_t;
/* PCI/PCI Express Registers */
typedef struct ccsr_pci {
u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */
u32 cfg_data; /* 0x004 - PCI Configuration Data Register */
u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */
u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
u32 config; /* 0x014 - PCIE CONFIG Register */
char res2[8];
u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
u32 pm_command; /* 0x02c - PCIE PM Command register */
char res4[3016]; /* (- #xbf8 #x30)3016 */
u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
u32 res5[64];
pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
#define PIT3 0
#define PIT2 1
#define PIT1 2
#if 0
u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */
u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
char res5[8];
u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */
char res6[12];
u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */
u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */
char res7[4];
u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */
char res8[12];
u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */
u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */
char res9[4];
u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */
char res10[12];
u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */
u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */
char res11[4];
u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */
char res12[12];
u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */
u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */
char res13[4];
u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */
char res14[268];
u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */
char res15[4];
u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */
u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */
char res16[12];
u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */
char res17[4];
u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */
u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */
char res18[12];
u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */
char res19[4];
u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */
char res20[4];
u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */
char res21[12];
#endif
u32 pedr; /* 0xe00 - PCI Error Detect Register */
u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */
u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */
u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */
u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */
/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */
u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */
u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */
u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */
u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */
/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */
char res22[4];
u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */
u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
char res23[200];
u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
char res24[252];
} ccsr_fsl_pci_t;
struct fsl_pci_info {
unsigned long regs;
pci_addr_t mem_bus;
phys_size_t mem_phys;
pci_size_t mem_size;
pci_addr_t io_bus;
phys_size_t io_phys;
pci_size_t io_size;
int pci_num;
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno);
#define SET_STD_PCI_INFO(x, num) \
{ \
x.regs = CONFIG_SYS_PCI##num##_ADDR; \
x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
x.pci_num = num; \
}
#define SET_STD_PCIE_INFO(x, num) \
{ \
x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
x.pci_num = num; \
}
#endif

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#ifndef __FSL_SERDES_H
#define __FSL_SERDES_H
#include <config.h>
#define FSL_SERDES_CLK_100 (0 << 28)
#define FSL_SERDES_CLK_125 (1 << 28)
#define FSL_SERDES_CLK_150 (3 << 28)
#define FSL_SERDES_PROTO_SATA 0
#define FSL_SERDES_PROTO_PEX 1
#define FSL_SERDES_PROTO_PEX_X2 2
#define FSL_SERDES_PROTO_SGMII 3
#define FSL_SERDES_VDD_1V 1
#ifdef CONFIG_FSL_SERDES
extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
#else
static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {}
#endif /* CONFIG_FSL_SERDES */
#endif /* __FSL_SERDES_H */

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/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
#include "config.h"
#include "asm/types.h"
/*
* The following data structure is placed in some memory wich is
* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
* some locked parts of the data cache) to allow for a minimum set of
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
* Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#if defined(CONFIG_8xx)
unsigned long brg_clk;
#endif
#if defined(CONFIG_CPM2)
/* There are many clocks on the MPC8260 - see page 9-5 */
unsigned long vco_out;
unsigned long cpm_clk;
unsigned long scc_clk;
unsigned long brg_clk;
#ifdef CONFIG_PCI
unsigned long pci_clk;
#endif
#endif
unsigned long mem_clk;
#if defined(CONFIG_MPC83xx)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
#endif
#if defined (CONFIG_MPC834x)
u32 usbmph_clk;
#endif /* CONFIG_MPC834x */
#if defined(CONFIG_MPC8315)
u32 tdm_clk;
#endif
u32 core_clk;
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
u32 pci_clk;
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
u32 sata_clk;
#endif
#if defined(CONFIG_MPC8360)
u32 mem_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 lbc_clk;
void *cpu;
#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 i2c1_clk;
u32 i2c2_clk;
#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
#if defined(CONFIG_FSL_LAW)
u32 used_laws;
#endif
#if defined(CONFIG_E500)
u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
#endif
#if defined(CONFIG_MPC512X)
u32 ips_clk;
u32 csb_clk;
u32 pci_clk;
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC8220)
unsigned long bExtUart;
unsigned long inp_clk;
unsigned long pci_clk;
unsigned long vco_clk;
unsigned long pev_clk;
unsigned long flb_clk;
#endif
phys_size_t ram_size; /* RAM size */
unsigned long reset_status; /* reset status register at boot */
#if defined(CONFIG_MPC83xx)
unsigned long arbiter_event_attributes;
unsigned long arbiter_event_address;
#endif
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif
#if defined(CONFIG_4xx)
u32 uart_clk;
#endif /* CONFIG_4xx */
#if defined(CONFIG_SYS_GT_6426x)
unsigned int mirror_hack[16];
#endif
#if defined(CONFIG_A3000) || \
defined(CONFIG_HIDDEN_DRAGON) || \
defined(CONFIG_MUSENKI) || \
defined(CONFIG_SANDPOINT)
void * console_addr;
#endif
unsigned long relocaddr; /* Start address of U-Boot in RAM */
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
unsigned long fb_base; /* Base address of framebuffer memory */
#endif
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
unsigned long post_log_word; /* Record POST activities */
unsigned long post_init_f_time; /* When post_init_f started */
#endif
#ifdef CONFIG_BOARD_TYPES
unsigned long board_type;
#endif
#ifdef CONFIG_MODEM_SUPPORT
unsigned long do_mdm_init;
unsigned long be_quiet;
#endif
#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
#if defined(CONFIG_WD_MAX_RATE)
unsigned long long wdt_last; /* trace watch-dog triggering rate */
#endif
void **jt; /* jump table */
} gd_t;
/*
* Global Data Flags
*/
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
#else /* We could use plain global data, but the resulting code is bigger */
#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
gd_t *gd
#endif
#endif /* __ASM_GBL_DATA_H */

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/*
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_PPC_GPIO_H
#define __ASM_PPC_GPIO_H
#include <asm/types.h>
/* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define GPIO_GROUP_MAX 2
#else
#define GPIO_GROUP_MAX 1
#endif
/* GPIO controller */
struct ppc4xx_gpio {
u32 or; /* Output Control */
u32 tcr; /* Tri-State Control */
u32 osl; /* Output Select 16..31 */
u32 osh; /* Output Select 0..15 */
u32 tsl; /* Tri-State Select 16..31 */
u32 tsh; /* Tri-State Select 0..15 */
u32 odr; /* Open Drain */
u32 ir; /* Input */
u32 rr1; /* Receive Register 1 */
u32 rr2; /* Receive Register 2 */
u32 rr3; /* Receive Register 3 */
u32 reserved;
u32 is1l; /* Input Select 1 16..31 */
u32 is1h; /* Input Select 1 0..15 */
u32 is2l; /* Input Select 2 16..31 */
u32 is2h; /* Input Select 2 0..15 */
u32 is3l; /* Input Select 3 16..31 */
u32 is3h; /* Input Select 3 0..15 */
};
/* Offsets */
#define GPIOx_OR 0x00 /* GPIO Output Register */
#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
#define GPIOx_IR 0x1C /* GPIO Input Register */
#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */
#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */
#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */
#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
#define GPIO0 0
#define GPIO1 1
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000
#define GPIO_ALT2_SEL 0x80000000
#define GPIO_ALT3_SEL 0xc0000000
#define GPIO_IN_SEL 0x40000000
#define GPIO_MASK 0xc0000000
#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
#ifndef __ASSEMBLY__
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
typedef struct {
unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
gpio_out_t out_val;/* Default Output Value */
} gpio_param_s;
#endif
void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val);
int gpio_read_out_bit(int pin);
int gpio_read_in_bit(int pin);
void gpio_set_chip_configuration(void);
#endif /* __ASM_PPC_GPIO_H */

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arch/powerpc/include/asm/immap_512x.h Normal file
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arch/powerpc/include/asm/immap_8220.h Normal file
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/*
* MPC8220 Internal Memory Map
* Copyright (c) 2004 TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* The Internal Memory Map of the 8220.
*
*/
#ifndef __IMMAP_MPC8220__
#define __IMMAP_MPC8220__
/*
* System configuration registers.
*/
typedef struct sys_conf {
u16 mbar; /* 0x00 */
u16 res1;
u16 res2; /* 0x04 */
u16 sdramds;
u32 res3[6]; /* 0x08 */
u32 cscfg[6]; /* 0x20 */
u32 res4[2]; /* 0x38 */
u8 res5[3]; /* 0x40 */
u8 rstctrl;
u8 res6[3]; /* 0x44 */
u8 rststat;
u32 res7[2]; /* 0x48 */
u32 jtagid; /* 0x50 */
} sysconf8220_t;
/*
* Memory controller registers.
*/
typedef struct mem_ctlr {
ushort mode; /* 0x100 */
ushort res1;
u32 ctrl; /* 0x104 */
u32 cfg1; /* 0x108 */
u32 cfg2; /* 0x10c */
} memctl8220_t;
/*
* XLB Arbitration registers
*/
typedef struct xlb_arb
{
uint res1[16]; /* 0x200 */
uint config; /* 0x240 */
uint version; /* 0x244 */
uint status; /* 0x248 */
uint intEnable; /* 0x24c */
uint addrCap; /* 0x250 */
uint busSigCap; /* 0x254 */
uint addrTenTimeOut; /* 0x258 */
uint dataTenTimeOut; /* 0x25c */
uint busActTimeOut; /* 0x260 */
uint mastPriEn; /* 0x264 */
uint mastPriority; /* 0x268 */
uint baseAddr; /* 0x26c */
} xlbarb8220_t;
/*
* Flexbus registers
*/
typedef struct flexbus
{
ushort csar0; /* 0x00 */
ushort res1;
uint csmr0; /* 0x04 */
uint cscr0; /* 0x08 */
ushort csar1; /* 0x0c */
ushort res2;
uint csmr1; /* 0x10 */
uint cscr1; /* 0x14 */
ushort csar2; /* 0x18 */
ushort res3;
uint csmr2; /* 0x1c */
uint cscr2; /* 0x20 */
ushort csar3; /* 0x24 */
ushort res4;
uint csmr3; /* 0x28 */
uint cscr3; /* 0x2c */
ushort csar4; /* 0x30 */
ushort res5;
uint csmr4; /* 0x34 */
uint cscr4; /* 0x38 */
ushort csar5; /* 0x3c */
ushort res6;
uint csmr5; /* 0x40 */
uint cscr5; /* 0x44 */
} flexbus8220_t;
/*
* GPIO registers
*/
typedef struct gpio
{
u32 out; /* 0x00 */
u32 obs; /* 0x04 */
u32 obc; /* 0x08 */
u32 obt; /* 0x0c */
u32 en; /* 0x10 */
u32 ebs; /* 0x14 */
u32 ebc; /* 0x18 */
u32 ebt; /* 0x1c */
u32 mc; /* 0x20 */
u32 st; /* 0x24 */
u32 intr; /* 0x28 */
} gpio8220_t;
/*
* General Purpose Timer registers
*/
typedef struct gptimer
{
u8 OCPW;
u8 OctIct;
u8 Control;
u8 Mode;
u16 Prescl; /* Prescale */
u16 Count; /* Count */
u16 PwmWid; /* PWM Width */
u8 PwmOp; /* Output Polarity */
u8 PwmLd; /* Immediate Update */
u16 Capture; /* Capture internal counter */
u8 OvfPin; /* Ovf and Pin */
u8 Int; /* Interrupts */
} gptmr8220_t;
/*
* PSC registers
*/
typedef struct psc
{
u32 mr1_2; /* 0x00 Mode reg 1 & 2 */
u32 sr_csr; /* 0x04 Status/Clock Select reg */
u32 cr; /* 0x08 Command reg */
u8 xmitbuf[4]; /* 0x0c Receive/Transmit Buffer */
u32 ipcr_acr; /* 0x10 Input Port Change/Auxiliary Control reg */
u32 isr_imr; /* 0x14 Interrupt Status/Mask reg */
u32 ctur; /* 0x18 Counter Timer Upper reg */
u32 ctlr; /* 0x1c Counter Timer Lower reg */
u32 rsvd1[4]; /* 0x20 ... 0x2c */
u32 ivr; /* 0x30 Interrupt Vector reg */
u32 ipr; /* 0x34 Input Port reg */
u32 opsetr; /* 0x38 Output Port Set reg */
u32 opresetr; /* 0x3c Output Port Reset reg */
u32 sicr; /* 0x40 PSC/IrDA control reg */
u32 ircr1; /* 0x44 IrDA control reg 1*/
u32 ircr2; /* 0x48 IrDA control reg 2*/
u32 irsdr; /* 0x4c IrDA SIR Divide reg */
u32 irmdr; /* 0x50 IrDA MIR Divide reg */
u32 irfdr; /* 0x54 PSC IrDA FIR Divide reg */
u32 rfnum; /* 0x58 RX-FIFO counter */
u32 txnum; /* 0x5c TX-FIFO counter */
u32 rfdata; /* 0x60 RX-FIFO data */
u32 rfstat; /* 0x64 RX-FIFO status */
u32 rfcntl; /* 0x68 RX-FIFO control */
u32 rfalarm; /* 0x6c RX-FIFO alarm */
u32 rfrptr; /* 0x70 RX-FIFO read pointer */
u32 rfwptr; /* 0x74 RX-FIFO write pointer */
u32 rflfrptr; /* 0x78 RX-FIFO last read frame pointer */
u32 rflfwptr; /* 0x7c RX-FIFO last write frame pointer */
u32 tfdata; /* 0x80 TX-FIFO data */
u32 tfstat; /* 0x84 TX-FIFO status */
u32 tfcntl; /* 0x88 TX-FIFO control */
u32 tfalarm; /* 0x8c TX-FIFO alarm */
u32 tfrptr; /* 0x90 TX-FIFO read pointer */
u32 tfwptr; /* 0x94 TX-FIFO write pointer */
u32 tflfrptr; /* 0x98 TX-FIFO last read frame pointer */
u32 tflfwptr; /* 0x9c TX-FIFO last write frame pointer */
} psc8220_t;
/*
* Interrupt Controller registers
*/
typedef struct interrupt_controller {
} intctl8220_t;
/* Fast controllers
*/
/*
* I2C registers
*/
typedef struct i2c
{
u8 adr; /* 0x00 */
u8 res1[3];
u8 fdr; /* 0x04 */
u8 res2[3];
u8 cr; /* 0x08 */
u8 res3[3];
u8 sr; /* 0x0C */
u8 res4[3];
u8 dr; /* 0x10 */
u8 res5[3];
u32 reserved0; /* 0x14 */
u32 reserved1; /* 0x18 */
u32 reserved2; /* 0x1c */
u8 icr; /* 0x20 */
u8 res6[3];
} i2c8220_t;
/*
* Port Configuration Registers
*/
typedef struct pcfg
{
uint pcfg0; /* 0x00 */
uint pcfg1; /* 0x04 */
uint pcfg2; /* 0x08 */
uint pcfg3; /* 0x0c */
} pcfg8220_t;
/* ...and the whole thing wrapped up....
*/
typedef struct immap {
sysconf8220_t im_sysconf; /* System Configuration */
memctl8220_t im_memctl; /* Memory Controller */
xlbarb8220_t im_xlbarb; /* XLB Arbitration */
psc8220_t im_psc; /* PSC controller */
flexbus8220_t im_fb; /* FlexBus Controller */
i2c8220_t im_i2c; /* I2C control/status */
pcfg8220_t im_pcfg; /* Port configuration */
} immap_t;
#endif /* __IMMAP_MPC8220__ */

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arch/powerpc/include/asm/immap_8260.h Normal file
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/*
* MPC8260 Internal Memory Map
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
*
* The Internal Memory Map of the 8260. I don't know how generic
* this will be, as I don't have any knowledge of the subsequent
* parts at this time. I copied this from the 8xx_immap.h.
*/
#ifndef __IMMAP_82XX__
#define __IMMAP_82XX__
/* System configuration registers.
*/
typedef struct sys_conf {
uint sc_siumcr;
uint sc_sypcr;
char res1[6];
ushort sc_swsr;
char res2[20];
uint sc_bcr;
u_char sc_ppc_acr;
char res3[3];
uint sc_ppc_alrh;
uint sc_ppc_alrl;
u_char sc_lcl_acr;
char res4[3];
uint sc_lcl_alrh;
uint sc_lcl_alrl;
uint sc_tescr1;
uint sc_tescr2;
uint sc_ltescr1;
uint sc_ltescr2;
uint sc_pdtea;
u_char sc_pdtem;
char res5[3];
uint sc_ldtea;
u_char sc_ldtem;
char res6[163];
} sysconf8260_t;
/* Memory controller registers.
*/
typedef struct mem_ctlr {
uint memc_br0;
uint memc_or0;
uint memc_br1;
uint memc_or1;
uint memc_br2;
uint memc_or2;
uint memc_br3;
uint memc_or3;
uint memc_br4;
uint memc_or4;
uint memc_br5;
uint memc_or5;
uint memc_br6;
uint memc_or6;
uint memc_br7;
uint memc_or7;
uint memc_br8;
uint memc_or8;
uint memc_br9;
uint memc_or9;
uint memc_br10;
uint memc_or10;
uint memc_br11;
uint memc_or11;
char res1[8];
uint memc_mar;
char res2[4];
uint memc_mamr;
uint memc_mbmr;
uint memc_mcmr;
char res3[8];
ushort memc_mptpr;
char res4[2];
uint memc_mdr;
char res5[4];
uint memc_psdmr;
uint memc_lsdmr;
u_char memc_purt;
char res6[3];
u_char memc_psrt;
char res7[3];
u_char memc_lurt;
char res8[3];
u_char memc_lsrt;
char res9[3];
uint memc_immr;
uint memc_pcibr0;
uint memc_pcibr1;
char res10[16];
uint memc_pcimsk0;
uint memc_pcimsk1;
char res11[52];
} memctl8260_t;
/* System Integration Timers.
*/
typedef struct sys_int_timers {
char res1[32];
ushort sit_tmcntsc;
char res2[2];
uint sit_tmcnt;
char res3[4];
uint sit_tmcntal;
char res4[16];
ushort sit_piscr;
char res5[2];
uint sit_pitc;
uint sit_pitr;
char res6[94];
char res7[390];
} sit8260_t;
/* PCI
*/
typedef struct pci_config {
uint pci_omisr;
uint pci_ominr;
char res1[8];
uint pci_ifqpr;
uint pci_ofqpr;
char res2[8];
uint pci_imr0;
uint pci_imr1;
uint pci_omr0;
uint pci_omr1;
uint pci_odr;
char res3[4];
uint pci_idr;
char res4[20];
uint pci_imisr;
uint pci_imimr;
char res5[24];
uint pci_ifhpr;
char res5_2[4];
uint pci_iftpr;
char res6[4];
uint pci_iphpr;
char res6_2[4];
uint pci_iptpr;
char res7[4];
uint pci_ofhpr;
char res7_2[4];
uint pci_oftpr;
char res8[4];
uint pci_ophpr;
char res8_2[4];
uint pci_optpr;
char res9[8];
uint pci_mucr;
char res10[8];
uint pci_qbar;
char res11[12];
uint pci_dmamr0;
uint pci_dmasr0;
uint pci_dmacdar0;
char res12[4];
uint pci_dmasar0;
char res13[4];
uint pci_dmadar0;
char res14[4];
uint pci_dmabcr0;
uint pci_dmandar0;
char res15[88];
uint pci_dmamr1;
uint pci_dmasr1;
uint pci_dmacdar1;
char res16[4];
uint pci_dmasar1;
char res17[4];
uint pci_dmadar1;
char res18[4];
uint pci_dmabcr1;
uint pci_dmandar1;
char res19[88];
uint pci_dmamr2;
uint pci_dmasr2;
uint pci_dmacdar2;
char res20[4];
uint pci_dmasar2;
char res21[4];
uint pci_dmadar2;
char res22[4];
uint pci_dmabcr2;
uint pci_dmandar2;
char res23[88];
uint pci_dmamr3;
uint pci_dmasr3;
uint pci_dmacdar3;
char res24[4];
uint pci_dmasar3;
char res25[4];
uint pci_dmadar3;
char res26[4];
uint pci_dmabcr3;
uint pci_dmandar3;
char res27[344];
uint pci_potar0;
char res28[4];
uint pci_pobar0;
char res29[4];
uint pci_pocmr0;
char res30[4];
uint pci_potar1;
char res31[4];
uint pci_pobar1;
char res32[4];
uint pci_pocmr1;
char res33[4];
uint pci_potar2;
char res34[4];
uint pci_pobar2;
char res35[4];
uint pci_pocmr2;
char res36[52];
uint pci_ptcr;
uint pci_gpcr;
uint pci_gcr;
uint pci_esr;
uint pci_emr;
uint pci_ecr;
uint pci_eacr;
char res37[4];
uint pci_edcr;
char res38[4];
uint pci_eccr;
char res39[44];
uint pci_pitar1;
char res40[4];
uint pci_pibar1;
char res41[4];
uint pci_picmr1;
char res42[4];
uint pci_pitar0;
char res43[4];
uint pci_pibar0;
char res44[4];
uint pci_picmr0;
char res45[4];
uint pci_cfg_addr;
uint pci_cfg_data;
uint pci_int_ack;
char res46[756];
}pci8260_t;
#define PISCR_PIRQ_MASK ((ushort)0xff00)
#define PISCR_PS ((ushort)0x0080)
#define PISCR_PIE ((ushort)0x0004)
#define PISCR_PTF ((ushort)0x0002)
#define PISCR_PTE ((ushort)0x0001)
/* Interrupt Controller.
*/
typedef struct interrupt_controller {
ushort ic_sicr;
char res1[2];
uint ic_sivec;
uint ic_sipnrh;
uint ic_sipnrl;
uint ic_siprr;
uint ic_scprrh;
uint ic_scprrl;
uint ic_simrh;
uint ic_simrl;
uint ic_siexr;
char res2[88];
} intctl8260_t;
/* Clocks and Reset.
*/
typedef struct clk_and_reset {
uint car_sccr;
char res1[4];
uint car_scmr;
char res2[4];
uint car_rsr;
uint car_rmr;
char res[104];
} car8260_t;
/* Input/Output Port control/status registers.
* Names consistent with processor manual, although they are different
* from the original 8xx names.......
*/
typedef struct io_port {
uint iop_pdira;
uint iop_ppara;
uint iop_psora;
uint iop_podra;
uint iop_pdata;
char res1[12];
uint iop_pdirb;
uint iop_pparb;
uint iop_psorb;
uint iop_podrb;
uint iop_pdatb;
char res2[12];
uint iop_pdirc;
uint iop_pparc;
uint iop_psorc;
uint iop_podrc;
uint iop_pdatc;
char res3[12];
uint iop_pdird;
uint iop_ppard;
uint iop_psord;
uint iop_podrd;
uint iop_pdatd;
char res4[12];
} iop8260_t;
/* Communication Processor Module Timers
*/
typedef struct cpm_timers {
u_char cpmt_tgcr1;
char res1[3];
u_char cpmt_tgcr2;
char res2[11];
ushort cpmt_tmr1;
ushort cpmt_tmr2;
ushort cpmt_trr1;
ushort cpmt_trr2;
ushort cpmt_tcr1;
ushort cpmt_tcr2;
ushort cpmt_tcn1;
ushort cpmt_tcn2;
ushort cpmt_tmr3;
ushort cpmt_tmr4;
ushort cpmt_trr3;
ushort cpmt_trr4;
ushort cpmt_tcr3;
ushort cpmt_tcr4;
ushort cpmt_tcn3;
ushort cpmt_tcn4;
ushort cpmt_ter1;
ushort cpmt_ter2;
ushort cpmt_ter3;
ushort cpmt_ter4;
char res3[584];
} cpmtimer8260_t;
/* DMA control/status registers.
*/
typedef struct sdma_csr {
char res0[24];
u_char sdma_sdsr;
char res1[3];
u_char sdma_sdmr;
char res2[3];
u_char sdma_idsr1;
char res3[3];
u_char sdma_idmr1;
char res4[3];
u_char sdma_idsr2;
char res5[3];
u_char sdma_idmr2;
char res6[3];
u_char sdma_idsr3;
char res7[3];
u_char sdma_idmr3;
char res8[3];
u_char sdma_idsr4;
char res9[3];
u_char sdma_idmr4;
char res10[707];
} sdma8260_t;
/* Fast controllers
*/
typedef struct fcc {
uint fcc_gfmr;
uint fcc_fpsmr;
ushort fcc_ftodr;
char res1[2];
ushort fcc_fdsr;
char res2[2];
ushort fcc_fcce;
char res3[2];
ushort fcc_fccm;
char res4[2];
u_char fcc_fccs;
char res5[3];
u_char fcc_ftirr_phy[4];
} fcc_t;
/* Fast controllers continued
*/
typedef struct fcc_c {
uint fcc_firper;
uint fcc_firer;
uint fcc_firsr_hi;
uint fcc_firsr_lo;
u_char fcc_gfemr;
char res1[15];
} fcc_c_t;
/* TC Layer
*/
typedef struct tclayer {
ushort tc_tcmode;
ushort tc_cdsmr;
ushort tc_tcer;
ushort tc_rcc;
ushort tc_tcmr;
ushort tc_fcc;
ushort tc_ccc;
ushort tc_icc;
ushort tc_tcc;
ushort tc_ecc;
char res1[12];
} tclayer_t;
/* I2C
*/
typedef struct i2c {
u_char i2c_i2mod;
char res1[3];
u_char i2c_i2add;
char res2[3];
u_char i2c_i2brg;
char res3[3];
u_char i2c_i2com;
char res4[3];
u_char i2c_i2cer;
char res5[3];
u_char i2c_i2cmr;
char res6[331];
} i2c8260_t;
typedef struct scc { /* Serial communication channels */
uint scc_gsmrl;
uint scc_gsmrh;
ushort scc_psmr;
char res1[2];
ushort scc_todr;
ushort scc_dsr;
ushort scc_scce;
char res2[2];
ushort scc_sccm;
char res3;
u_char scc_sccs;
char res4[8];
} scc_t;
typedef struct smc { /* Serial management channels */
char res1[2];
ushort smc_smcmr;
char res2[2];
u_char smc_smce;
char res3[3];
u_char smc_smcm;
char res4[5];
} smc_t;
/* Serial Peripheral Interface.
*/
typedef struct im_spi {
ushort spi_spmode;
char res1[4];
u_char spi_spie;
char res2[3];
u_char spi_spim;
char res3[2];
u_char spi_spcom;
char res4[82];
} im_spi_t;
/* CPM Mux.
*/
typedef struct cpmux {
u_char cmx_si1cr;
char res1;
u_char cmx_si2cr;
char res2;
uint cmx_fcr;
uint cmx_scr;
u_char cmx_smr;
char res3;
ushort cmx_uar;
char res4[16];
} cpmux_t;
/* SIRAM control
*/
typedef struct siram {
ushort si_amr;
ushort si_bmr;
ushort si_cmr;
ushort si_dmr;
u_char si_gmr;
char res1;
u_char si_cmdr;
char res2;
u_char si_str;
char res3;
ushort si_rsr;
} siramctl_t;
typedef struct mcc {
ushort mcc_mcce;
char res1[2];
ushort mcc_mccm;
char res2[2];
u_char mcc_mccf;
char res3[7];
} mcc_t;
typedef struct comm_proc {
uint cp_cpcr;
uint cp_rccr;
char res1[14];
ushort cp_rter;
char res2[2];
ushort cp_rtmr;
ushort cp_rtscr;
char res3[2];
uint cp_rtsr;
char res4[12];
} cpm8260_t;
/* ...and the whole thing wrapped up....
*/
typedef struct immap {
/* Some references are into the unique and known dpram spaces,
* others are from the generic base.
*/
#define im_dprambase im_dpram1
u_char im_dpram1[16*1024];
char res1[16*1024];
u_char im_dpram2[4*1024];
char res2[8*1024];
u_char im_dpram3[4*1024];
char res3[16*1024];
sysconf8260_t im_siu_conf; /* SIU Configuration */
memctl8260_t im_memctl; /* Memory Controller */
sit8260_t im_sit; /* System Integration Timers */
pci8260_t im_pci; /* PCI Configuration */
intctl8260_t im_intctl; /* Interrupt Controller */
car8260_t im_clkrst; /* Clocks and reset */
iop8260_t im_ioport; /* IO Port control/status */
cpmtimer8260_t im_cpmtimer; /* CPM timers */
sdma8260_t im_sdma; /* SDMA control/status */
fcc_t im_fcc[3]; /* Three FCCs */
char res4[32];
fcc_c_t im_fcc_c[3]; /* Continued FCCs */
char res4a[32];
tclayer_t im_tclayer[8]; /* Eight TCLayers */
ushort tc_tcgsr;
ushort tc_tcger;
/* First set of baud rate generators.
*/
char res4b[236];
uint im_brgc5;
uint im_brgc6;
uint im_brgc7;
uint im_brgc8;
char res5[608];
i2c8260_t im_i2c; /* I2C control/status */
cpm8260_t im_cpm; /* Communication processor */
/* Second set of baud rate generators.
*/
uint im_brgc1;
uint im_brgc2;
uint im_brgc3;
uint im_brgc4;
scc_t im_scc[4]; /* Four SCCs */
smc_t im_smc[2]; /* Couple of SMCs */
im_spi_t im_spi; /* A SPI */
cpmux_t im_cpmux; /* CPM clock route mux */
siramctl_t im_siramctl1; /* First SI RAM Control */
mcc_t im_mcc1; /* First MCC */
siramctl_t im_siramctl2; /* Second SI RAM Control */
mcc_t im_mcc2; /* Second MCC */
char res6[1184];
ushort im_si1txram[256];
char res7[512];
ushort im_si1rxram[256];
char res8[512];
ushort im_si2txram[256];
char res9[512];
ushort im_si2rxram[256];
char res10[512];
char res11[4096];
} immap_t;
#endif /* __IMMAP_82XX__ */

877
arch/powerpc/include/asm/immap_83xx.h Normal file
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@@ -0,0 +1,877 @@
/*
* Copyright 2004-2009 Freescale Semiconductor, Inc.
*
* MPC83xx Internal Memory Map
*
* Contributors:
* Dave Liu <daveliu@freescale.com>
* Tanya Jiang <tanya.jiang@freescale.com>
* Mandy Lavi <mandy.lavi@freescale.com>
* Eran Liberty <liberty@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __IMMAP_83xx__
#define __IMMAP_83xx__
#include <asm/types.h>
#include <asm/fsl_i2c.h>
#include <asm/mpc8xxx_spi.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_dma.h>
/*
* Local Access Window
*/
typedef struct law83xx {
u32 bar; /* LBIU local access window base address register */
u32 ar; /* LBIU local access window attribute register */
} law83xx_t;
/*
* System configuration registers
*/
typedef struct sysconf83xx {
u32 immrbar; /* Internal memory map base address register */
u8 res0[0x04];
u32 altcbar; /* Alternate configuration base address register */
u8 res1[0x14];
law83xx_t lblaw[4]; /* LBIU local access window */
u8 res2[0x20];
law83xx_t pcilaw[2]; /* PCI local access window */
u8 res3[0x10];
law83xx_t pcielaw[2]; /* PCI Express local access window */
u8 res4[0x10];
law83xx_t ddrlaw[2]; /* DDR local access window */
u8 res5[0x50];
u32 sgprl; /* System General Purpose Register Low */
u32 sgprh; /* System General Purpose Register High */
u32 spridr; /* System Part and Revision ID Register */
u8 res6[0x04];
u32 spcr; /* System Priority Configuration Register */
u32 sicrl; /* System I/O Configuration Register Low */
u32 sicrh; /* System I/O Configuration Register High */
u8 res7[0x04];
u32 sidcr0; /* System I/O Delay Configuration Register 0 */
u32 sidcr1; /* System I/O Delay Configuration Register 1 */
u32 ddrcdr; /* DDR Control Driver Register */
u32 ddrdsr; /* DDR Debug Status Register */
u32 obir; /* Output Buffer Impedance Register */
u8 res8[0xC];
u32 pecr1; /* PCI Express control register 1 */
u32 pecr2; /* PCI Express control register 2 */
u8 res9[0xB8];
} sysconf83xx_t;
/*
* Watch Dog Timer (WDT) Registers
*/
typedef struct wdt83xx {
u8 res0[4];
u32 swcrr; /* System watchdog control register */
u32 swcnr; /* System watchdog count register */
u8 res1[2];
u16 swsrr; /* System watchdog service register */
u8 res2[0xF0];
} wdt83xx_t;
/*
* RTC/PIT Module Registers
*/
typedef struct rtclk83xx {
u32 cnr; /* control register */
u32 ldr; /* load register */
u32 psr; /* prescale register */
u32 ctr; /* counter value field register */
u32 evr; /* event register */
u32 alr; /* alarm register */
u8 res0[0xE8];
} rtclk83xx_t;
/*
* Global timer module
*/
typedef struct gtm83xx {
u8 cfr1; /* Timer1/2 Configuration */
u8 res0[3];
u8 cfr2; /* Timer3/4 Configuration */
u8 res1[10];
u16 mdr1; /* Timer1 Mode Register */
u16 mdr2; /* Timer2 Mode Register */
u16 rfr1; /* Timer1 Reference Register */
u16 rfr2; /* Timer2 Reference Register */
u16 cpr1; /* Timer1 Capture Register */
u16 cpr2; /* Timer2 Capture Register */
u16 cnr1; /* Timer1 Counter Register */
u16 cnr2; /* Timer2 Counter Register */
u16 mdr3; /* Timer3 Mode Register */
u16 mdr4; /* Timer4 Mode Register */
u16 rfr3; /* Timer3 Reference Register */
u16 rfr4; /* Timer4 Reference Register */
u16 cpr3; /* Timer3 Capture Register */
u16 cpr4; /* Timer4 Capture Register */
u16 cnr3; /* Timer3 Counter Register */
u16 cnr4; /* Timer4 Counter Register */
u16 evr1; /* Timer1 Event Register */
u16 evr2; /* Timer2 Event Register */
u16 evr3; /* Timer3 Event Register */
u16 evr4; /* Timer4 Event Register */
u16 psr1; /* Timer1 Prescaler Register */
u16 psr2; /* Timer2 Prescaler Register */
u16 psr3; /* Timer3 Prescaler Register */
u16 psr4; /* Timer4 Prescaler Register */
u8 res[0xC0];
} gtm83xx_t;
/*
* Integrated Programmable Interrupt Controller
*/
typedef struct ipic83xx {
u32 sicfr; /* System Global Interrupt Configuration Register */
u32 sivcr; /* System Global Interrupt Vector Register */
u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
u8 res0[8];
u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
u32 simsr_h; /* System Internal Interrupt Mask Register - High */
u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
u8 res1[4];
u32 sepnr; /* System External Interrupt Pending Register */
u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
u32 semsr; /* System External Interrupt Mask Register */
u32 secnr; /* System External Interrupt Control Register */
u32 sersr; /* System Error Status Register */
u32 sermr; /* System Error Mask Register */
u32 sercr; /* System Error Control Register */
u8 res2[4];
u32 sifcr_h; /* System Internal Interrupt Force Register - High */
u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
u32 sefcr; /* System External Interrupt Force Register */
u32 serfr; /* System Error Force Register */
u32 scvcr; /* System Critical Interrupt Vector Register */
u32 smvcr; /* System Management Interrupt Vector Register */
u8 res3[0x98];
} ipic83xx_t;
/*
* System Arbiter Registers
*/
typedef struct arbiter83xx {
u32 acr; /* Arbiter Configuration Register */
u32 atr; /* Arbiter Timers Register */
u8 res[4];
u32 aer; /* Arbiter Event Register */
u32 aidr; /* Arbiter Interrupt Definition Register */
u32 amr; /* Arbiter Mask Register */
u32 aeatr; /* Arbiter Event Attributes Register */
u32 aeadr; /* Arbiter Event Address Register */
u32 aerr; /* Arbiter Event Response Register */
u8 res1[0xDC];
} arbiter83xx_t;
/*
* Reset Module
*/
typedef struct reset83xx {
u32 rcwl; /* Reset Configuration Word Low Register */
u32 rcwh; /* Reset Configuration Word High Register */
u8 res0[8];
u32 rsr; /* Reset Status Register */
u32 rmr; /* Reset Mode Register */
u32 rpr; /* Reset protection Register */
u32 rcr; /* Reset Control Register */
u32 rcer; /* Reset Control Enable Register */
u8 res1[0xDC];
} reset83xx_t;
/*
* Clock Module
*/
typedef struct clk83xx {
u32 spmr; /* system PLL mode Register */
u32 occr; /* output clock control Register */
u32 sccr; /* system clock control Register */
u8 res0[0xF4];
} clk83xx_t;
/*
* Power Management Control Module
*/
typedef struct pmc83xx {
u32 pmccr; /* PMC Configuration Register */
u32 pmcer; /* PMC Event Register */
u32 pmcmr; /* PMC Mask Register */
u32 pmccr1; /* PMC Configuration Register 1 */
u32 pmccr2; /* PMC Configuration Register 2 */
u8 res0[0xEC];
} pmc83xx_t;
/*
* General purpose I/O module
*/
typedef struct gpio83xx {
u32 dir; /* direction register */
u32 odr; /* open drain register */
u32 dat; /* data register */
u32 ier; /* interrupt event register */
u32 imr; /* interrupt mask register */
u32 icr; /* external interrupt control register */
u8 res0[0xE8];
} gpio83xx_t;
/*
* QE Ports Interrupts Registers
*/
typedef struct qepi83xx {
u8 res0[0xC];
u32 qepier; /* QE Ports Interrupt Event Register */
u32 qepimr; /* QE Ports Interrupt Mask Register */
u32 qepicr; /* QE Ports Interrupt Control Register */
u8 res1[0xE8];
} qepi83xx_t;
/*
* QE Parallel I/O Ports
*/
typedef struct gpio_n {
u32 podr; /* Open Drain Register */
u32 pdat; /* Data Register */
u32 dir1; /* direction register 1 */
u32 dir2; /* direction register 2 */
u32 ppar1; /* Pin Assignment Register 1 */
u32 ppar2; /* Pin Assignment Register 2 */
} gpio_n_t;
typedef struct qegpio83xx {
gpio_n_t ioport[0x7];
u8 res0[0x358];
} qepio83xx_t;
/*
* QE Secondary Bus Access Windows
*/
typedef struct qesba83xx {
u32 lbmcsar; /* Local bus memory controller start address */
u32 sdmcsar; /* Secondary DDR memory controller start address */
u8 res0[0x38];
u32 lbmcear; /* Local bus memory controller end address */
u32 sdmcear; /* Secondary DDR memory controller end address */
u8 res1[0x38];
u32 lbmcar; /* Local bus memory controller attributes */
u32 sdmcar; /* Secondary DDR memory controller attributes */
u8 res2[0x378];
} qesba83xx_t;
/*
* DDR Memory Controller Memory Map
*/
typedef struct ddr_cs_bnds {
u32 csbnds;
u8 res0[4];
} ddr_cs_bnds_t;
typedef struct ddr83xx {
ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
u8 res0[0x60];
u32 cs_config[4]; /* Chip Select x Configuration */
u8 res1[0x70];
u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
u32 sdram_cfg; /* SDRAM Control Configuration */
u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
u32 sdram_mode; /* SDRAM Mode Configuration */
u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
u32 sdram_md_cntl; /* SDRAM Mode Control */
u32 sdram_interval; /* SDRAM Interval Configuration */
u32 ddr_data_init; /* SDRAM Data Initialization */
u8 res2[4];
u32 sdram_clk_cntl; /* SDRAM Clock Control */
u8 res3[0x14];
u32 ddr_init_addr; /* DDR training initialization address */
u32 ddr_init_ext_addr; /* DDR training initialization extended address */
u8 res4[0xAA8];
u32 ddr_ip_rev1; /* DDR IP block revision 1 */
u32 ddr_ip_rev2; /* DDR IP block revision 2 */
u8 res5[0x200];
u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
u8 res6[0x14];
u32 capture_data_hi; /* Memory Data Path Read Capture High */
u32 capture_data_lo; /* Memory Data Path Read Capture Low */
u32 capture_ecc; /* Memory Data Path Read Capture ECC */
u8 res7[0x14];
u32 err_detect; /* Memory Error Detect */
u32 err_disable; /* Memory Error Disable */
u32 err_int_en; /* Memory Error Interrupt Enable */
u32 capture_attributes; /* Memory Error Attributes Capture */
u32 capture_address; /* Memory Error Address Capture */
u32 capture_ext_address;/* Memory Error Extended Address Capture */
u32 err_sbe; /* Memory Single-Bit ECC Error Management */
u8 res8[0xA4];
u32 debug_reg;
u8 res9[0xFC];
} ddr83xx_t;
/*
* DUART
*/
typedef struct duart83xx {
u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
u8 uier_udmb; /* combined register for UIER and UDMB */
u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
u8 ulcr; /* line control register */
u8 umcr; /* MODEM control register */
u8 ulsr; /* line status register */
u8 umsr; /* MODEM status register */
u8 uscr; /* scratch register */
u8 res0[8];
u8 udsr; /* DMA status register */
u8 res1[3];
u8 res2[0xEC];
} duart83xx_t;
/*
* DMA/Messaging Unit
*/
typedef struct dma83xx {
u32 res0[0xC]; /* 0x0-0x29 reseverd */
u32 omisr; /* 0x30 Outbound message interrupt status register */
u32 omimr; /* 0x34 Outbound message interrupt mask register */
u32 res1[0x6]; /* 0x38-0x49 reserved */
u32 imr0; /* 0x50 Inbound message register 0 */
u32 imr1; /* 0x54 Inbound message register 1 */
u32 omr0; /* 0x58 Outbound message register 0 */
u32 omr1; /* 0x5C Outbound message register 1 */
u32 odr; /* 0x60 Outbound doorbell register */
u32 res2; /* 0x64-0x67 reserved */
u32 idr; /* 0x68 Inbound doorbell register */
u32 res3[0x5]; /* 0x6C-0x79 reserved */
u32 imisr; /* 0x80 Inbound message interrupt status register */
u32 imimr; /* 0x84 Inbound message interrupt mask register */
u32 res4[0x1E]; /* 0x88-0x99 reserved */
struct fsl_dma dma[4];
} dma83xx_t;
/*
* PCI Software Configuration Registers
*/
typedef struct pciconf83xx {
u32 config_address;
u32 config_data;
u32 int_ack;
u8 res[116];
} pciconf83xx_t;
/*
* PCI Outbound Translation Register
*/
typedef struct pci_outbound_window {
u32 potar;
u8 res0[4];
u32 pobar;
u8 res1[4];
u32 pocmr;
u8 res2[4];
} pot83xx_t;
/*
* Sequencer
*/
typedef struct ios83xx {
pot83xx_t pot[6];
u8 res0[0x60];
u32 pmcr;
u8 res1[4];
u32 dtcr;
u8 res2[4];
} ios83xx_t;
/*
* PCI Controller Control and Status Registers
*/
typedef struct pcictrl83xx {
u32 esr;
u32 ecdr;
u32 eer;
u32 eatcr;
u32 eacr;
u32 eeacr;
u32 edlcr;
u32 edhcr;
u32 gcr;
u32 ecr;
u32 gsr;
u8 res0[12];
u32 pitar2;
u8 res1[4];
u32 pibar2;
u32 piebar2;
u32 piwar2;
u8 res2[4];
u32 pitar1;
u8 res3[4];
u32 pibar1;
u32 piebar1;
u32 piwar1;
u8 res4[4];
u32 pitar0;
u8 res5[4];
u32 pibar0;
u8 res6[4];
u32 piwar0;
u8 res7[132];
} pcictrl83xx_t;
/*
* USB
*/
typedef struct usb83xx {
u8 fixme[0x1000];
} usb83xx_t;
/*
* TSEC
*/
typedef struct tsec83xx {
u8 fixme[0x1000];
} tsec83xx_t;
/*
* Security
*/
typedef struct security83xx {
u8 fixme[0x10000];
} security83xx_t;
/*
* PCI Express
*/
struct pex_inbound_window {
u32 ar;
u32 tar;
u32 barl;
u32 barh;
};
struct pex_outbound_window {
u32 ar;
u32 bar;
u32 tarl;
u32 tarh;
};
struct pex_csb_bridge {
u32 pex_csb_ver;
u32 pex_csb_cab;
u32 pex_csb_ctrl;
u8 res0[8];
u32 pex_dms_dstmr;
u8 res1[4];
u32 pex_cbs_stat;
u8 res2[0x20];
u32 pex_csb_obctrl;
u32 pex_csb_obstat;
u8 res3[0x98];
u32 pex_csb_ibctrl;
u32 pex_csb_ibstat;
u8 res4[0xb8];
u32 pex_wdma_ctrl;
u32 pex_wdma_addr;
u32 pex_wdma_stat;
u8 res5[0x94];
u32 pex_rdma_ctrl;
u32 pex_rdma_addr;
u32 pex_rdma_stat;
u8 res6[0xd4];
u32 pex_ombcr;
u32 pex_ombdr;
u8 res7[0x38];
u32 pex_imbcr;
u32 pex_imbdr;
u8 res8[0x38];
u32 pex_int_enb;
u32 pex_int_stat;
u32 pex_int_apio_vec1;
u32 pex_int_apio_vec2;
u8 res9[0x10];
u32 pex_int_ppio_vec1;
u32 pex_int_ppio_vec2;
u32 pex_int_wdma_vec1;
u32 pex_int_wdma_vec2;
u32 pex_int_rdma_vec1;
u32 pex_int_rdma_vec2;
u32 pex_int_misc_vec;
u8 res10[4];
u32 pex_int_axi_pio_enb;
u32 pex_int_axi_wdma_enb;
u32 pex_int_axi_rdma_enb;
u32 pex_int_axi_misc_enb;
u32 pex_int_axi_pio_stat;
u32 pex_int_axi_wdma_stat;
u32 pex_int_axi_rdma_stat;
u32 pex_int_axi_misc_stat;
u8 res11[0xa0];
struct pex_outbound_window pex_outbound_win[4];
u8 res12[0x100];
u32 pex_epiwtar0;
u32 pex_epiwtar1;
u32 pex_epiwtar2;
u32 pex_epiwtar3;
u8 res13[0x70];
struct pex_inbound_window pex_inbound_win[4];
};
typedef struct pex83xx {
u8 pex_cfg_header[0x404];
u32 pex_ltssm_stat;
u8 res0[0x30];
u32 pex_ack_replay_timeout;
u8 res1[4];
u32 pex_gclk_ratio;
u8 res2[0xc];
u32 pex_pm_timer;
u32 pex_pme_timeout;
u8 res3[4];
u32 pex_aspm_req_timer;
u8 res4[0x18];
u32 pex_ssvid_update;
u8 res5[0x34];
u32 pex_cfg_ready;
u8 res6[0x24];
u32 pex_bar_sizel;
u8 res7[4];
u32 pex_bar_sel;
u8 res8[0x20];
u32 pex_bar_pf;
u8 res9[0x88];
u32 pex_pme_to_ack_tor;
u8 res10[0xc];
u32 pex_ss_intr_mask;
u8 res11[0x25c];
struct pex_csb_bridge bridge;
u8 res12[0x160];
} pex83xx_t;
/*
* SATA
*/
typedef struct sata83xx {
u8 fixme[0x1000];
} sata83xx_t;
/*
* eSDHC
*/
typedef struct sdhc83xx {
u8 fixme[0x1000];
} sdhc83xx_t;
/*
* SerDes
*/
typedef struct serdes83xx {
u8 fixme[0x100];
} serdes83xx_t;
/*
* On Chip ROM
*/
typedef struct rom83xx {
u8 mem[0x10000];
} rom83xx_t;
/*
* TDM
*/
typedef struct tdm83xx {
u8 fixme[0x200];
} tdm83xx_t;
/*
* TDM DMAC
*/
typedef struct tdmdmac83xx {
u8 fixme[0x2000];
} tdmdmac83xx_t;
#if defined(CONFIG_MPC834x)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
rtclk83xx_t pit; /* Periodic Interval Timer */
gtm83xx_t gtm[2]; /* Global Timers Module */
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter83xx_t arbiter; /* System Arbiter Registers */
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
gpio83xx_t gpio[2]; /* General purpose I/O module */
u8 res0[0x200];
u8 dll_ddr[0x100];
u8 dll_lbc[0x100];
u8 res1[0xE00];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res2[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res3[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res4[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
u8 res5[0x19900];
usb83xx_t usb[2];
tsec83xx_t tsec[2];
u8 res6[0xA000];
security83xx_t security;
u8 res7[0xC0000];
} immap_t;
#ifdef CONFIG_HAS_FSL_MPH_USB
#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */
#else
#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */
#endif
#elif defined(CONFIG_MPC8313)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
rtclk83xx_t pit; /* Periodic Interval Timer */
gtm83xx_t gtm[2]; /* Global Timers Module */
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter83xx_t arbiter; /* System Arbiter Registers */
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
gpio83xx_t gpio[1]; /* General purpose I/O module */
u8 res0[0x1300];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
u8 res4[0x80];
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
u8 res5[0x1aa00];
usb83xx_t usb[1];
tsec83xx_t tsec[2];
u8 res6[0xA000];
security83xx_t security;
u8 res7[0xC0000];
} immap_t;
#elif defined(CONFIG_MPC8315)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
rtclk83xx_t pit; /* Periodic Interval Timer */
gtm83xx_t gtm[2]; /* Global Timers Module */
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter83xx_t arbiter; /* System Arbiter Registers */
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
gpio83xx_t gpio[1]; /* General purpose I/O module */
u8 res0[0x1300];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
u8 res4[0x80];
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
u8 res5[0xa00];
pex83xx_t pciexp[2]; /* PCI Express Controller */
u8 res6[0xb000];
tdm83xx_t tdm; /* TDM Controller */
u8 res7[0x1e00];
sata83xx_t sata[2]; /* SATA Controller */
u8 res8[0x9000];
usb83xx_t usb[1]; /* USB DR Controller */
tsec83xx_t tsec[2];
u8 res9[0x6000];
tdmdmac83xx_t tdmdmac; /* TDM DMAC */
u8 res10[0x2000];
security83xx_t security;
u8 res11[0xA3000];
serdes83xx_t serdes[1]; /* SerDes Registers */
u8 res12[0x1CF00];
} immap_t;
#elif defined(CONFIG_MPC837x)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
rtclk83xx_t pit; /* Periodic Interval Timer */
gtm83xx_t gtm[2]; /* Global Timers Module */
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter83xx_t arbiter; /* System Arbiter Registers */
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
gpio83xx_t gpio[2]; /* General purpose I/O module */
u8 res0[0x1200];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
u8 res4[0x80];
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
u8 res5[0xa00];
pex83xx_t pciexp[2]; /* PCI Express Controller */
u8 res6[0xd000];
sata83xx_t sata[4]; /* SATA Controller */
u8 res7[0x7000];
usb83xx_t usb[1]; /* USB DR Controller */
tsec83xx_t tsec[2];
u8 res8[0x8000];
sdhc83xx_t sdhc; /* SDHC Controller */
u8 res9[0x1000];
security83xx_t security;
u8 res10[0xA3000];
serdes83xx_t serdes[2]; /* SerDes Registers */
u8 res11[0xCE00];
rom83xx_t rom; /* On Chip ROM */
} immap_t;
#elif defined(CONFIG_MPC8360)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
rtclk83xx_t pit; /* Periodic Interval Timer */
u8 res0[0x200];
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter83xx_t arbiter; /* System Arbiter Registers */
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
qepi83xx_t qepi; /* QE Ports Interrupts Registers */
u8 res1[0x300];
u8 dll_ddr[0x100];
u8 dll_lbc[0x100];
u8 res2[0x200];
qepio83xx_t qepio; /* QE Parallel I/O ports */
qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
u8 res3[0x400];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res4[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res5[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res6[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
u8 res7[128];
ios83xx_t ios; /* Sequencer (IOS) */
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
u8 res8[0x4A00];
ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
u8 res9[0x22000];
security83xx_t security;
u8 res10[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
#elif defined(CONFIG_MPC832x)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
rtclk83xx_t pit; /* Periodic Interval Timer */
gtm83xx_t gtm[2]; /* Global Timers Module */
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter83xx_t arbiter; /* System Arbiter Registers */
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
qepi83xx_t qepi; /* QE Ports Interrupts Registers */
u8 res0[0x300];
u8 dll_ddr[0x100];
u8 dll_lbc[0x100];
u8 res1[0x200];
qepio83xx_t qepio; /* QE Parallel I/O ports */
u8 res2[0x800];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res3[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res4[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res5[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
u8 res6[128];
ios83xx_t ios; /* Sequencer (IOS) */
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
u8 res7[0x27A00];
security83xx_t security;
u8 res8[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
#endif
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
#endif
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
#endif /* __IMMAP_83xx__ */

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/*
* QUICC Engine (QE) Internal Memory Map.
* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
*
* Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
* Author: Shlomi Gridih <gridish@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __IMMAP_QE_H__
#define __IMMAP_QE_H__
/* QE I-RAM
*/
typedef struct qe_iram {
u32 iadd; /* I-RAM Address Register */
u32 idata; /* I-RAM Data Register */
u8 res0[0x4];
u32 iready;
u8 res1[0x70];
} __attribute__ ((packed)) qe_iram_t;
/* QE Interrupt Controller
*/
typedef struct qe_ic {
u32 qicr;
u32 qivec;
u32 qripnr;
u32 qipnr;
u32 qipxcc;
u32 qipycc;
u32 qipwcc;
u32 qipzcc;
u32 qimr;
u32 qrimr;
u32 qicnr;
u8 res0[0x4];
u32 qiprta;
u32 qiprtb;
u8 res1[0x4];
u32 qricr;
u8 res2[0x20];
u32 qhivec;
u8 res3[0x1C];
} __attribute__ ((packed)) qe_ic_t;
/* Communications Processor
*/
typedef struct cp_qe {
u32 cecr; /* QE command register */
u32 ceccr; /* QE controller configuration register */
u32 cecdr; /* QE command data register */
u8 res0[0xA];
u16 ceter; /* QE timer event register */
u8 res1[0x2];
u16 cetmr; /* QE timers mask register */
u32 cetscr; /* QE time-stamp timer control register */
u32 cetsr1; /* QE time-stamp register 1 */
u32 cetsr2; /* QE time-stamp register 2 */
u8 res2[0x8];
u32 cevter; /* QE virtual tasks event register */
u32 cevtmr; /* QE virtual tasks mask register */
u16 cercr; /* QE RAM control register */
u8 res3[0x2];
u8 res4[0x24];
u16 ceexe1; /* QE external request 1 event register */
u8 res5[0x2];
u16 ceexm1; /* QE external request 1 mask register */
u8 res6[0x2];
u16 ceexe2; /* QE external request 2 event register */
u8 res7[0x2];
u16 ceexm2; /* QE external request 2 mask register */
u8 res8[0x2];
u16 ceexe3; /* QE external request 3 event register */
u8 res9[0x2];
u16 ceexm3; /* QE external request 3 mask register */
u8 res10[0x2];
u16 ceexe4; /* QE external request 4 event register */
u8 res11[0x2];
u16 ceexm4; /* QE external request 4 mask register */
u8 res12[0x2];
u8 res13[0x280];
} __attribute__ ((packed)) cp_qe_t;
/* QE Multiplexer
*/
typedef struct qe_mux {
u32 cmxgcr; /* CMX general clock route register */
u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
u32 cmxsi1syr; /* CMX SI1 SYNC route register */
u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
u32 cmxupcr; /* CMX UPC clock route register */
u8 res0[0x1C];
} __attribute__ ((packed)) qe_mux_t;
/* QE Timers
*/
typedef struct qe_timers {
u8 gtcfr1; /* Timer 1 2 global configuration register */
u8 res0[0x3];
u8 gtcfr2; /* Timer 3 4 global configuration register */
u8 res1[0xB];
u16 gtmdr1; /* Timer 1 mode register */
u16 gtmdr2; /* Timer 2 mode register */
u16 gtrfr1; /* Timer 1 reference register */
u16 gtrfr2; /* Timer 2 reference register */
u16 gtcpr1; /* Timer 1 capture register */
u16 gtcpr2; /* Timer 2 capture register */
u16 gtcnr1; /* Timer 1 counter */
u16 gtcnr2; /* Timer 2 counter */
u16 gtmdr3; /* Timer 3 mode register */
u16 gtmdr4; /* Timer 4 mode register */
u16 gtrfr3; /* Timer 3 reference register */
u16 gtrfr4; /* Timer 4 reference register */
u16 gtcpr3; /* Timer 3 capture register */
u16 gtcpr4; /* Timer 4 capture register */
u16 gtcnr3; /* Timer 3 counter */
u16 gtcnr4; /* Timer 4 counter */
u16 gtevr1; /* Timer 1 event register */
u16 gtevr2; /* Timer 2 event register */
u16 gtevr3; /* Timer 3 event register */
u16 gtevr4; /* Timer 4 event register */
u16 gtps; /* Timer 1 prescale register */
u8 res2[0x46];
} __attribute__ ((packed)) qe_timers_t;
/* BRG
*/
typedef struct qe_brg {
u32 brgc1; /* BRG1 configuration register */
u32 brgc2; /* BRG2 configuration register */
u32 brgc3; /* BRG3 configuration register */
u32 brgc4; /* BRG4 configuration register */
u32 brgc5; /* BRG5 configuration register */
u32 brgc6; /* BRG6 configuration register */
u32 brgc7; /* BRG7 configuration register */
u32 brgc8; /* BRG8 configuration register */
u32 brgc9; /* BRG9 configuration register */
u32 brgc10; /* BRG10 configuration register */
u32 brgc11; /* BRG11 configuration register */
u32 brgc12; /* BRG12 configuration register */
u32 brgc13; /* BRG13 configuration register */
u32 brgc14; /* BRG14 configuration register */
u32 brgc15; /* BRG15 configuration register */
u32 brgc16; /* BRG16 configuration register */
u8 res0[0x40];
} __attribute__ ((packed)) qe_brg_t;
/* SPI
*/
typedef struct spi {
u8 res0[0x20];
u32 spmode; /* SPI mode register */
u8 res1[0x2];
u8 spie; /* SPI event register */
u8 res2[0x1];
u8 res3[0x2];
u8 spim; /* SPI mask register */
u8 res4[0x1];
u8 res5[0x1];
u8 spcom; /* SPI command register */
u8 res6[0x2];
u32 spitd; /* SPI transmit data register (cpu mode) */
u32 spird; /* SPI receive data register (cpu mode) */
u8 res7[0x8];
} __attribute__ ((packed)) spi_t;
/* SI
*/
typedef struct si1 {
u16 siamr1; /* SI1 TDMA mode register */
u16 sibmr1; /* SI1 TDMB mode register */
u16 sicmr1; /* SI1 TDMC mode register */
u16 sidmr1; /* SI1 TDMD mode register */
u8 siglmr1_h; /* SI1 global mode register high */
u8 res0[0x1];
u8 sicmdr1_h; /* SI1 command register high */
u8 res2[0x1];
u8 sistr1_h; /* SI1 status register high */
u8 res3[0x1];
u16 sirsr1_h; /* SI1 RAM shadow address register high */
u8 sitarc1; /* SI1 RAM counter Tx TDMA */
u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
u8 sirarc1; /* SI1 RAM counter Rx TDMA */
u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
u8 sircrc1; /* SI1 RAM counter Rx TDMC */
u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
u8 res4[0x8];
u16 siemr1; /* SI1 TDME mode register 16 bits */
u16 sifmr1; /* SI1 TDMF mode register 16 bits */
u16 sigmr1; /* SI1 TDMG mode register 16 bits */
u16 sihmr1; /* SI1 TDMH mode register 16 bits */
u8 siglmg1_l; /* SI1 global mode register low 8 bits */
u8 res5[0x1];
u8 sicmdr1_l; /* SI1 command register low 8 bits */
u8 res6[0x1];
u8 sistr1_l; /* SI1 status register low 8 bits */
u8 res7[0x1];
u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */
u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
u8 res8[0x8];
u32 siml1; /* SI1 multiframe limit register */
u8 siedm1; /* SI1 extended diagnostic mode register */
u8 res9[0xBB];
} __attribute__ ((packed)) si1_t;
/* SI Routing Tables
*/
typedef struct sir {
u8 tx[0x400];
u8 rx[0x400];
u8 res0[0x800];
} __attribute__ ((packed)) sir_t;
/* USB Controller.
*/
typedef struct usb_ctlr {
u8 usb_usmod;
u8 usb_usadr;
u8 usb_uscom;
u8 res1[1];
u16 usb_usep1;
u16 usb_usep2;
u16 usb_usep3;
u16 usb_usep4;
u8 res2[4];
u16 usb_usber;
u8 res3[2];
u16 usb_usbmr;
u8 res4[1];
u8 usb_usbs;
u16 usb_ussft;
u8 res5[2];
u16 usb_usfrn;
u8 res6[0x22];
} __attribute__ ((packed)) usb_t;
/* MCC
*/
typedef struct mcc {
u32 mcce; /* MCC event register */
u32 mccm; /* MCC mask register */
u32 mccf; /* MCC configuration register */
u32 merl; /* MCC emergency request level register */
u8 res0[0xF0];
} __attribute__ ((packed)) mcc_t;
/* QE UCC Slow
*/
typedef struct ucc_slow {
u32 gumr_l; /* UCCx general mode register (low) */
u32 gumr_h; /* UCCx general mode register (high) */
u16 upsmr; /* UCCx protocol-specific mode register */
u8 res0[0x2];
u16 utodr; /* UCCx transmit on demand register */
u16 udsr; /* UCCx data synchronization register */
u16 ucce; /* UCCx event register */
u8 res1[0x2];
u16 uccm; /* UCCx mask register */
u8 res2[0x1];
u8 uccs; /* UCCx status register */
u8 res3[0x24];
u16 utpt;
u8 guemr; /* UCC general extended mode register */
u8 res4[0x200 - 0x091];
} __attribute__ ((packed)) ucc_slow_t;
typedef struct ucc_mii_mng {
u32 miimcfg; /* MII management configuration reg */
u32 miimcom; /* MII management command reg */
u32 miimadd; /* MII management address reg */
u32 miimcon; /* MII management control reg */
u32 miimstat; /* MII management status reg */
u32 miimind; /* MII management indication reg */
u32 ifctl; /* interface control reg */
u32 ifstat; /* interface statux reg */
} __attribute__ ((packed))uec_mii_t;
typedef struct ucc_ethernet {
u32 maccfg1; /* mac configuration reg. 1 */
u32 maccfg2; /* mac configuration reg. 2 */
u32 ipgifg; /* interframe gap reg. */
u32 hafdup; /* half-duplex reg. */
u8 res1[0x10];
u32 miimcfg; /* MII management configuration reg */
u32 miimcom; /* MII management command reg */
u32 miimadd; /* MII management address reg */
u32 miimcon; /* MII management control reg */
u32 miimstat; /* MII management status reg */
u32 miimind; /* MII management indication reg */
u32 ifctl; /* interface control reg */
u32 ifstat; /* interface statux reg */
u32 macstnaddr1; /* mac station address part 1 reg */
u32 macstnaddr2; /* mac station address part 2 reg */
u8 res2[0x8];
u32 uempr; /* UCC Ethernet Mac parameter reg */
u32 utbipar; /* UCC tbi address reg */
u16 uescr; /* UCC Ethernet statistics control reg */
u8 res3[0x180 - 0x15A];
u32 tx64; /* Total number of frames (including bad
* frames) transmitted that were exactly
* of the minimal length (64 for un tagged,
* 68 for tagged, or with length exactly
* equal to the parameter MINLength */
u32 tx127; /* Total number of frames (including bad
* frames) transmitted that were between
* MINLength (Including FCS length==4)
* and 127 octets */
u32 tx255; /* Total number of frames (including bad
* frames) transmitted that were between
* 128 (Including FCS length==4) and 255
* octets */
u32 rx64; /* Total number of frames received including
* bad frames that were exactly of the
* mninimal length (64 bytes) */
u32 rx127; /* Total number of frames (including bad
* frames) received that were between
* MINLength (Including FCS length==4)
* and 127 octets */
u32 rx255; /* Total number of frames (including
* bad frames) received that were between
* 128 (Including FCS length==4) and 255
* octets */
u32 txok; /* Total number of octets residing in frames
* that where involved in succesfull
* transmission */
u16 txcf; /* Total number of PAUSE control frames
* transmitted by this MAC */
u8 res4[0x2];
u32 tmca; /* Total number of frames that were transmitted
* succesfully with the group address bit set
* that are not broadcast frames */
u32 tbca; /* Total number of frames transmitted
* succesfully that had destination address
* field equal to the broadcast address */
u32 rxfok; /* Total number of frames received OK */
u32 rxbok; /* Total number of octets received OK */
u32 rbyt; /* Total number of octets received including
* octets in bad frames. Must be implemented
* in HW because it includes octets in frames
* that never even reach the UCC */
u32 rmca; /* Total number of frames that were received
* succesfully with the group address bit set
* that are not broadcast frames */
u32 rbca; /* Total number of frames received succesfully
* that had destination address equal to the
* broadcast address */
u32 scar; /* Statistics carry register */
u32 scam; /* Statistics caryy mask register */
u8 res5[0x200 - 0x1c4];
} __attribute__ ((packed)) uec_t;
/* QE UCC Fast
*/
typedef struct ucc_fast {
u32 gumr; /* UCCx general mode register */
u32 upsmr; /* UCCx protocol-specific mode register */
u16 utodr; /* UCCx transmit on demand register */
u8 res0[0x2];
u16 udsr; /* UCCx data synchronization register */
u8 res1[0x2];
u32 ucce; /* UCCx event register */
u32 uccm; /* UCCx mask register. */
u8 uccs; /* UCCx status register */
u8 res2[0x7];
u32 urfb; /* UCC receive FIFO base */
u16 urfs; /* UCC receive FIFO size */
u8 res3[0x2];
u16 urfet; /* UCC receive FIFO emergency threshold */
u16 urfset; /* UCC receive FIFO special emergency
* threshold */
u32 utfb; /* UCC transmit FIFO base */
u16 utfs; /* UCC transmit FIFO size */
u8 res4[0x2];
u16 utfet; /* UCC transmit FIFO emergency threshold */
u8 res5[0x2];
u16 utftt; /* UCC transmit FIFO transmit threshold */
u8 res6[0x2];
u16 utpt; /* UCC transmit polling timer */
u8 res7[0x2];
u32 urtry; /* UCC retry counter register */
u8 res8[0x4C];
u8 guemr; /* UCC general extended mode register */
u8 res9[0x100 - 0x091];
uec_t ucc_eth;
} __attribute__ ((packed)) ucc_fast_t;
/* QE UCC
*/
typedef struct ucc_common {
u8 res1[0x90];
u8 guemr;
u8 res2[0x200 - 0x091];
} __attribute__ ((packed)) ucc_common_t;
typedef struct ucc {
union {
ucc_slow_t slow;
ucc_fast_t fast;
ucc_common_t common;
};
} __attribute__ ((packed)) ucc_t;
/* MultiPHY UTOPIA POS Controllers (UPC)
*/
typedef struct upc {
u32 upgcr; /* UTOPIA/POS general configuration register */
u32 uplpa; /* UTOPIA/POS last PHY address */
u32 uphec; /* ATM HEC register */
u32 upuc; /* UTOPIA/POS UCC configuration */
u32 updc1; /* UTOPIA/POS device 1 configuration */
u32 updc2; /* UTOPIA/POS device 2 configuration */
u32 updc3; /* UTOPIA/POS device 3 configuration */
u32 updc4; /* UTOPIA/POS device 4 configuration */
u32 upstpa; /* UTOPIA/POS STPA threshold */
u8 res0[0xC];
u32 updrs1_h; /* UTOPIA/POS device 1 rate select */
u32 updrs1_l; /* UTOPIA/POS device 1 rate select */
u32 updrs2_h; /* UTOPIA/POS device 2 rate select */
u32 updrs2_l; /* UTOPIA/POS device 2 rate select */
u32 updrs3_h; /* UTOPIA/POS device 3 rate select */
u32 updrs3_l; /* UTOPIA/POS device 3 rate select */
u32 updrs4_h; /* UTOPIA/POS device 4 rate select */
u32 updrs4_l; /* UTOPIA/POS device 4 rate select */
u32 updrp1; /* UTOPIA/POS device 1 receive priority low */
u32 updrp2; /* UTOPIA/POS device 2 receive priority low */
u32 updrp3; /* UTOPIA/POS device 3 receive priority low */
u32 updrp4; /* UTOPIA/POS device 4 receive priority low */
u32 upde1; /* UTOPIA/POS device 1 event */
u32 upde2; /* UTOPIA/POS device 2 event */
u32 upde3; /* UTOPIA/POS device 3 event */
u32 upde4; /* UTOPIA/POS device 4 event */
u16 uprp1;
u16 uprp2;
u16 uprp3;
u16 uprp4;
u8 res1[0x8];
u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
u16 uptirr4_3; /* Device 4 transmit internal rate 3 */
u32 uper1; /* Device 1 port enable register */
u32 uper2; /* Device 2 port enable register */
u32 uper3; /* Device 3 port enable register */
u32 uper4; /* Device 4 port enable register */
u8 res2[0x150];
} __attribute__ ((packed)) upc_t;
/* SDMA
*/
typedef struct sdma {
u32 sdsr; /* Serial DMA status register */
u32 sdmr; /* Serial DMA mode register */
u32 sdtr1; /* SDMA system bus threshold register */
u32 sdtr2; /* SDMA secondary bus threshold register */
u32 sdhy1; /* SDMA system bus hysteresis register */
u32 sdhy2; /* SDMA secondary bus hysteresis register */
u32 sdta1; /* SDMA system bus address register */
u32 sdta2; /* SDMA secondary bus address register */
u32 sdtm1; /* SDMA system bus MSNUM register */
u32 sdtm2; /* SDMA secondary bus MSNUM register */
u8 res0[0x10];
u32 sdaqr; /* SDMA address bus qualify register */
u32 sdaqmr; /* SDMA address bus qualify mask register */
u8 res1[0x4];
u32 sdwbcr; /* SDMA CAM entries base register */
u8 res2[0x38];
} __attribute__ ((packed)) sdma_t;
/* Debug Space
*/
typedef struct dbg {
u32 bpdcr; /* Breakpoint debug command register */
u32 bpdsr; /* Breakpoint debug status register */
u32 bpdmr; /* Breakpoint debug mask register */
u32 bprmrr0; /* Breakpoint request mode risc register 0 */
u32 bprmrr1; /* Breakpoint request mode risc register 1 */
u8 res0[0x8];
u32 bprmtr0; /* Breakpoint request mode trb register 0 */
u32 bprmtr1; /* Breakpoint request mode trb register 1 */
u8 res1[0x8];
u32 bprmir; /* Breakpoint request mode immediate register */
u32 bprmsr; /* Breakpoint request mode serial register */
u32 bpemr; /* Breakpoint exit mode register */
u8 res2[0x48];
} __attribute__ ((packed)) dbg_t;
/*
* RISC Special Registers (Trap and Breakpoint). These are described in
* the QE Developer's Handbook.
*/
typedef struct rsp {
u32 tibcr[16]; /* Trap/instruction breakpoint control regs */
u8 res0[64];
u32 ibcr0;
u32 ibs0;
u32 ibcnr0;
u8 res1[4];
u32 ibcr1;
u32 ibs1;
u32 ibcnr1;
u32 npcr;
u32 dbcr;
u32 dbar;
u32 dbamr;
u32 dbsr;
u32 dbcnr;
u8 res2[12];
u32 dbdr_h;
u32 dbdr_l;
u32 dbdmr_h;
u32 dbdmr_l;
u32 bsr;
u32 bor;
u32 bior;
u8 res3[4];
u32 iatr[4];
u32 eccr; /* Exception control configuration register */
u32 eicr;
u8 res4[0x100-0xf8];
} __attribute__ ((packed)) rsp_t;
typedef struct qe_immap {
qe_iram_t iram; /* I-RAM */
qe_ic_t ic; /* Interrupt Controller */
cp_qe_t cp; /* Communications Processor */
qe_mux_t qmx; /* QE Multiplexer */
qe_timers_t qet; /* QE Timers */
spi_t spi[0x2]; /* spi */
mcc_t mcc; /* mcc */
qe_brg_t brg; /* brg */
usb_t usb; /* USB */
si1_t si1; /* SI */
u8 res11[0x800];
sir_t sir; /* SI Routing Tables */
ucc_t ucc1; /* ucc1 */
ucc_t ucc3; /* ucc3 */
ucc_t ucc5; /* ucc5 */
ucc_t ucc7; /* ucc7 */
u8 res12[0x600];
upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
ucc_t ucc2; /* ucc2 */
ucc_t ucc4; /* ucc4 */
ucc_t ucc6; /* ucc6 */
ucc_t ucc8; /* ucc8 */
u8 res13[0x600];
upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
sdma_t sdma; /* SDMA */
dbg_t dbg; /* Debug Space */
rsp_t rsp[0x2]; /* RISC Special Registers
* (Trap and Breakpoint) */
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
#if defined(CONFIG_MPC8568)
u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
#elif defined(CONFIG_MPC8569)
u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */
u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */
#else
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
#endif
} __attribute__ ((packed)) qe_map_t;
extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8568)
#define QE_MURAM_SIZE 0x10000UL
#elif defined(CONFIG_MPC8569)
#define QE_MURAM_SIZE 0x20000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832x)
#define QE_MURAM_SIZE 0x4000UL
#endif
#if defined(CONFIG_MPC8323)
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC8569)
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
#else
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
#endif
#endif /* __IMMAP_QE_H__ */

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arch/powerpc/include/asm/interrupt.h Normal file
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/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef INTERRUPT_H
#define INTERRUPT_H
#if defined(CONFIG_XILINX_440)
#include <asm/xilinx_irq.h>
#else
#include <asm/ppc4xx-uic.h>
#endif
void pic_enable(void);
void pic_irq_enable(unsigned int irq);
void pic_irq_disable(unsigned int irq);
void pic_irq_ack(unsigned int irq);
void external_interrupt(struct pt_regs *regs);
void interrupt_run_handler(int vec);
#endif

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arch/powerpc/include/asm/io.h Normal file
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/* originally from linux source.
* removed the dependencies on CONFIG_ values
* removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
* Modified By Rob Taylor, Flying Pig Systems, 2000
*/
#ifndef _PPC_IO_H
#define _PPC_IO_H
#include <linux/config.h>
#include <asm/byteorder.h>
#ifdef CONFIG_ADDR_MAP
#include <addr_map.h>
#endif
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
#ifndef _IO_BASE
#define _IO_BASE 0
#endif
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
#if !defined(__BIG_ENDIAN)
#define readw(addr) (*(volatile u16 *) (addr))
#define readl(addr) (*(volatile u32 *) (addr))
#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
#else
#define readw(addr) in_le16((volatile u16 *)(addr))
#define readl(addr) in_le32((volatile u32 *)(addr))
#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
#endif
/*
* The insw/outsw/insl/outsl macros don't do byte-swapping.
* They are only used in practice for transferring buffers which
* are arrays of bytes, and byte-swapping is not appropriate in
* that case. - paulus
*/
#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define inb(port) in_8((u8 *)((port)+_IO_BASE))
#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
#if !defined(__BIG_ENDIAN)
#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
#else
#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
#endif
#define inb_p(port) in_8((u8 *)((port)+_IO_BASE))
#define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
#define inw_p(port) in_le16((u16 *)((port)+_IO_BASE))
#define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
#define inl_p(port) in_le32((u32 *)((port)+_IO_BASE))
#define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
extern void _insb(volatile u8 *port, void *buf, int ns);
extern void _outsb(volatile u8 *port, const void *buf, int ns);
extern void _insw(volatile u16 *port, void *buf, int ns);
extern void _outsw(volatile u16 *port, const void *buf, int ns);
extern void _insl(volatile u32 *port, void *buf, int nl);
extern void _outsl(volatile u32 *port, const void *buf, int nl);
extern void _insw_ns(volatile u16 *port, void *buf, int ns);
extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
extern void _insl_ns(volatile u32 *port, void *buf, int nl);
extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
/*
* The *_ns versions below don't do byte-swapping.
* Neither do the standard versions now, these are just here
* for older code.
*/
#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define IO_SPACE_LIMIT ~0
#define memset_io(a,b,c) memset((void *)(a),(b),(c))
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
/*
* Enforce In-order Execution of I/O:
* Acts as a barrier to ensure all previous I/O accesses have
* completed before any further ones are issued.
*/
static inline void eieio(void)
{
__asm__ __volatile__ ("eieio" : : : "memory");
}
static inline void sync(void)
{
__asm__ __volatile__ ("sync" : : : "memory");
}
static inline void isync(void)
{
__asm__ __volatile__ ("isync" : : : "memory");
}
/* Enforce in-order execution of data I/O.
* No distinction between read/write on PPC; use eieio for all three.
*/
#define iobarrier_rw() eieio()
#define iobarrier_r() eieio()
#define iobarrier_w() eieio()
/*
* Non ordered and non-swapping "raw" accessors
*/
#define __iomem
#define PCI_FIX_ADDR(addr) (addr)
static inline unsigned char __raw_readb(const volatile void __iomem *addr)
{
return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
}
static inline unsigned short __raw_readw(const volatile void __iomem *addr)
{
return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
}
static inline unsigned int __raw_readl(const volatile void __iomem *addr)
{
return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
}
static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
{
*(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
}
static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
{
*(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
}
static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
{
*(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
}
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*
* Read operations have additional twi & isync to make sure the read
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
extern inline int in_8(const volatile unsigned char __iomem *addr)
{
int ret;
__asm__ __volatile__(
"sync; lbz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_8(volatile unsigned char __iomem *addr, int val)
{
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}
extern inline int in_le16(const volatile unsigned short __iomem *addr)
{
int ret;
__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
extern inline int in_be16(const volatile unsigned short __iomem *addr)
{
int ret;
__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
{
__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
"r" (val), "r" (addr));
}
extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
{
__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
{
unsigned ret;
__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
{
unsigned ret;
__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_le32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
"r" (val), "r" (addr));
}
extern inline void out_be32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
/* Clear and set bits in one shot. These macros can be used to clear and
* set multiple bits in a register using a single call. These macros can
* also be used to set a multiple-bit bit pattern using a mask, by
* specifying the mask in the 'clear' parameter and the new bit pattern
* in the 'set' parameter.
*/
#define clrbits(type, addr, clear) \
out_##type((addr), in_##type(addr) & ~(clear))
#define setbits(type, addr, set) \
out_##type((addr), in_##type(addr) | (set))
#define clrsetbits(type, addr, clear, set) \
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
#define setbits_be32(addr, set) setbits(be32, addr, set)
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
#ifdef CONFIG_ADDR_MAP
return (void *)(addrmap_phys_to_virt(paddr));
#else
return (void *)((unsigned long)paddr);
#endif
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
static inline phys_addr_t virt_to_phys(void * vaddr)
{
#ifdef CONFIG_ADDR_MAP
return addrmap_virt_to_phys(vaddr);
#else
return (phys_addr_t)((unsigned long)vaddr);
#endif
}
#endif

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/*
* MPC8260 I/O port pin manipulation functions
*/
#ifndef _ASM_IOPIN_8260_H_
#define _ASM_IOPIN_8260_H_
#include <linux/types.h>
#include <asm/immap_8260.h>
#ifdef __KERNEL__
typedef
struct {
u_char port:2; /* port number (A=0, B=1, C=2, D=3) */
u_char pin:5; /* port pin (0-31) */
u_char flag:1; /* for whatever */
}
iopin_t;
#define IOPIN_PORTA 0
#define IOPIN_PORTB 1
#define IOPIN_PORTC 2
#define IOPIN_PORTD 3
extern __inline__ void
iopin_set_high(iopin_t *iopin)
{
volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_low(iopin_t *iopin)
{
volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_high(iopin_t *iopin)
{
volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_low(iopin_t *iopin)
{
volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void
iopin_set_out(iopin_t *iopin)
{
volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_in(iopin_t *iopin)
{
volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_out(iopin_t *iopin)
{
volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_in(iopin_t *iopin)
{
volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void
iopin_set_odr(iopin_t *iopin)
{
volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_act(iopin_t *iopin)
{
volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_odr(iopin_t *iopin)
{
volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_act(iopin_t *iopin)
{
volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void
iopin_set_ded(iopin_t *iopin)
{
volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_gen(iopin_t *iopin)
{
volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_ded(iopin_t *iopin)
{
volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_gen(iopin_t *iopin)
{
volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void
iopin_set_opt2(iopin_t *iopin)
{
volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_opt1(iopin_t *iopin)
{
volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_opt2(iopin_t *iopin)
{
volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_opt1(iopin_t *iopin)
{
volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
#endif /* __KERNEL__ */
#endif /* _ASM_IOPIN_8260_H_ */

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/*
* MPC85xx I/O port pin manipulation functions
*/
#ifndef _ASM_IOPIN_85xx_H_
#define _ASM_IOPIN_85xx_H_
#include <linux/types.h>
#include <asm/immap_85xx.h>
#ifdef __KERNEL__
typedef struct {
u_char port:2; /* port number (A=0, B=1, C=2, D=3) */
u_char pin:5; /* port pin (0-31) */
u_char flag:1; /* for whatever */
} iopin_t;
#define IOPIN_PORTA 0
#define IOPIN_PORTB 1
#define IOPIN_PORTC 2
#define IOPIN_PORTD 3
extern __inline__ void iopin_set_high (iopin_t * iopin)
{
volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_low (iopin_t * iopin)
{
volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_high (iopin_t * iopin)
{
volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_low (iopin_t * iopin)
{
volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_out (iopin_t * iopin)
{
volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_in (iopin_t * iopin)
{
volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_out (iopin_t * iopin)
{
volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_in (iopin_t * iopin)
{
volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_odr (iopin_t * iopin)
{
volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_act (iopin_t * iopin)
{
volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_odr (iopin_t * iopin)
{
volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_act (iopin_t * iopin)
{
volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_ded (iopin_t * iopin)
{
volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_gen (iopin_t * iopin)
{
volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_ded (iopin_t * iopin)
{
volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_gen (iopin_t * iopin)
{
volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
{
volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
{
volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
{
volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
{
volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
#endif /* __KERNEL__ */
#endif /* _ASM_IOPIN_85xx_H_ */

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/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* MPC8xx I/O port pin manipulation functions
* Roughly based on iopin_8260.h
*/
#ifndef _ASM_IOPIN_8XX_H_
#define _ASM_IOPIN_8XX_H_
#include <linux/types.h>
#include <asm/8xx_immap.h>
#ifdef __KERNEL__
typedef struct {
u_char port:2; /* port number (A=0, B=1, C=2, D=3) */
u_char pin:5; /* port pin (0-31) */
u_char flag:1; /* for whatever */
} iopin_t;
#define IOPIN_PORTA 0
#define IOPIN_PORTB 1
#define IOPIN_PORTC 2
#define IOPIN_PORTD 3
extern __inline__ void
iopin_set_high(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
*datp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
*datp |= (1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
*datp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
*datp |= (1 << (15 - iopin->pin));
}
}
extern __inline__ void
iopin_set_low(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
*datp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
*datp &= ~(1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
*datp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
*datp &= ~(1 << (15 - iopin->pin));
}
}
extern __inline__ uint
iopin_is_high(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
return (*datp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
return (*datp >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
return (*datp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
return (*datp >> (15 - iopin->pin)) & 1;
}
return 0;
}
extern __inline__ uint
iopin_is_low(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
return ((*datp >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
extern __inline__ void
iopin_set_out(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
*dirp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
*dirp |= (1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
*dirp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
*dirp |= (1 << (15 - iopin->pin));
}
}
extern __inline__ void
iopin_set_in(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
*dirp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
*dirp &= ~(1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
*dirp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
*dirp &= ~(1 << (15 - iopin->pin));
}
}
extern __inline__ uint
iopin_is_out(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
return (*dirp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
return (*dirp >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
return (*dirp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
return (*dirp >> (15 - iopin->pin)) & 1;
}
return 0;
}
extern __inline__ uint
iopin_is_in(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
extern __inline__ void
iopin_set_odr(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
*odrp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
*odrp |= (1 << (31 - iopin->pin));
}
}
extern __inline__ void
iopin_set_act(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
*odrp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
*odrp &= ~(1 << (31 - iopin->pin));
}
}
extern __inline__ uint
iopin_is_odr(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
return (*odrp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
return (*odrp >> (31 - iopin->pin)) & 1;
}
return 0;
}
extern __inline__ uint
iopin_is_act(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
extern __inline__ void
iopin_set_ded(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
*parp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
*parp |= (1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
*parp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
*parp |= (1 << (15 - iopin->pin));
}
}
extern __inline__ void
iopin_set_gen(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
*parp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
*parp &= ~(1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
*parp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
*parp &= ~(1 << (15 - iopin->pin));
}
}
extern __inline__ uint
iopin_is_ded(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
return (*parp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
return (*parp >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
return (*parp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
return (*parp >> (15 - iopin->pin)) & 1;
}
return 0;
}
extern __inline__ uint
iopin_is_gen(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
return ((*parp >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
extern __inline__ void
iopin_set_opt2(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
*sorp |= (1 << (15 - iopin->pin));
}
}
extern __inline__ void
iopin_set_opt1(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
*sorp &= ~(1 << (15 - iopin->pin));
}
}
extern __inline__ uint
iopin_is_opt2(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
return (*sorp >> (15 - iopin->pin)) & 1;
}
return 0;
}
extern __inline__ uint
iopin_is_opt1(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
extern __inline__ void
iopin_set_falledge(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
*intp |= (1 << (15 - iopin->pin));
}
}
extern __inline__ void
iopin_set_anyedge(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
*intp &= ~(1 << (15 - iopin->pin));
}
}
extern __inline__ uint
iopin_is_falledge(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
return (*intp >> (15 - iopin->pin)) & 1;
}
return 0;
}
extern __inline__ uint
iopin_is_anyedge(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
return ((*intp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
#endif /* __KERNEL__ */
#endif /* _ASM_IOPIN_8XX_H_ */

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arch/powerpc/include/asm/m8260_pci.h Normal file
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#ifndef _PPC_KERNEL_M8260_PCI_H
#define _PPC_KERNEL_M8260_PCI_H
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
#define M8265_PCIMSK0 0x101c4
#define M8265_PCIMSK1 0x101c8
/* Bit definitions for PCIBR registers */
#define PCIBR_ENABLE 0x00000001
/* Bit definitions for PCIMSK registers */
#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
#define PCIMSK_64KB 0xFFFF0000
#define PCIMSK_128KB 0xFFFE0000
#define PCIMSK_256KB 0xFFFC0000
#define PCIMSK_512KB 0xFFF80000
#define PCIMSK_1MB 0xFFF00000
#define PCIMSK_2MB 0xFFE00000
#define PCIMSK_4MB 0xFFC00000
#define PCIMSK_8MB 0xFF800000
#define PCIMSK_16MB 0xFF000000
#define PCIMSK_32MB 0xFE000000
#define PCIMSK_64MB 0xFC000000
#define PCIMSK_128MB 0xF8000000
#define PCIMSK_256MB 0xF0000000
#define PCIMSK_512MB 0xE0000000
#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */
#define M826X_SCCR_PCI_MODE_EN 0x100
/*
* Outbound ATU registers (3 sets). These registers control how 60x bus (local)
* addresses are translated to PCI addresses when the MPC826x is a PCI bus
* master (initiator).
*/
#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
#define POTAR_REG1 0x10818
#define POTAR_REG2 0x10830
#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
#define POBAR_REG1 0x10820
#define POBAR_REG2 0x10838
#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
#define POCMR_REG1 0x10828
#define POCMR_REG2 0x10840
/* Bit definitions for POMCR registers */
#define POCMR_MASK_4KB 0x000FFFFF
#define POCMR_MASK_8KB 0x000FFFFE
#define POCMR_MASK_16KB 0x000FFFFC
#define POCMR_MASK_32KB 0x000FFFF8
#define POCMR_MASK_64KB 0x000FFFF0
#define POCMR_MASK_128KB 0x000FFFE0
#define POCMR_MASK_256KB 0x000FFFC0
#define POCMR_MASK_512KB 0x000FFF80
#define POCMR_MASK_1MB 0x000FFF00
#define POCMR_MASK_2MB 0x000FFE00
#define POCMR_MASK_4MB 0x000FFC00
#define POCMR_MASK_8MB 0x000FF800
#define POCMR_MASK_16MB 0x000FF000
#define POCMR_MASK_32MB 0x000FE000
#define POCMR_MASK_64MB 0x000FC000
#define POCMR_MASK_128MB 0x000F8000
#define POCMR_MASK_256MB 0x000F0000
#define POCMR_MASK_512MB 0x000E0000
#define POCMR_MASK_1GB 0x000C0000
#define POCMR_ENABLE 0x80000000
#define POCMR_PCI_IO 0x40000000
#define POCMR_PREFETCH_EN 0x20000000
/* Soft PCI reset */
#define PCI_GCR_REG 0x10880
/* Bit definitions for PCI_GCR registers */
#define PCIGCR_PCI_BUS_EN 0x1
/*
* Inbound ATU registers (2 sets). These registers control how PCI addresses
* are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
*/
#define PITAR_REG1 0x108D0
#define PIBAR_REG1 0x108D8
#define PICMR_REG1 0x108E0
#define PITAR_REG0 0x108E8
#define PIBAR_REG0 0x108F0
#define PICMR_REG0 0x108F8
/* Bit definitions for PCI Inbound Comparison Mask registers */
#define PICMR_MASK_4KB 0x000FFFFF
#define PICMR_MASK_8KB 0x000FFFFE
#define PICMR_MASK_16KB 0x000FFFFC
#define PICMR_MASK_32KB 0x000FFFF8
#define PICMR_MASK_64KB 0x000FFFF0
#define PICMR_MASK_128KB 0x000FFFE0
#define PICMR_MASK_256KB 0x000FFFC0
#define PICMR_MASK_512KB 0x000FFF80
#define PICMR_MASK_1MB 0x000FFF00
#define PICMR_MASK_2MB 0x000FFE00
#define PICMR_MASK_4MB 0x000FFC00
#define PICMR_MASK_8MB 0x000FF800
#define PICMR_MASK_16MB 0x000FF000
#define PICMR_MASK_32MB 0x000FE000
#define PICMR_MASK_64MB 0x000FC000
#define PICMR_MASK_128MB 0x000F8000
#define PICMR_MASK_256MB 0x000F0000
#define PICMR_MASK_512MB 0x000E0000
#define PICMR_MASK_1GB 0x000C0000
#define PICMR_ENABLE 0x80000000
#define PICMR_NO_SNOOP_EN 0x40000000
#define PICMR_PREFETCH_EN 0x20000000
/* PCI error Registers */
#define PCI_ERROR_STATUS_REG 0x10884
#define PCI_ERROR_MASK_REG 0x10888
#define PCI_ERROR_CONTROL_REG 0x1088C
#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
/* PCI error Register bit defines */
#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
#define PCI_ERROR_PCI_NO_RSP 0x00000008
#define PCI_ERROR_PCI_TAR_ABT 0x00000010
#define PCI_ERROR_PCI_SERR 0x00000020
#define PCI_ERROR_PCI_PERR_RD 0x00000040
#define PCI_ERROR_PCI_PERR_WR 0x00000080
#define PCI_ERROR_I2O_OFQO 0x00000100
#define PCI_ERROR_I2O_IPQO 0x00000200
#define PCI_ERROR_IRA 0x00000400
#define PCI_ERROR_NMI 0x00000800
#define PCI_ERROR_I2O_DBMC 0x00001000
/*
* Register pair used to generate configuration cycles on the PCI bus
* and access the MPC826x's own PCI configuration registers.
*/
#define PCI_CFG_ADDR_REG 0x10900
#define PCI_CFG_DATA_REG 0x10904
/* Bus parking decides where the bus control sits when idle */
/* If modifying memory controllers for PCI park on the core */
#define PPC_ACR_BUS_PARK_CORE 0x6
#define PPC_ACR_BUS_PARK_PCI 0x3
#endif /* _PPC_KERNEL_M8260_PCI_H */

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arch/powerpc/include/asm/mc146818rtc.h Normal file
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/*
* Machine dependent access functions for RTC registers.
*/
#ifndef __ASM_PPC_MC146818RTC_H
#define __ASM_PPC_MC146818RTC_H
#include <asm/io.h>
#ifndef RTC_PORT
#define RTC_PORT(x) (0x70 + (x))
#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
#endif
/*
* The yet supported machines all access the RTC index register via
* an ISA port access but the way to access the date register differs ...
*/
#define CMOS_READ(addr) ({ \
outb_p((addr),RTC_PORT(0)); \
inb_p(RTC_PORT(1)); \
})
#define CMOS_WRITE(val, addr) ({ \
outb_p((addr),RTC_PORT(0)); \
outb_p((val),RTC_PORT(1)); \
})
#endif /* __ASM_PPC_MC146818RTC_H */

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arch/powerpc/include/asm/mmu.h Normal file
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/*
* PowerPC memory management structures
*/
#ifndef _PPC_MMU_H_
#define _PPC_MMU_H_
#include <linux/config.h>
#ifndef __ASSEMBLY__
/* Hardware Page Table Entry */
typedef struct _PTE {
#ifdef CONFIG_PPC64BRIDGE
unsigned long long vsid:52;
unsigned long api:5;
unsigned long :5;
unsigned long h:1;
unsigned long v:1;
unsigned long long rpn:52;
#else /* CONFIG_PPC64BRIDGE */
unsigned long v:1; /* Entry is valid */
unsigned long vsid:24; /* Virtual segment identifier */
unsigned long h:1; /* Hash algorithm indicator */
unsigned long api:6; /* Abbreviated page index */
unsigned long rpn:20; /* Real (physical) page number */
#endif /* CONFIG_PPC64BRIDGE */
unsigned long :3; /* Unused */
unsigned long r:1; /* Referenced */
unsigned long c:1; /* Changed */
unsigned long w:1; /* Write-thru cache mode */
unsigned long i:1; /* Cache inhibited */
unsigned long m:1; /* Memory coherence */
unsigned long g:1; /* Guarded */
unsigned long :1; /* Unused */
unsigned long pp:2; /* Page protection */
} PTE;
/* Values for PP (assumes Ks=0, Kp=1) */
#define PP_RWXX 0 /* Supervisor read/write, User none */
#define PP_RWRX 1 /* Supervisor read/write, User read */
#define PP_RWRW 2 /* Supervisor read/write, User read/write */
#define PP_RXRX 3 /* Supervisor read, User read */
/* Segment Register */
typedef struct _SEGREG {
unsigned long t:1; /* Normal or I/O type */
unsigned long ks:1; /* Supervisor 'key' (normally 0) */
unsigned long kp:1; /* User 'key' (normally 1) */
unsigned long n:1; /* No-execute */
unsigned long :4; /* Unused */
unsigned long vsid:24; /* Virtual Segment Identifier */
} SEGREG;
/* Block Address Translation (BAT) Registers */
typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
unsigned long bepi:15; /* Effective page index (virtual address) */
unsigned long :8; /* unused */
unsigned long w:1;
unsigned long i:1; /* Cache inhibit */
unsigned long m:1; /* Memory coherence */
unsigned long ks:1; /* Supervisor key (normally 0) */
unsigned long kp:1; /* User key (normally 1) */
unsigned long pp:2; /* Page access protections */
} P601_BATU;
typedef struct _BATU { /* Upper part of BAT (all except 601) */
#ifdef CONFIG_PPC64BRIDGE
unsigned long long bepi:47;
#else /* CONFIG_PPC64BRIDGE */
unsigned long bepi:15; /* Effective page index (virtual address) */
#endif /* CONFIG_PPC64BRIDGE */
unsigned long :4; /* Unused */
unsigned long bl:11; /* Block size mask */
unsigned long vs:1; /* Supervisor valid */
unsigned long vp:1; /* User valid */
} BATU;
typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
unsigned long brpn:15; /* Real page index (physical address) */
unsigned long :10; /* Unused */
unsigned long v:1; /* Valid bit */
unsigned long bl:6; /* Block size mask */
} P601_BATL;
typedef struct _BATL { /* Lower part of BAT (all except 601) */
#ifdef CONFIG_PPC64BRIDGE
unsigned long long brpn:47;
#else /* CONFIG_PPC64BRIDGE */
unsigned long brpn:15; /* Real page index (physical address) */
#endif /* CONFIG_PPC64BRIDGE */
unsigned long :10; /* Unused */
unsigned long w:1; /* Write-thru cache */
unsigned long i:1; /* Cache inhibit */
unsigned long m:1; /* Memory coherence */
unsigned long g:1; /* Guarded (MBZ in IBAT) */
unsigned long :1; /* Unused */
unsigned long pp:2; /* Page access protections */
} BATL;
typedef struct _BAT {
BATU batu; /* Upper register */
BATL batl; /* Lower register */
} BAT;
typedef struct _P601_BAT {
P601_BATU batu; /* Upper register */
P601_BATL batl; /* Lower register */
} P601_BAT;
/*
* Simulated two-level MMU. This structure is used by the kernel
* to keep track of MMU mappings and is used to update/maintain
* the hardware HASH table which is really a cache of mappings.
*
* The simulated structures mimic the hardware available on other
* platforms, notably the 80x86 and 680x0.
*/
typedef struct _pte {
unsigned long page_num:20;
unsigned long flags:12; /* Page flags (some unused bits) */
} pte;
#define PD_SHIFT (10+12) /* Page directory */
#define PD_MASK 0x02FF
#define PT_SHIFT (12) /* Page Table */
#define PT_MASK 0x02FF
#define PG_SHIFT (12) /* Page Entry */
/* MMU context */
typedef struct _MMU_context {
SEGREG segs[16]; /* Segment registers */
pte **pmap; /* Two-level page-map structure */
} MMU_context;
extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
extern void _tlbia(void); /* invalidate all TLB entries */
#ifdef CONFIG_ADDR_MAP
extern void init_addr_map(void);
#endif
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3,
#ifdef CONFIG_HIGH_BATS
IBAT4, IBAT5, IBAT6, IBAT7,
DBAT4, DBAT5, DBAT6, DBAT7
#endif
} ppc_bat_t;
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
extern void print_bats(void);
#endif /* __ASSEMBLY__ */
#define BATU_VS 0x00000002
#define BATU_VP 0x00000001
#define BATU_INVALID 0x00000000
#define BATL_WRITETHROUGH 0x00000040
#define BATL_CACHEINHIBIT 0x00000020
#define BATL_MEMCOHERENCE 0x00000010
#define BATL_GUARDEDSTORAGE 0x00000008
#define BATL_NO_ACCESS 0x00000000
#define BATL_PP_MSK 0x00000003
#define BATL_PP_00 0x00000000 /* No access */
#define BATL_PP_01 0x00000001 /* Read-only */
#define BATL_PP_10 0x00000002 /* Read-write */
#define BATL_PP_11 0x00000003
#define BATL_PP_NO_ACCESS BATL_PP_00
#define BATL_PP_RO BATL_PP_01
#define BATL_PP_RW BATL_PP_10
/* BAT Block size values */
#define BATU_BL_128K 0x00000000
#define BATU_BL_256K 0x00000004
#define BATU_BL_512K 0x0000000c
#define BATU_BL_1M 0x0000001c
#define BATU_BL_2M 0x0000003c
#define BATU_BL_4M 0x0000007c
#define BATU_BL_8M 0x000000fc
#define BATU_BL_16M 0x000001fc
#define BATU_BL_32M 0x000003fc
#define BATU_BL_64M 0x000007fc
#define BATU_BL_128M 0x00000ffc
#define BATU_BL_256M 0x00001ffc
/* Block lengths for processors that support extended block length */
#ifdef HID0_XBSEN
#define BATU_BL_512M 0x00003ffc
#define BATU_BL_1G 0x00007ffc
#define BATU_BL_2G 0x0000fffc
#define BATU_BL_4G 0x0001fffc
#define BATU_BL_MAX BATU_BL_4G
#else
#define BATU_BL_MAX BATU_BL_256M
#endif
/* BAT Access Protection */
#define BPP_XX 0x00 /* No access */
#define BPP_RX 0x01 /* Read only */
#define BPP_RW 0x02 /* Read/write */
/* Macros to get values from BATs, once data is in the BAT register format */
#define BATU_VALID(x) (x & 0x3)
#define BATU_VADDR(x) (x & 0xfffe0000)
#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
| ((x & 0x0e00ULL) << 24) \
| ((x & 0x04ULL) << 30)))
#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17))
/* bytes into BATU_BL */
#define TO_BATU_BL(x) \
(u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
/* Used to set up SDR1 register */
#define HASH_TABLE_SIZE_64K 0x00010000
#define HASH_TABLE_SIZE_128K 0x00020000
#define HASH_TABLE_SIZE_256K 0x00040000
#define HASH_TABLE_SIZE_512K 0x00080000
#define HASH_TABLE_SIZE_1M 0x00100000
#define HASH_TABLE_SIZE_2M 0x00200000
#define HASH_TABLE_SIZE_4M 0x00400000
#define HASH_TABLE_MASK_64K 0x000
#define HASH_TABLE_MASK_128K 0x001
#define HASH_TABLE_MASK_256K 0x003
#define HASH_TABLE_MASK_512K 0x007
#define HASH_TABLE_MASK_1M 0x00F
#define HASH_TABLE_MASK_2M 0x01F
#define HASH_TABLE_MASK_4M 0x03F
/* Control/status registers for the MPC8xx.
* A write operation to these registers causes serialized access.
* During software tablewalk, the registers used perform mask/shift-add
* operations when written/read. A TLB entry is created when the Mx_RPN
* is written, and the contents of several registers are used to
* create the entry.
*/
#define MI_CTR 784 /* Instruction TLB control register */
#define MI_GPM 0x80000000 /* Set domain manager mode */
#define MI_PPM 0x40000000 /* Set subpage protection */
#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
#define MI_RESETVAL 0x00000000 /* Value of register at reset */
/* These are the Ks and Kp from the PowerPC books. For proper operation,
* Ks = 0, Kp = 1.
*/
#define MI_AP 786
#define MI_Ks 0x80000000 /* Should not be set */
#define MI_Kp 0x40000000 /* Should always be set */
/* The effective page number register. When read, contains the information
* about the last instruction TLB miss. When MI_RPN is written, bits in
* this register are used to create the TLB entry.
*/
#define MI_EPN 787
#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
#define MI_EVALID 0x00000200 /* Entry is valid */
#define MI_ASIDMASK 0x0000000f /* ASID match value */
/* Reset value is undefined */
/* A "level 1" or "segment" or whatever you want to call it register.
* For the instruction TLB, it contains bits that get loaded into the
* TLB entry when the MI_RPN is written.
*/
#define MI_TWC 789
#define MI_APG 0x000001e0 /* Access protection group (0) */
#define MI_GUARDED 0x00000010 /* Guarded storage */
#define MI_PSMASK 0x0000000c /* Mask of page size bits */
#define MI_PS8MEG 0x0000000c /* 8M page size */
#define MI_PS512K 0x00000004 /* 512K page size */
#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
#define MI_SVALID 0x00000001 /* Segment entry is valid */
/* Reset value is undefined */
/* Real page number. Defined by the pte. Writing this register
* causes a TLB entry to be created for the instruction TLB, using
* additional information from the MI_EPN, and MI_TWC registers.
*/
#define MI_RPN 790
/* Define an RPN value for mapping kernel memory to large virtual
* pages for boot initialization. This has real page number of 0,
* large page size, shared page, cache enabled, and valid.
* Also mark all subpages valid and write access.
*/
#define MI_BOOTINIT 0x000001fd
#define MD_CTR 792 /* Data TLB control register */
#define MD_GPM 0x80000000 /* Set domain manager mode */
#define MD_PPM 0x40000000 /* Set subpage protection */
#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
#define MD_RESETVAL 0x04000000 /* Value of register at reset */
#define M_CASID 793 /* Address space ID (context) to match */
#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
/* These are the Ks and Kp from the PowerPC books. For proper operation,
* Ks = 0, Kp = 1.
*/
#define MD_AP 794
#define MD_Ks 0x80000000 /* Should not be set */
#define MD_Kp 0x40000000 /* Should always be set */
/* The effective page number register. When read, contains the information
* about the last instruction TLB miss. When MD_RPN is written, bits in
* this register are used to create the TLB entry.
*/
#define MD_EPN 795
#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
#define MD_EVALID 0x00000200 /* Entry is valid */
#define MD_ASIDMASK 0x0000000f /* ASID match value */
/* Reset value is undefined */
/* The pointer to the base address of the first level page table.
* During a software tablewalk, reading this register provides the address
* of the entry associated with MD_EPN.
*/
#define M_TWB 796
#define M_L1TB 0xfffff000 /* Level 1 table base address */
#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
/* Reset value is undefined */
/* A "level 1" or "segment" or whatever you want to call it register.
* For the data TLB, it contains bits that get loaded into the TLB entry
* when the MD_RPN is written. It is also provides the hardware assist
* for finding the PTE address during software tablewalk.
*/
#define MD_TWC 797
#define MD_L2TB 0xfffff000 /* Level 2 table base address */
#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
#define MD_APG 0x000001e0 /* Access protection group (0) */
#define MD_GUARDED 0x00000010 /* Guarded storage */
#define MD_PSMASK 0x0000000c /* Mask of page size bits */
#define MD_PS8MEG 0x0000000c /* 8M page size */
#define MD_PS512K 0x00000004 /* 512K page size */
#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
#define MD_WT 0x00000002 /* Use writethrough page attribute */
#define MD_SVALID 0x00000001 /* Segment entry is valid */
/* Reset value is undefined */
/* Real page number. Defined by the pte. Writing this register
* causes a TLB entry to be created for the data TLB, using
* additional information from the MD_EPN, and MD_TWC registers.
*/
#define MD_RPN 798
/* This is a temporary storage register that could be used to save
* a processor working register during a tablewalk.
*/
#define M_TW 799
/*
* At present, all PowerPC 400-class processors share a similar TLB
* architecture. The instruction and data sides share a unified,
* 64-entry, fully-associative TLB which is maintained totally under
* software control. In addition, the instruction side has a
* hardware-managed, 4-entry, fully- associative TLB which serves as a
* first level to the shared TLB. These two TLBs are known as the UTLB
* and ITLB, respectively.
*/
#define PPC4XX_TLB_SIZE 64
/*
* TLB entries are defined by a "high" tag portion and a "low" data
* portion. On all architectures, the data portion is 32-bits.
*
* TLB entries are managed entirely under software control by reading,
* writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
* instructions.
*/
/*
* FSL Book-E support
*/
#define MAS0_TLBSEL_MSK 0x30000000
#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK)
#define MAS0_ESEL_MSK 0x0FFF0000
#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK)
#define MAS0_NV(x) ((x) & 0x00000FFF)
#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
#define MAS1_TS 0x00001000
#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
#define MAS2_EPN 0xFFFFF000
#define MAS2_X0 0x00000040
#define MAS2_X1 0x00000020
#define MAS2_W 0x00000010
#define MAS2_I 0x00000008
#define MAS2_M 0x00000004
#define MAS2_G 0x00000002
#define MAS2_E 0x00000001
#define MAS3_RPN 0xFFFFF000
#define MAS3_U0 0x00000200
#define MAS3_U1 0x00000100
#define MAS3_U2 0x00000080
#define MAS3_U3 0x00000040
#define MAS3_UX 0x00000020
#define MAS3_SX 0x00000010
#define MAS3_UW 0x00000008
#define MAS3_SW 0x00000004
#define MAS3_UR 0x00000002
#define MAS3_SR 0x00000001
#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
#define MAS4_TIDDSEL 0x000F0000
#define MAS4_TSIZED(x) MAS1_TSIZE(x)
#define MAS4_X0D 0x00000040
#define MAS4_X1D 0x00000020
#define MAS4_WD 0x00000010
#define MAS4_ID 0x00000008
#define MAS4_MD 0x00000004
#define MAS4_GD 0x00000002
#define MAS4_ED 0x00000001
#define MAS6_SPID0 0x3FFF0000
#define MAS6_SPID1 0x00007FFE
#define MAS6_SAS 0x00000001
#define MAS6_SPID MAS6_SPID0
#define MAS7_RPN 0xFFFFFFFF
#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
(MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
((((v) << 31) & MAS1_VALID) |\
(((iprot) << 30) & MAS1_IPROT) |\
(MAS1_TID(tid)) |\
(((ts) << 12) & MAS1_TS) |\
(MAS1_TSIZE(tsize)))
#define FSL_BOOKE_MAS2(epn, wimge) \
(((epn) & MAS3_RPN) | (wimge))
#define FSL_BOOKE_MAS3(rpn, user, perms) \
(((rpn) & MAS3_RPN) | (user) | (perms))
#define FSL_BOOKE_MAS7(rpn) \
(((u64)(rpn)) >> 32)
#define BOOKE_PAGESZ_1K 0
#define BOOKE_PAGESZ_4K 1
#define BOOKE_PAGESZ_16K 2
#define BOOKE_PAGESZ_64K 3
#define BOOKE_PAGESZ_256K 4
#define BOOKE_PAGESZ_1M 5
#define BOOKE_PAGESZ_4M 6
#define BOOKE_PAGESZ_16M 7
#define BOOKE_PAGESZ_64M 8
#define BOOKE_PAGESZ_256M 9
#define BOOKE_PAGESZ_1G 10
#define BOOKE_PAGESZ_4G 11
#define BOOKE_PAGESZ_16GB 12
#define BOOKE_PAGESZ_64GB 13
#define BOOKE_PAGESZ_256GB 14
#define BOOKE_PAGESZ_1TB 15
#ifdef CONFIG_E500
#ifndef __ASSEMBLY__
extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
u8 perms, u8 wimge,
u8 ts, u8 esel, u8 tsize, u8 iprot);
extern void disable_tlb(u8 esel);
extern void invalidate_tlb(u8 tlb);
extern void init_tlbs(void);
extern int find_tlb_idx(void *addr, u8 tlbsel);
extern void init_used_tlb_cams(void);
extern int find_free_tlbcam(void);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
{ .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \
.mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \
.mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \
.mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \
.mas7 = FSL_BOOKE_MAS7(_rpn), }
struct fsl_e_tlb_entry {
u32 mas0;
u32 mas1;
u32 mas2;
u32 mas3;
u32 mas7;
};
extern struct fsl_e_tlb_entry tlb_table[];
extern int num_tlb_entries;
#endif
#endif
#ifdef CONFIG_E300
#define LAWAR_EN 0x80000000
#define LAWAR_SIZE 0x0000003F
#define LAWAR_TRGT_IF_PCI 0x00000000
#define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
#define LAWAR_TRGT_IF_PCIE1 0x00200000
#define LAWAR_TRGT_IF_PCIE2 0x00100000
#define LAWAR_TRGT_IF_PCIE3 0x00300000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
#define LAWAR_TRGT_IF_RIO 0x00c00000
#define LAWAR_TRGT_IF_DDR 0x00f00000
#define LAWAR_TRGT_IF_DDR1 0x00f00000
#define LAWAR_TRGT_IF_DDR2 0x01600000
#define LAWAR_SIZE_BASE 0xa
#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
#endif
#ifdef CONFIG_440
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
#define TLB2(a) ((a) & 0x00000fbf)
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ;\
0: mflr r0 ;\
mtlr r1 ;\
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/*----------------------------------------------------------------------------+
| TLB specific defines.
+----------------------------------------------------------------------------*/
#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
#define TLB_16MB_ALIGN_MASK 0xFFF000000ULL
#define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL
#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
#define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL
#define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL
#define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL
#define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL
#define TLB_256MB_SIZE 0x10000000
#define TLB_16MB_SIZE 0x01000000
#define TLB_1MB_SIZE 0x00100000
#define TLB_256KB_SIZE 0x00040000
#define TLB_64KB_SIZE 0x00010000
#define TLB_16KB_SIZE 0x00004000
#define TLB_4KB_SIZE 0x00001000
#define TLB_1KB_SIZE 0x00000400
#define TLB_WORD0_EPN_MASK 0xFFFFFC00
#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_V_MASK 0x00000200
#define TLB_WORD0_V_ENABLE 0x00000200
#define TLB_WORD0_V_DISABLE 0x00000000
#define TLB_WORD0_TS_MASK 0x00000100
#define TLB_WORD0_TS_1 0x00000100
#define TLB_WORD0_TS_0 0x00000000
#define TLB_WORD0_SIZE_MASK 0x000000F0
#define TLB_WORD0_SIZE_1KB 0x00000000
#define TLB_WORD0_SIZE_4KB 0x00000010
#define TLB_WORD0_SIZE_16KB 0x00000020
#define TLB_WORD0_SIZE_64KB 0x00000030
#define TLB_WORD0_SIZE_256KB 0x00000040
#define TLB_WORD0_SIZE_1MB 0x00000050
#define TLB_WORD0_SIZE_16MB 0x00000070
#define TLB_WORD0_SIZE_256MB 0x00000090
#define TLB_WORD0_TPAR_MASK 0x0000000F
#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
#define TLB_WORD1_RPN_MASK 0xFFFFFC00
#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_PAR1_MASK 0x00000300
#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
#define TLB_WORD1_PAR1_0 0x00000000
#define TLB_WORD1_PAR1_1 0x00000100
#define TLB_WORD1_PAR1_2 0x00000200
#define TLB_WORD1_PAR1_3 0x00000300
#define TLB_WORD1_ERPN_MASK 0x0000000F
#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
#define TLB_WORD2_PAR2_MASK 0xC0000000
#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
#define TLB_WORD2_PAR2_0 0x00000000
#define TLB_WORD2_PAR2_1 0x40000000
#define TLB_WORD2_PAR2_2 0x80000000
#define TLB_WORD2_PAR2_3 0xC0000000
#define TLB_WORD2_U0_MASK 0x00008000
#define TLB_WORD2_U0_ENABLE 0x00008000
#define TLB_WORD2_U0_DISABLE 0x00000000
#define TLB_WORD2_U1_MASK 0x00004000
#define TLB_WORD2_U1_ENABLE 0x00004000
#define TLB_WORD2_U1_DISABLE 0x00000000
#define TLB_WORD2_U2_MASK 0x00002000
#define TLB_WORD2_U2_ENABLE 0x00002000
#define TLB_WORD2_U2_DISABLE 0x00000000
#define TLB_WORD2_U3_MASK 0x00001000
#define TLB_WORD2_U3_ENABLE 0x00001000
#define TLB_WORD2_U3_DISABLE 0x00000000
#define TLB_WORD2_W_MASK 0x00000800
#define TLB_WORD2_W_ENABLE 0x00000800
#define TLB_WORD2_W_DISABLE 0x00000000
#define TLB_WORD2_I_MASK 0x00000400
#define TLB_WORD2_I_ENABLE 0x00000400
#define TLB_WORD2_I_DISABLE 0x00000000
#define TLB_WORD2_M_MASK 0x00000200
#define TLB_WORD2_M_ENABLE 0x00000200
#define TLB_WORD2_M_DISABLE 0x00000000
#define TLB_WORD2_G_MASK 0x00000100
#define TLB_WORD2_G_ENABLE 0x00000100
#define TLB_WORD2_G_DISABLE 0x00000000
#define TLB_WORD2_E_MASK 0x00000080
#define TLB_WORD2_E_ENABLE 0x00000080
#define TLB_WORD2_E_DISABLE 0x00000000
#define TLB_WORD2_UX_MASK 0x00000020
#define TLB_WORD2_UX_ENABLE 0x00000020
#define TLB_WORD2_UX_DISABLE 0x00000000
#define TLB_WORD2_UW_MASK 0x00000010
#define TLB_WORD2_UW_ENABLE 0x00000010
#define TLB_WORD2_UW_DISABLE 0x00000000
#define TLB_WORD2_UR_MASK 0x00000008
#define TLB_WORD2_UR_ENABLE 0x00000008
#define TLB_WORD2_UR_DISABLE 0x00000000
#define TLB_WORD2_SX_MASK 0x00000004
#define TLB_WORD2_SX_ENABLE 0x00000004
#define TLB_WORD2_SX_DISABLE 0x00000000
#define TLB_WORD2_SW_MASK 0x00000002
#define TLB_WORD2_SW_ENABLE 0x00000002
#define TLB_WORD2_SW_DISABLE 0x00000000
#define TLB_WORD2_SR_MASK 0x00000001
#define TLB_WORD2_SR_ENABLE 0x00000001
#define TLB_WORD2_SR_DISABLE 0x00000000
/*----------------------------------------------------------------------------+
| Following instructions are not available in Book E mode of the GNU assembler.
+----------------------------------------------------------------------------*/
#define DCCCI(ra,rb) .long 0x7c000000|\
(ra<<16)|(rb<<11)|(454<<1)
#define ICCCI(ra,rb) .long 0x7c000000|\
(ra<<16)|(rb<<11)|(966<<1)
#define DCREAD(rt,ra,rb) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
#define ICREAD(ra,rb) .long 0x7c000000|\
(ra<<16)|(rb<<11)|(998<<1)
#define TLBSX(rt,ra,rb) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
#define TLBWE(rs,ra,ws) .long 0x7c000000|\
(rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
#define TLBRE(rt,ra,ws) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
#define MSYNC .long 0x7c000000|\
(598<<1)
#define MBAR_INST .long 0x7c000000|\
(854<<1)
#ifndef __ASSEMBLY__
/* Prototypes */
void mttlb1(unsigned long index, unsigned long value);
void mttlb2(unsigned long index, unsigned long value);
void mttlb3(unsigned long index, unsigned long value);
unsigned long mftlb1(unsigned long index);
unsigned long mftlb2(unsigned long index);
unsigned long mftlb3(unsigned long index);
void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void remove_tlb(u32 vaddr, u32 size);
void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_440 */
#endif /* _PPC_MMU_H_ */

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/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _ASM_MP_H_
#define _ASM_MP_H_
#include <lmb.h>
void setup_mp(void);
void cpu_mp_lmb_reserve(struct lmb *lmb);
u32 determine_mp_bootpg(void);
#endif

58
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/*
* include/asm-ppc/mpc512x.h
*
* Prototypes, etc. for the Freescale MPC512x embedded cpu chips
*
* 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASMPPC_MPC512X_H
#define __ASMPPC_MPC512X_H
/*
* macros for manipulating CSx_START/STOP
*/
#define CSAW_START(start) ((start) & 0xFFFF0000)
#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
/*
* Inlines
*/
/*
* According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was
* modified last and an isync.
*/
static inline void sync_law(volatile void *addr)
{
in_be32(addr);
__asm__ __volatile__ ("isync");
}
/*
* Prototypes
*/
extern long int fixed_sdram(ddr512x_config_t *mddrc_config,
u32 *dram_init_seq, int seq_sz);
extern int mpc5121_diu_init(void);
extern void ide_set_reset(int idereset);
#endif /* __ASMPPC_MPC512X_H */

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arch/powerpc/include/asm/mpc8349_pci.h Normal file
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#ifndef _PPC_KERNEL_MPC8349_PCI_H
#define _PPC_KERNEL_MPC8349_PCI_H
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
#define M8265_PCIMSK0 0x101c4
#define M8265_PCIMSK1 0x101c8
/* Bit definitions for PCIBR registers */
#define PCIBR_ENABLE 0x00000001
/* Bit definitions for PCIMSK registers */
#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
#define PCIMSK_64KB 0xFFFF0000
#define PCIMSK_128KB 0xFFFE0000
#define PCIMSK_256KB 0xFFFC0000
#define PCIMSK_512KB 0xFFF80000
#define PCIMSK_1MB 0xFFF00000
#define PCIMSK_2MB 0xFFE00000
#define PCIMSK_4MB 0xFFC00000
#define PCIMSK_8MB 0xFF800000
#define PCIMSK_16MB 0xFF000000
#define PCIMSK_32MB 0xFE000000
#define PCIMSK_64MB 0xFC000000
#define PCIMSK_128MB 0xF8000000
#define PCIMSK_256MB 0xF0000000
#define PCIMSK_512MB 0xE0000000
#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */
#define M826X_SCCR_PCI_MODE_EN 0x100
/*
* Outbound ATU registers (3 sets). These registers control how 60x bus
* (local) addresses are translated to PCI addresses when the MPC826x is
* a PCI bus master (initiator).
*/
#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
#define POTAR_REG1 0x10818
#define POTAR_REG2 0x10830
#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
#define POBAR_REG1 0x10820
#define POBAR_REG2 0x10838
#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
#define POCMR_REG1 0x10828
#define POCMR_REG2 0x10840
/* Bit definitions for POMCR registers */
#define POCMR_MASK_4KB 0x000FFFFF
#define POCMR_MASK_8KB 0x000FFFFE
#define POCMR_MASK_16KB 0x000FFFFC
#define POCMR_MASK_32KB 0x000FFFF8
#define POCMR_MASK_64KB 0x000FFFF0
#define POCMR_MASK_128KB 0x000FFFE0
#define POCMR_MASK_256KB 0x000FFFC0
#define POCMR_MASK_512KB 0x000FFF80
#define POCMR_MASK_1MB 0x000FFF00
#define POCMR_MASK_2MB 0x000FFE00
#define POCMR_MASK_4MB 0x000FFC00
#define POCMR_MASK_8MB 0x000FF800
#define POCMR_MASK_16MB 0x000FF000
#define POCMR_MASK_32MB 0x000FE000
#define POCMR_MASK_64MB 0x000FC000
#define POCMR_MASK_128MB 0x000F8000
#define POCMR_MASK_256MB 0x000F0000
#define POCMR_MASK_512MB 0x000E0000
#define POCMR_MASK_1GB 0x000C0000
#define POCMR_ENABLE 0x80000000
#define POCMR_PCI_IO 0x40000000
#define POCMR_PREFETCH_EN 0x20000000
#define POCMR_PCI2 0x10000000
/* Soft PCI reset */
#define PCI_GCR_REG 0x10880
/* Bit definitions for PCI_GCR registers */
#define PCIGCR_PCI_BUS_EN 0x1
/*
* Inbound ATU registers (2 sets). These registers control how PCI
* addresses are translated to 60x bus (local) addresses when the
* MPC826x is a PCI bus target.
*/
#define PITAR_REG1 0x108D0
#define PIBAR_REG1 0x108D8
#define PICMR_REG1 0x108E0
#define PITAR_REG0 0x108E8
#define PIBAR_REG0 0x108F0
#define PICMR_REG0 0x108F8
/* Bit definitions for PCI Inbound Comparison Mask registers */
#define PICMR_MASK_4KB 0x000FFFFF
#define PICMR_MASK_8KB 0x000FFFFE
#define PICMR_MASK_16KB 0x000FFFFC
#define PICMR_MASK_32KB 0x000FFFF8
#define PICMR_MASK_64KB 0x000FFFF0
#define PICMR_MASK_128KB 0x000FFFE0
#define PICMR_MASK_256KB 0x000FFFC0
#define PICMR_MASK_512KB 0x000FFF80
#define PICMR_MASK_1MB 0x000FFF00
#define PICMR_MASK_2MB 0x000FFE00
#define PICMR_MASK_4MB 0x000FFC00
#define PICMR_MASK_8MB 0x000FF800
#define PICMR_MASK_16MB 0x000FF000
#define PICMR_MASK_32MB 0x000FE000
#define PICMR_MASK_64MB 0x000FC000
#define PICMR_MASK_128MB 0x000F8000
#define PICMR_MASK_256MB 0x000F0000
#define PICMR_MASK_512MB 0x000E0000
#define PICMR_MASK_1GB 0x000C0000
#define PICMR_ENABLE 0x80000000
#define PICMR_NO_SNOOP_EN 0x40000000
#define PICMR_PREFETCH_EN 0x20000000
/* PCI error Registers */
#define PCI_ERROR_STATUS_REG 0x10884
#define PCI_ERROR_MASK_REG 0x10888
#define PCI_ERROR_CONTROL_REG 0x1088C
#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
/* PCI error Register bit defines */
#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
#define PCI_ERROR_PCI_NO_RSP 0x00000008
#define PCI_ERROR_PCI_TAR_ABT 0x00000010
#define PCI_ERROR_PCI_SERR 0x00000020
#define PCI_ERROR_PCI_PERR_RD 0x00000040
#define PCI_ERROR_PCI_PERR_WR 0x00000080
#define PCI_ERROR_I2O_OFQO 0x00000100
#define PCI_ERROR_I2O_IPQO 0x00000200
#define PCI_ERROR_IRA 0x00000400
#define PCI_ERROR_NMI 0x00000800
#define PCI_ERROR_I2O_DBMC 0x00001000
/*
* Register pair used to generate configuration cycles on the PCI bus
* and access the MPC826x's own PCI configuration registers.
*/
#define PCI_CFG_ADDR_REG 0x10900
#define PCI_CFG_DATA_REG 0x10904
/* Bus parking decides where the bus control sits when idle */
/* If modifying memory controllers for PCI park on the core */
#define PPC_ACR_BUS_PARK_CORE 0x6
#define PPC_ACR_BUS_PARK_PCI 0x3
#endif /* _PPC_KERNEL_M8260_PCI_H */

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/*
* Freescale non-CPM SPI Controller
*
* Copyright 2008 Qstreams Networks, Inc.
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_MPC8XXX_SPI_H_
#define _ASM_MPC8XXX_SPI_H_
#include <asm/types.h>
#if defined(CONFIG_MPC834x) || \
defined(CONFIG_MPC8313) || \
defined(CONFIG_MPC8315) || \
defined(CONFIG_MPC837x)
typedef struct spi8xxx {
u8 res0[0x20]; /* 0x0-0x01f reserved */
u32 mode; /* mode register */
u32 event; /* event register */
u32 mask; /* mask register */
u32 com; /* command register */
u32 tx; /* transmit register */
u32 rx; /* receive register */
u8 res1[0xFC8]; /* fill up to 0x1000 */
} spi8xxx_t;
#endif
#endif /* _ASM_MPC8XXX_SPI_H_ */

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/* originally from linux source (asm-ppc/io.h).
* Sanity added by Rob Taylor, Flying Pig Systems, 2000
*/
#ifndef _PCI_IO_H_
#define _PCI_IO_H_
#include "io.h"
#define pci_read_le16(addr, dest) \
__asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \
"r" (addr), "m" (*addr));
#define pci_write_le16(addr, val) \
__asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \
"r" (val), "r" (addr));
#define pci_read_le32(addr, dest) \
__asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \
"r" (addr), "m" (*addr));
#define pci_write_le32(addr, val) \
__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \
"r" (val), "r" (addr));
#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr))
#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
#if !defined(__BIG_ENDIAN)
#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr))
#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr))
#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
#else
#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b))
#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b))
#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b))
#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b))
#endif
#endif /* _PCI_IO_H_ */

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arch/powerpc/include/asm/pnp.h Normal file
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/* 11/02/95 */
/*----------------------------------------------------------------------------*/
/* Plug and Play header definitions */
/*----------------------------------------------------------------------------*/
/* Structure map for PnP on PowerPC Reference Platform */
/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */
/* (or later versions) is available on Compuserve in the PLUGPLAY area. */
/* This code has extensions to that specification, namely new short and */
/* long tag types for platform dependent information */
/* Warning: LE notation used throughout this file */
/* For enum's: if given in hex then they are bit significant, i.e. */
/* only one bit is on for each enum */
#ifndef _PNP_
#define _PNP_
#ifndef __ASSEMBLY__
#define MAX_MEM_REGISTERS 9
#define MAX_IO_PORTS 20
#define MAX_IRQS 7
/*#define MAX_DMA_CHANNELS 7*/
/* Interrupt controllers */
#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */
#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */
#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */
#define PNPinterrupt3 "PNP0003" /* APIC */
#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */
/* Timers */
#define PNPtimer0 "PNP0100" /* AT Timer */
#define PNPtimer1 "PNP0101" /* EISA Timer */
#define PNPtimer2 "PNP0102" /* MCA Timer */
/* DMA controllers */
#define PNPdma0 "PNP0200" /* AT DMA Controller */
#define PNPdma1 "PNP0201" /* EISA DMA Controller */
#define PNPdma2 "PNP0202" /* MCA DMA Controller */
/* start of August 15, 1994 additions */
/* CMOS */
#define PNPCMOS "IBM0009" /* CMOS */
/* L2 Cache */
#define PNPL2 "IBM0007" /* L2 Cache */
/* NVRAM */
#define PNPNVRAM "IBM0008" /* NVRAM */
/* Power Management */
#define PNPPM "IBM0005" /* Power Management */
/* end of August 15, 1994 additions */
/* Keyboards */
#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */
#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */
#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */
#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */
#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */
#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */
#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */
#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */
/* Parallel port controllers */
#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */
#define PNPparallel1 "PNP0401" /* ECP Parallel Port */
#define PNPepp "IBM001C" /* EPP Parallel Port */
/* Serial port controllers */
#define PNPserial0 "PNP0500" /* Standard PC Serial port */
#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */
/* Disk controllers */
#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */
#define PNPdisk1 "PNP0601" /* Plus Hardcard II */
#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */
/* Diskette controllers */
#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */
/* Display controllers */
#define PNPdisplay0 "PNP0900" /* VGA Compatible */
#define PNPdisplay1 "PNP0901" /* Video Seven VGA */
#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */
#define PNPdisplay3 "PNP0903" /* Trident VGA */
#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */
#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */
#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */
#define PNPdisplay7 "PNP0907" /* Western Digital VGA */
#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */
#define PNPdisplay9 "PNP0909" /* S3 */
#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */
#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */
#define PNPdisplayC "PNP090C" /* XGA Compatible */
#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */
#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */
#define PNPdisplayF "PNP090F" /* Oak Technology VGA */
/* Peripheral busses */
#define PNPbuses0 "PNP0A00" /* ISA Bus */
#define PNPbuses1 "PNP0A01" /* EISA Bus */
#define PNPbuses2 "PNP0A02" /* MCA Bus */
#define PNPbuses3 "PNP0A03" /* PCI Bus */
#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */
/* RTC, BIOS, planar devices */
#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */
#define PNPrtc0 "PNP0B00" /* AT RTC */
#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */
#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */
#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */
#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */
/* PCMCIA controller */
#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */
/* Mice */
#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */
#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */
#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */
#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */
#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */
#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */
#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */
#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */
#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */
#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */
#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */
#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */
/* Modems */
#define PNPmodem0 "PNP9000" /* Specific IDs TBD */
/* Network controllers */
#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */
#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */
#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */
#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */
#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */
#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */
#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */
#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */
/* SCSI controllers */
#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */
#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */
#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/
#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */
#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */
#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */
#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */
/* Sound/Video, Multimedia */
#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */
#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */
#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */
#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */
#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */
#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */
#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */
#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */
/* Operator Panel */
#define PNPopctl "IBM000B" /* Operator's panel */
/* Service Processor */
#define PNPsp "IBM0011" /* IBM Service Processor */
#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */
#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */
/* Memory Controller */
#define PNPmemctl "IBM000A" /* Memory controller */
/* Graphics Assist */
#define PNPg_assist "IBM0014" /* Graphics Assist */
/* Miscellaneous Device Controllers */
#define PNPtablet "IBM0019" /* IBM Tablet Controller */
/* PNP Packet Handles */
#define S1_Packet 0x0A /* Version resource */
#define S2_Packet 0x15 /* Logical DEVID (without flags) */
#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */
#define S3_Packet 0x1C /* Compatible device ID */
#define S4_Packet 0x22 /* IRQ resource (without flags) */
#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */
#define S5_Packet 0x2A /* DMA resource */
#define S6_Packet 0x30 /* Depend funct start (w/o priority) */
#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */
#define S7_Packet 0x38 /* Depend funct end */
#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */
#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */
#define S14_Packet 0x71 /* Vendor defined */
#define S15_Packet 0x78 /* End of resource (w/o checksum) */
#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */
#define L1_Packet 0x81 /* Memory range */
#define L1_Shadow 0x20 /* Memory is shadowable */
#define L1_32bit_mem 0x18 /* 32-bit memory only */
#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */
#define L1_Decode_Hi 0x04 /* decode supports high address */
#define L1_Cache 0x02 /* read cacheable, write-through */
#define L1_Writeable 0x01 /* Memory is writeable */
#define L2_Packet 0x82 /* ANSI ID string */
#define L3_Packet 0x83 /* Unicode ID string */
#define L4_Packet 0x84 /* Vendor defined */
#define L5_Packet 0x85 /* Large I/O */
#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */
#define END_TAG 0x78 /* End of resource */
#define DF_START_TAG 0x30 /* Dependent function start */
#define DF_START_TAG_priority 0x31 /* Dependent function start */
#define DF_END_TAG 0x38 /* Dependent function end */
#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */
/* Device Base Type Codes */
typedef enum _PnP_BASE_TYPE {
Reserved = 0,
MassStorageDevice = 1,
NetworkInterfaceController = 2,
DisplayController = 3,
MultimediaController = 4,
MemoryController = 5,
BridgeController = 6,
CommunicationsDevice = 7,
SystemPeripheral = 8,
InputDevice = 9,
ServiceProcessor = 0x0A, /* 11/2/95 */
} PnP_BASE_TYPE;
/* Device Sub Type Codes */
typedef enum _PnP_SUB_TYPE {
SCSIController = 0,
IDEController = 1,
FloppyController = 2,
IPIController = 3,
OtherMassStorageController = 0x80,
EthernetController = 0,
TokenRingController = 1,
FDDIController = 2,
OtherNetworkController = 0x80,
VGAController= 0,
SVGAController= 1,
XGAController= 2,
OtherDisplayController = 0x80,
VideoController = 0,
AudioController = 1,
OtherMultimediaController = 0x80,
RAM = 0,
FLASH = 1,
OtherMemoryDevice = 0x80,
HostProcessorBridge = 0,
ISABridge = 1,
EISABridge = 2,
MicroChannelBridge = 3,
PCIBridge = 4,
PCMCIABridge = 5,
VMEBridge = 6,
OtherBridgeDevice = 0x80,
RS232Device = 0,
ATCompatibleParallelPort = 1,
OtherCommunicationsDevice = 0x80,
ProgrammableInterruptController = 0,
DMAController = 1,
SystemTimer = 2,
RealTimeClock = 3,
L2Cache = 4,
NVRAM = 5,
PowerManagement = 6,
CMOS = 7,
OperatorPanel = 8,
ServiceProcessorClass1 = 9,
ServiceProcessorClass2 = 0xA,
ServiceProcessorClass3 = 0xB,
GraphicAssist = 0xC,
SystemPlanar = 0xF, /* 10/5/95 */
OtherSystemPeripheral = 0x80,
KeyboardController = 0,
Digitizer = 1,
MouseController = 2,
TabletController = 3, /* 10/27/95 */
OtherInputController = 0x80,
GeneralMemoryController = 0,
} PnP_SUB_TYPE;
/* Device Interface Type Codes */
typedef enum _PnP_INTERFACE {
General = 0,
GeneralSCSI = 0,
GeneralIDE = 0,
ATACompatible = 1,
GeneralFloppy = 0,
Compatible765 = 1,
NS398_Floppy = 2, /* NS Super I/O wired to use index
register at port 398 and data
register at port 399 */
NS26E_Floppy = 3, /* Ports 26E and 26F */
NS15C_Floppy = 4, /* Ports 15C and 15D */
NS2E_Floppy = 5, /* Ports 2E and 2F */
CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */
GeneralIPI = 0,
GeneralEther = 0,
GeneralToken = 0,
GeneralFDDI = 0,
GeneralVGA = 0,
GeneralSVGA = 0,
GeneralXGA = 0,
GeneralVideo = 0,
GeneralAudio = 0,
CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */
GeneralRAM = 0,
GeneralFLASH = 0,
PCIMemoryController = 0, /* PCI Config Method */
RS6KMemoryController = 1, /* RS6K Config Method */
GeneralHostBridge = 0,
GeneralISABridge = 0,
GeneralEISABridge = 0,
GeneralMCABridge = 0,
GeneralPCIBridge = 0,
PCIBridgeDirect = 0,
PCIBridgeIndirect = 1,
PCIBridgeRS6K = 2,
GeneralPCMCIABridge = 0,
GeneralVMEBridge = 0,
GeneralRS232 = 0,
COMx = 1,
Compatible16450 = 2,
Compatible16550 = 3,
NS398SerPort = 4, /* NS Super I/O wired to use index
register at port 398 and data
register at port 399 */
NS26ESerPort = 5, /* Ports 26E and 26F */
NS15CSerPort = 6, /* Ports 15C and 15D */
NS2ESerPort = 7, /* Ports 2E and 2F */
GeneralParPort = 0,
LPTx = 1,
NS398ParPort = 2, /* NS Super I/O wired to use index
register at port 398 and data
register at port 399 */
NS26EParPort = 3, /* Ports 26E and 26F */
NS15CParPort = 4, /* Ports 15C and 15D */
NS2EParPort = 5, /* Ports 2E and 2F */
GeneralPIC = 0,
ISA_PIC = 1,
EISA_PIC = 2,
MPIC = 3,
RS6K_PIC = 4,
GeneralDMA = 0,
ISA_DMA = 1,
EISA_DMA = 2,
GeneralTimer = 0,
ISA_Timer = 1,
EISA_Timer = 2,
GeneralRTC = 0,
ISA_RTC = 1,
StoreThruOnly = 1,
StoreInEnabled = 2,
RS6KL2Cache = 3,
IndirectNVRAM = 0, /* Indirectly addressed */
DirectNVRAM = 1, /* Memory Mapped */
IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */
GeneralPowerManagement = 0,
EPOWPowerManagement = 1,
PowerControl = 2, /* d1378 */
GeneralCMOS = 0,
GeneralOPPanel = 0,
HarddiskLight = 1,
CDROMLight = 2,
PowerLight = 3,
KeyLock = 4,
ANDisplay = 5, /* AlphaNumeric Display */
SystemStatusLED = 6, /* 3 digit 7 segment LED */
CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */
GeneralServiceProcessor = 0,
TransferData = 1,
IGMC32 = 2,
IGMC64 = 3,
GeneralSystemPlanar = 0, /* 10/5/95 */
} PnP_INTERFACE;
/* PnP resources */
/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
typedef struct _SERIAL_ID {
unsigned char VendorID0; /* Bit(7)=0 */
/* Bits(6:2)=1st character in */
/* compressed ASCII */
/* Bits(1:0)=2nd character in */
/* compressed ASCII bits(4:3) */
unsigned char VendorID1; /* Bits(7:5)=2nd character in */
/* compressed ASCII bits(2:0) */
/* Bits(4:0)=3rd character in */
/* compressed ASCII */
unsigned char VendorID2; /* Product number - vendor assigned */
unsigned char VendorID3; /* Product number - vendor assigned */
/* Serial number is to provide uniqueness if more than one board of same */
/* type is in system. Must be "FFFFFFFF" if feature not supported. */
unsigned char Serial0; /* Unique serial number bits (7:0) */
unsigned char Serial1; /* Unique serial number bits (15:8) */
unsigned char Serial2; /* Unique serial number bits (23:16) */
unsigned char Serial3; /* Unique serial number bits (31:24) */
unsigned char Checksum;
} SERIAL_ID;
typedef enum _PnPItemName {
Unused = 0,
PnPVersion = 1,
LogicalDevice = 2,
CompatibleDevice = 3,
IRQFormat = 4,
DMAFormat = 5,
StartDepFunc = 6,
EndDepFunc = 7,
IOPort = 8,
FixedIOPort = 9,
Res1 = 10,
Res2 = 11,
Res3 = 12,
SmallVendorItem = 14,
EndTag = 15,
MemoryRange = 1,
ANSIIdentifier = 2,
UnicodeIdentifier = 3,
LargeVendorItem = 4,
MemoryRange32 = 5,
MemoryRangeFixed32 = 6,
} PnPItemName;
/* Define a bunch of access functions for the bits in the tag field */
/* Tag type - 0 = small; 1 = large */
#define tag_type(t) (((t) & 0x80)>>7)
#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
/* Small item name is 4 bits - one of PnPItemName enum above */
#define tag_small_item_name(t) (((t) & 0x78)>>3)
#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
/* Small item count is 3 bits - count of further bytes in packet */
#define tag_small_count(t) ((t) & 0x07)
#define set_tag_count(t,v) (t = (t & 0x78) | (v))
/* Large item name is 7 bits - one of PnPItemName enum above */
#define tag_large_item_name(t) ((t) & 0x7f)
#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
typedef union _PnP_TAG_PACKET {
struct _S1_Pack{ /* VERSION PACKET */
unsigned char Tag; /* small tag = 0x0a */
unsigned char Version[2]; /* PnP version, Vendor version */
} S1_Pack;
struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */
unsigned char Tag; /* small tag = 0x15 or 0x16 */
unsigned char DevId[4]; /* Logical device id */
unsigned char Flags[2]; /* bit(0) boot device; */
/* bit(7:1) cmd in range x31-x37 */
/* bit(7:0) cmd in range x28-x3f (opt)*/
} S2_Pack;
struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */
unsigned char Tag; /* small tag = 0x1c */
unsigned char CompatId[4]; /* Compatible device id */
} S3_Pack;
struct _S4_Pack{ /* IRQ PACKET */
unsigned char Tag; /* small tag = 0x22 or 0x23 */
unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */
/* bit(0) is IRQ8 ... */
unsigned char IRQInfo; /* optional; assume bit(0)=1; else */
/* bit(0) - high true edge sensitive */
/* bit(1) - low true edge sensitive */
/* bit(2) - high true level sensitive*/
/* bit(3) - low true level sensitive */
/* bit(7:4) - must be 0 */
} S4_Pack;
struct _S5_Pack{ /* DMA PACKET */
unsigned char Tag; /* small tag = 0x2a */
unsigned char DMAMask; /* bit(0) is channel 0 ... */
unsigned char DMAInfo;
} S5_Pack;
struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */
unsigned char Tag; /* small tag = 0x30 or 0x31 */
unsigned char Priority; /* Optional; if missing then x01; else*/
/* x00 = best possible */
/* x01 = acceptible */
/* x02 = sub-optimal but functional */
} S6_Pack;
struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */
unsigned char Tag; /* small tag = 0x38 */
} S7_Pack;
struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */
unsigned char Tag; /* small tag x47 */
unsigned char IOInfo; /* x0 = decode only bits(9:0); */
#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */
unsigned char RangeMin[2]; /* Min base address */
unsigned char RangeMax[2]; /* Max base address */
unsigned char IOAlign; /* base alignmt, incr in 1B blocks */
unsigned char IONum; /* number of contiguous I/O ports */
} S8_Pack;
struct _S9_Pack{ /* FIXED I/O PORT PACKET */
unsigned char Tag; /* small tag = 0x4b */
unsigned char Range[2]; /* base address 10 bits */
unsigned char IONum; /* number of contiguous I/O ports */
} S9_Pack;
struct _S14_Pack{ /* VENDOR DEFINED PACKET */
unsigned char Tag; /* small tag = 0x7m m = 1-7 */
union _S14_Data{
unsigned char Data[7]; /* Vendor defined */
struct _S14_PPCPack{ /* Pr*p s14 pack */
unsigned char Type; /* 00=non-IBM */
unsigned char PPCData[6]; /* Vendor defined */
} S14_PPCPack;
} S14_Data;
} S14_Pack;
struct _S15_Pack{ /* END PACKET */
unsigned char Tag; /* small tag = 0x78 or 0x79 */
unsigned char Check; /* optional - checksum */
} S15_Pack;
struct _L1_Pack{ /* MEMORY RANGE PACKET */
unsigned char Tag; /* large tag = 0x81 */
unsigned char Count0; /* x09 */
unsigned char Count1; /* x00 */
unsigned char Data[9]; /* a variable array of bytes, */
/* count in tag */
} L1_Pack;
struct _L2_Pack{ /* ANSI ID STRING PACKET */
unsigned char Tag; /* large tag = 0x82 */
unsigned char Count0; /* Length of string */
unsigned char Count1;
unsigned char Identifier[1]; /* a variable array of bytes, */
/* count in tag */
} L2_Pack;
struct _L3_Pack{ /* UNICODE ID STRING PACKET */
unsigned char Tag; /* large tag = 0x83 */
unsigned char Count0; /* Length + 2 of string */
unsigned char Count1;
unsigned char Country0; /* TBD */
unsigned char Country1; /* TBD */
unsigned char Identifier[1]; /* a variable array of bytes, */
/* count in tag */
} L3_Pack;
struct _L4_Pack{ /* VENDOR DEFINED PACKET */
unsigned char Tag; /* large tag = 0x84 */
unsigned char Count0;
unsigned char Count1;
union _L4_Data{
unsigned char Data[1]; /* a variable array of bytes, */
/* count in tag */
struct _L4_PPCPack{ /* Pr*p L4 packet */
unsigned char Type; /* 00=non-IBM */
unsigned char PPCData[1]; /* a variable array of bytes, */
/* count in tag */
} L4_PPCPack;
} L4_Data;
} L4_Pack;
struct _L5_Pack{
unsigned char Tag; /* large tag = 0x85 */
unsigned char Count0; /* Count = 17 */
unsigned char Count1;
unsigned char Data[17];
} L5_Pack;
struct _L6_Pack{
unsigned char Tag; /* large tag = 0x86 */
unsigned char Count0; /* Count = 9 */
unsigned char Count1;
unsigned char Data[9];
} L6_Pack;
} PnP_TAG_PACKET;
#endif /* __ASSEMBLY__ */
#endif /* ndef _PNP_ */

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#ifndef _PPC_POSIX_TYPES_H
#define _PPC_POSIX_TYPES_H
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
typedef unsigned int __kernel_dev_t;
typedef unsigned int __kernel_ino_t;
typedef unsigned int __kernel_mode_t;
typedef unsigned short __kernel_nlink_t;
typedef long __kernel_off_t;
typedef int __kernel_pid_t;
typedef unsigned int __kernel_uid_t;
typedef unsigned int __kernel_gid_t;
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef long __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
typedef int __kernel_daddr_t;
typedef char * __kernel_caddr_t;
typedef short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
typedef unsigned int __kernel_gid32_t;
typedef unsigned int __kernel_old_uid_t;
typedef unsigned int __kernel_old_gid_t;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
int val[2];
} __kernel_fsid_t;
#ifndef __GNUC__
#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
#define __FD_ZERO(set) \
((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
#else /* __GNUC__ */
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
|| (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
/* With GNU C, use inline functions instead so args are evaluated only once: */
#undef __FD_SET
static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
}
#undef __FD_CLR
static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
}
#undef __FD_ISSET
static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
}
/*
* This will unroll the loop for the normal constant case (8 ints,
* for a 256-bit fd_set)
*/
#undef __FD_ZERO
static __inline__ void __FD_ZERO(__kernel_fd_set *p)
{
unsigned int *tmp = (unsigned int *)p->fds_bits;
int i;
if (__builtin_constant_p(__FDSET_LONGS)) {
switch (__FDSET_LONGS) {
case 8:
tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
return;
}
}
i = __FDSET_LONGS;
while (i) {
i--;
*tmp = 0;
tmp++;
}
}
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
#endif /* __GNUC__ */
#endif /* _PPC_POSIX_TYPES_H */

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/*
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _PPC4xx_EBC_H_
#define _PPC4xx_EBC_H_
/*
* Currently there are two register layout versions for the IBM EBC core
* used on 4xx PPC's. The following grouping lists the first layout.
* Within this group there is a slight variation concerning the bit field
* position of the EMPL and EMPH fields:
*/
#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define CONFIG_EBC_PPC4xx_IBM_VER1
#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
defined(CONFIG_405EP)
#define EBC_CFG_EMPH_POS 8
#define EBC_CFG_EMPL_POS 6
#else
#define EBC_CFG_EMPH_POS 6
#define EBC_CFG_EMPL_POS 8
#endif
#endif
/*
* Define the max number of EBC banks (chip selects)
*/
#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_440GP) || defined(CONFIG_440GX)
#define EBC_NUM_BANKS 8
#endif
#if defined(CONFIG_405EP)
#define EBC_NUM_BANKS 5
#endif
#if defined(CONFIG_405EX) || \
defined(CONFIG_460SX)
#define EBC_NUM_BANKS 4
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define EBC_NUM_BANKS 6
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define EBC_NUM_BANKS 3
#endif
/* Bank Configuration Register */
#define EBC_BXCR(n) (n)
#define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17))
#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)
#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)
#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0)
#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1)
#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2)
#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3)
#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4)
#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5)
#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6)
#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7)
#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3)
#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0)
#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1)
#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2)
#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3)
#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3)
#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0)
#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1)
#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2)
#else
#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3)
#endif
/* Bank Access Parameter Register */
#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1)
#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0)
#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF)
#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F)
#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7)
#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0)
#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1)
#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3)
#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0)
#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1)
#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2)
#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3)
#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3)
#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3)
#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3)
#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3)
#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7)
#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1)
#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0)
#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0)
#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1)
#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0)
#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1)
#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0)
#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1)
/* Common fields in EBC0_CFG register */
#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1)
#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0)
#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1)
#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7)
#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0)
#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1)
#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2)
#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3)
#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4)
#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5)
#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6)
#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7)
#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1)
#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0)
#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1)
#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F)
#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F)
/* Now the two versions of the other bits */
#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
#define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1)
#define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0)
#define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1)
#define EBC_CFG_EMPH_MASK PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3)
#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \
(static_cast(u32, n)) & 0x3)
#define EBC_CFG_EMPL_MASK PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3)
#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \
(static_cast(u32, n)) & 0x3)
#define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1)
#define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0)
#define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1)
#define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3)
#define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0)
#define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1)
#define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2)
#define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3)
#define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0)
#define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1)
#define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2)
#else
#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1)
#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0)
#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1)
#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1)
#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0)
#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1)
#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1)
#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0)
#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1)
#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1)
#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0)
#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1)
#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1)
#define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0)
#define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1)
#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1)
#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0)
#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1)
#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3)
#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0)
#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1)
#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2)
#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3)
#endif
#endif /* _PPC4xx_EBC_H_ */

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/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _PPC4xx_ISRAM_H_
#define _PPC4xx_ISRAM_H_
/*
* Internal SRAM
*/
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define ISRAM0_DCR_BASE 0x380
#else
#define ISRAM0_DCR_BASE 0x020
#endif
#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define ISRAM1_DCR_BASE 0x0B0
#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */
#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */
#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */
#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */
#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */
#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
#endif /* CONFIG_460EX || CONFIG_460GT */
/*
* L2 Cache
*/
#if defined (CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
#define L2_CACHE_BASE 0x030
#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */
#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
#endif /* CONFIG_440GX */
#endif /* _PPC4xx_ISRAM_H_ */

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/*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* (C) Copyright 2008-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _PPC4xx_UIC_H_
#define _PPC4xx_UIC_H_
/*
* Define the number of UIC's
*/
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
#define UIC_MAX 4
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define UIC_MAX 3
#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UIC_MAX 2
#else
#define UIC_MAX 1
#endif
#define IRQ_MAX (UIC_MAX * 32)
/*
* UIC register
*/
#define UIC_SR 0x0 /* UIC status */
#define UIC_ER 0x2 /* UIC enable */
#define UIC_CR 0x3 /* UIC critical */
#define UIC_PR 0x4 /* UIC polarity */
#define UIC_TR 0x5 /* UIC triggering */
#define UIC_MSR 0x6 /* UIC masked status */
#define UIC_VR 0x7 /* UIC vector */
#define UIC_VCR 0x8 /* UIC vector configuration */
/*
* On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's
* are cascaded on. With this trick we can use the common UIC code for 440GX
* too.
*/
#if defined(CONFIG_440GX)
#define UIC0_DCR_BASE 0x200
#define UIC1_DCR_BASE 0xc0
#define UIC2_DCR_BASE 0xd0
#define UIC3_DCR_BASE 0x210
#else
#define UIC0_DCR_BASE 0xc0
#define UIC1_DCR_BASE 0xd0
#define UIC2_DCR_BASE 0xe0
#define UIC3_DCR_BASE 0xf0
#endif
#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */
#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */
#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */
#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */
#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */
#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */
#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */
#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */
#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */
#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */
#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */
#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */
#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */
#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
/*
* Now the interrupt vector definitions. They are different for most of
* the 4xx variants, so we need some more #ifdef's here. No mask
* definitions anymore here. For this please use the UIC_MASK macro below.
*
* Note: Please only define the interrupts really used in U-Boot here.
* Those are the cascading and EMAC/MAL related interrupt.
*/
#if defined(CONFIG_405EP) || defined(CONFIG_405GP)
#define VECNUM_MAL_SERR 10
#define VECNUM_MAL_TXEOB 11
#define VECNUM_MAL_RXEOB 12
#define VECNUM_MAL_TXDE 13
#define VECNUM_MAL_RXDE 14
#define VECNUM_ETH0 15
#define VECNUM_ETH1_OFFS 2
#define VECNUM_EIRQ6 29
#endif /* defined(CONFIG_405EP) */
#if defined(CONFIG_405EZ)
#define VECNUM_USBDEV 15
#define VECNUM_ETH0 16
#define VECNUM_MAL_SERR 18
#define VECNUM_MAL_TXDE 18
#define VECNUM_MAL_RXDE 18
#define VECNUM_MAL_TXEOB 19
#define VECNUM_MAL_RXEOB 21
#endif /* CONFIG_405EX */
#if defined(CONFIG_405EX)
/* UIC 0 */
#define VECNUM_MAL_TXEOB 10
#define VECNUM_MAL_RXEOB 11
#define VECNUM_ETH0 24
#define VECNUM_ETH1_OFFS 1
#define VECNUM_UIC2NCI 28
#define VECNUM_UIC2CI 29
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 1 */
#define VECNUM_MAL_SERR (32 + 0)
#define VECNUM_MAL_TXDE (32 + 1)
#define VECNUM_MAL_RXDE (32 + 2)
#endif /* CONFIG_405EX */
#if defined(CONFIG_440GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* UIC 0 */
#define VECNUM_MAL_TXEOB 10
#define VECNUM_MAL_RXEOB 11
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 1 */
#define VECNUM_MAL_SERR (32 + 0)
#define VECNUM_MAL_TXDE (32 + 1)
#define VECNUM_MAL_RXDE (32 + 2)
#define VECNUM_USBDEV (32 + 23)
#define VECNUM_ETH0 (32 + 28)
#define VECNUM_ETH1_OFFS 2
#endif /* CONFIG_440GP */
#if defined(CONFIG_440GX)
/* UICB 0 (440GX only) */
/*
* All those defines below are off-by-one, so that the common UIC code
* can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc.
*/
#define VECNUM_UIC1CI 0
#define VECNUM_UIC1NCI 1
#define VECNUM_UIC2CI 2
#define VECNUM_UIC2NCI 3
#define VECNUM_UIC3CI 4
#define VECNUM_UIC3NCI 5
/* UIC 0, used as UIC1 on 440GX because of UICB0 */
#define VECNUM_MAL_TXEOB (32 + 10)
#define VECNUM_MAL_RXEOB (32 + 11)
/* UIC 1, used as UIC2 on 440GX because of UICB0 */
#define VECNUM_MAL_SERR (64 + 0)
#define VECNUM_MAL_TXDE (64 + 1)
#define VECNUM_MAL_RXDE (64 + 2)
#define VECNUM_ETH0 (64 + 28)
#define VECNUM_ETH1_OFFS 2
#endif /* CONFIG_440GX */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* UIC 0 */
#define VECNUM_MAL_TXEOB 10
#define VECNUM_MAL_RXEOB 11
#define VECNUM_USBDEV 20
#define VECNUM_ETH0 24
#define VECNUM_ETH1_OFFS 1
#define VECNUM_UIC2NCI 28
#define VECNUM_UIC2CI 29
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 1 */
#define VECNUM_MAL_SERR (32 + 0)
#define VECNUM_MAL_TXDE (32 + 1)
#define VECNUM_MAL_RXDE (32 + 2)
/* UIC 2 */
#define VECNUM_EIRQ2 (64 + 3)
#endif /* CONFIG_440EPX */
#if defined(CONFIG_440SP)
/* UIC 0 */
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 1 */
#define VECNUM_MAL_SERR (32 + 1)
#define VECNUM_MAL_TXDE (32 + 2)
#define VECNUM_MAL_RXDE (32 + 3)
#define VECNUM_MAL_TXEOB (32 + 6)
#define VECNUM_MAL_RXEOB (32 + 7)
#define VECNUM_ETH0 (32 + 28)
#endif /* CONFIG_440SP */
#if defined(CONFIG_440SPE)
/* UIC 0 */
#define VECNUM_UIC2NCI 10
#define VECNUM_UIC2CI 11
#define VECNUM_UIC3NCI 16
#define VECNUM_UIC3CI 17
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 1 */
#define VECNUM_MAL_SERR (32 + 1)
#define VECNUM_MAL_TXDE (32 + 2)
#define VECNUM_MAL_RXDE (32 + 3)
#define VECNUM_MAL_TXEOB (32 + 6)
#define VECNUM_MAL_RXEOB (32 + 7)
#define VECNUM_ETH0 (32 + 28)
#endif /* CONFIG_440SPE */
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
/* UIC 0 */
#define VECNUM_UIC2NCI 10
#define VECNUM_UIC2CI 11
#define VECNUM_UIC3NCI 16
#define VECNUM_UIC3CI 17
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 2 */
#define VECNUM_MAL_SERR (64 + 3)
#define VECNUM_MAL_TXDE (64 + 4)
#define VECNUM_MAL_RXDE (64 + 5)
#define VECNUM_MAL_TXEOB (64 + 6)
#define VECNUM_MAL_RXEOB (64 + 7)
#define VECNUM_ETH0 (64 + 16)
#define VECNUM_ETH1_OFFS 1
#endif /* CONFIG_460EX */
#if defined(CONFIG_460SX)
/* UIC 0 */
#define VECNUM_UIC2NCI 10
#define VECNUM_UIC2CI 11
#define VECNUM_UIC3NCI 16
#define VECNUM_UIC3CI 17
#define VECNUM_ETH0 19
#define VECNUM_ETH1_OFFS 1
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 1 */
#define VECNUM_MAL_SERR (32 + 1)
#define VECNUM_MAL_TXDE (32 + 2)
#define VECNUM_MAL_RXDE (32 + 3)
#define VECNUM_MAL_TXEOB (32 + 6)
#define VECNUM_MAL_RXEOB (32 + 7)
#endif /* CONFIG_460EX */
#if !defined(VECNUM_ETH1_OFFS)
#define VECNUM_ETH1_OFFS 1
#endif
/*
* Mask definitions (used for example in 4xx_enet.c)
*/
#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
#define UIC_NR(vec) ((vec) >> 5)
#endif /* _PPC4xx_UIC_H_ */

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/*
* (C) Copyright 2008-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2009
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __PPC4xx_CONFIG_H
#define __PPC4xx_CONFIG_H
#include <common.h>
struct ppc4xx_config {
char label[16];
char description[64];
u8 val[CONFIG_4xx_CONFIG_BLOCKSIZE];
};
extern struct ppc4xx_config ppc4xx_config_val[];
extern int ppc4xx_config_count;
#endif /* __PPC4xx_CONFIG_H */

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#ifndef _PPC_PTRACE_H
#define _PPC_PTRACE_H
/*
* This struct defines the way the registers are stored on the
* kernel stack during a system call or other kernel entry.
*
* this should only contain volatile regs
* since we can keep non-volatile in the thread_struct
* should set this up when only volatiles are saved
* by intr code.
*
* Since this is going on the stack, *CARE MUST BE TAKEN* to insure
* that the overall structure is a multiple of 16 bytes in length.
*
* Note that the offsets of the fields in this struct correspond with
* the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
*/
#include <linux/config.h>
#ifndef __ASSEMBLY__
#ifdef CONFIG_PPC64BRIDGE
#define PPC_REG unsigned long /*long*/
#else
#define PPC_REG unsigned long
#endif
struct pt_regs {
PPC_REG gpr[32];
PPC_REG nip;
PPC_REG msr;
PPC_REG orig_gpr3; /* Used for restarting system calls */
PPC_REG ctr;
PPC_REG link;
PPC_REG xer;
PPC_REG ccr;
PPC_REG mq; /* 601 only (not used at present) */
/* Used on APUS to hold IPL value. */
PPC_REG trap; /* Reason for being here */
PPC_REG dar; /* Fault registers */
PPC_REG dsisr;
PPC_REG result; /* Result of a system call */
};
#endif
#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
/* Size of stack frame allocated when calling signal handler. */
#define __SIGNAL_FRAMESIZE 64
#define instruction_pointer(regs) ((regs)->nip)
#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
/*
* Offsets used by 'ptrace' system call interface.
* These can't be changed without breaking binary compatibility
* with MkLinux, etc.
*/
#define PT_R0 0
#define PT_R1 1
#define PT_R2 2
#define PT_R3 3
#define PT_R4 4
#define PT_R5 5
#define PT_R6 6
#define PT_R7 7
#define PT_R8 8
#define PT_R9 9
#define PT_R10 10
#define PT_R11 11
#define PT_R12 12
#define PT_R13 13
#define PT_R14 14
#define PT_R15 15
#define PT_R16 16
#define PT_R17 17
#define PT_R18 18
#define PT_R19 19
#define PT_R20 20
#define PT_R21 21
#define PT_R22 22
#define PT_R23 23
#define PT_R24 24
#define PT_R25 25
#define PT_R26 26
#define PT_R27 27
#define PT_R28 28
#define PT_R29 29
#define PT_R30 30
#define PT_R31 31
#define PT_NIP 32
#define PT_MSR 33
#ifdef __KERNEL__
#define PT_ORIG_R3 34
#endif
#define PT_CTR 35
#define PT_LNK 36
#define PT_XER 37
#define PT_CCR 38
#define PT_MQ 39
#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
#define PT_FPR31 (PT_FPR0 + 2*31)
#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
#endif

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/* 7/18/95 */
/*----------------------------------------------------------------------------*/
/* Residual Data header definitions and prototypes */
/*----------------------------------------------------------------------------*/
/* Structure map for RESIDUAL on PowerPC Reference Platform */
/* residual.h - Residual data structure passed in r3. */
/* Load point passed in r4 to boot image. */
/* For enum's: if given in hex then they are bit significant, */
/* i.e. only one bit is on for each enum */
/* Reserved fields must be filled with zeros. */
#ifndef _RESIDUAL_
#define _RESIDUAL_
#ifndef __ASSEMBLY__
#define MAX_CPUS 32 /* These should be set to the maximum */
#define MAX_MEMS 64 /* number possible for this system. */
#define MAX_DEVICES 256 /* Changing these will change the */
#define AVE_PNP_SIZE 32 /* structure, hence the version of */
#define MAX_MEM_SEGS 64 /* this header file. */
/*----------------------------------------------------------------------------*/
/* Public structures... */
/*----------------------------------------------------------------------------*/
#include "pnp.h"
typedef enum _L1CACHE_TYPE {
NoneCAC = 0,
SplitCAC = 1,
CombinedCAC = 2
} L1CACHE_TYPE;
typedef enum _TLB_TYPE {
NoneTLB = 0,
SplitTLB = 1,
CombinedTLB = 2
} TLB_TYPE;
typedef enum _FIRMWARE_SUPPORT {
Conventional = 0x01,
OpenFirmware = 0x02,
Diagnostics = 0x04,
LowDebug = 0x08,
Multiboot = 0x10,
LowClient = 0x20,
Hex41 = 0x40,
FAT = 0x80,
ISO9660 = 0x0100,
SCSI_InitiatorID_Override = 0x0200,
Tape_Boot = 0x0400,
FW_Boot_Path = 0x0800
} FIRMWARE_SUPPORT;
typedef enum _FIRMWARE_SUPPLIERS {
IBMFirmware = 0x00,
MotoFirmware = 0x01, /* 7/18/95 */
FirmWorks = 0x02, /* 10/5/95 */
Bull = 0x03, /* 04/03/96 */
} FIRMWARE_SUPPLIERS;
typedef enum _ENDIAN_SWITCH_METHODS {
UsePort92 = 0x01,
UsePCIConfigA8 = 0x02,
UseFF001030 = 0x03,
} ENDIAN_SWITCH_METHODS;
typedef enum _SPREAD_IO_METHODS {
UsePort850 = 0x00,
/*UsePCIConfigA8 = 0x02,*/
} SPREAD_IO_METHODS;
typedef struct _VPD {
/* Box dependent stuff */
unsigned char PrintableModel[32]; /* Null terminated string.
Must be of the form:
vvv,<20h>,<model designation>,<0x0>
where vvv is the vendor ID
e.g. IBM PPS MODEL 6015<0x0> */
unsigned char Serial[16]; /* 12/94:
Serial Number; must be of the form:
vvv<serial number> where vvv is the
vendor ID.
e.g. IBM60151234567<20h><20h> */
unsigned char Reserved[48];
unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */
unsigned long FirmwareSupports; /* See FirmwareSupport enum */
unsigned long NvramSize; /* Size of nvram in bytes */
unsigned long NumSIMMSlots;
unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */
unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */
unsigned long SmpIar;
unsigned long RAMErrLogOffset; /* Heap offset to error log */
unsigned long Reserved5;
unsigned long Reserved6;
unsigned long ProcessorHz; /* Processor clock frequency in Hertz */
unsigned long ProcessorBusHz; /* Processor bus clock frequency */
unsigned long Reserved7;
unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */
unsigned long WordWidth; /* Word width in bits */
unsigned long PageSize; /* Page size in bytes */
unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache
for which coherency is maintained;
normally <= CacheLineSize. */
unsigned long GranuleSize; /* Unit of lock allocation to avoid */
/* false sharing of locks. */
/* L1 Cache variables */
unsigned long CacheSize; /* L1 Cache size in KB. This is the */
/* total size of the L1, whether */
/* combined or split */
unsigned long CacheAttrib; /* L1CACHE_TYPE */
unsigned long CacheAssoc; /* L1 Cache associativity. Use this
for combined cache. If split, put
zeros here. */
unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use
for combined cache. If split, put
zeros here. */
/* For split L1 Cache: (= combined if combined cache) */
unsigned long I_CacheSize;
unsigned long I_CacheAssoc;
unsigned long I_CacheLineSize;
unsigned long D_CacheSize;
unsigned long D_CacheAssoc;
unsigned long D_CacheLineSize;
/* Translation Lookaside Buffer variables */
unsigned long TLBSize; /* Total number of TLBs on the system */
unsigned long TLBAttrib; /* Combined I+D or split TLB */
unsigned long TLBAssoc; /* TLB Associativity. Use this for
combined TLB. If split, put zeros
here. */
/* For split TLB: (= combined if combined TLB) */
unsigned long I_TLBSize;
unsigned long I_TLBAssoc;
unsigned long D_TLBSize;
unsigned long D_TLBAssoc;
unsigned long ExtendedVPD; /* Offset to extended VPD area;
null if unused */
} VPD;
typedef enum _DEVICE_FLAGS {
Enabled = 0x4000, /* 1 - PCI device is enabled */
Integrated = 0x2000,
Failed = 0x1000, /* 1 - device failed POST code tests */
Static = 0x0800, /* 0 - dynamically configurable
1 - static */
Dock = 0x0400, /* 0 - not a docking station device
1 - is a docking station device */
Boot = 0x0200, /* 0 - device cannot be used for BOOT
1 - can be a BOOT device */
Configurable = 0x0100, /* 1 - device is configurable */
Disableable = 0x80, /* 1 - device can be disabled */
PowerManaged = 0x40, /* 0 - not managed; 1 - managed */
ReadOnly = 0x20, /* 1 - device is read only */
Removable = 0x10, /* 1 - device is removable */
ConsoleIn = 0x08,
ConsoleOut = 0x04,
Input = 0x02,
Output = 0x01
} DEVICE_FLAGS;
typedef enum _BUS_ID {
ISADEVICE = 0x01,
EISADEVICE = 0x02,
PCIDEVICE = 0x04,
PCMCIADEVICE = 0x08,
PNPISADEVICE = 0x10,
MCADEVICE = 0x20,
MXDEVICE = 0x40, /* Devices on mezzanine bus */
PROCESSORDEVICE = 0x80, /* Devices on processor bus */
VMEDEVICE = 0x100,
} BUS_ID;
typedef struct _DEVICE_ID {
unsigned long BusId; /* See BUS_ID enum above */
unsigned long DevId; /* Big Endian format */
unsigned long SerialNum; /* For multiple usage of a single
DevId */
unsigned long Flags; /* See DEVICE_FLAGS enum above */
unsigned char BaseType; /* See pnp.h for bit definitions */
unsigned char SubType; /* See pnp.h for bit definitions */
unsigned char Interface; /* See pnp.h for bit definitions */
unsigned char Spare;
} DEVICE_ID;
typedef union _BUS_ACCESS {
struct _PnPAccess{
unsigned char CSN;
unsigned char LogicalDevNumber;
unsigned short ReadDataPort;
} PnPAccess;
struct _ISAAccess{
unsigned char SlotNumber; /* ISA Slot Number generally not
available; 0 if unknown */
unsigned char LogicalDevNumber;
unsigned short ISAReserved;
} ISAAccess;
struct _MCAAccess{
unsigned char SlotNumber;
unsigned char LogicalDevNumber;
unsigned short MCAReserved;
} MCAAccess;
struct _PCMCIAAccess{
unsigned char SlotNumber;
unsigned char LogicalDevNumber;
unsigned short PCMCIAReserved;
} PCMCIAAccess;
struct _EISAAccess{
unsigned char SlotNumber;
unsigned char FunctionNumber;
unsigned short EISAReserved;
} EISAAccess;
struct _PCIAccess{
unsigned char BusNumber;
unsigned char DevFuncNumber;
unsigned short PCIReserved;
} PCIAccess;
struct _ProcBusAccess{
unsigned char BusNumber;
unsigned char BUID;
unsigned short ProcBusReserved;
} ProcBusAccess;
} BUS_ACCESS;
/* Per logical device information */
typedef struct _PPC_DEVICE {
DEVICE_ID DeviceId;
BUS_ACCESS BusAccess;
/* The following three are offsets into the DevicePnPHeap */
/* All are in PnP compressed format */
unsigned long AllocatedOffset; /* Allocated resource description */
unsigned long PossibleOffset; /* Possible resource description */
unsigned long CompatibleOffset; /* Compatible device identifiers */
} PPC_DEVICE;
typedef enum _CPU_STATE {
CPU_GOOD = 0, /* CPU is present, and active */
CPU_GOOD_FW = 1, /* CPU is present, and in firmware */
CPU_OFF = 2, /* CPU is present, but inactive */
CPU_FAILED = 3, /* CPU is present, but failed POST */
CPU_NOT_PRESENT = 255 /* CPU not present */
} CPU_STATE;
typedef struct _PPC_CPU {
unsigned long CpuType; /* Result of mfspr from Processor
Version Register (PVR).
PVR(0-15) = Version (e.g. 601)
PVR(16-31 = EC Level */
unsigned char CpuNumber; /* CPU Number for this processor */
unsigned char CpuState; /* CPU State, see CPU_STATE enum */
unsigned short Reserved;
} PPC_CPU;
typedef struct _PPC_MEM {
unsigned long SIMMSize; /* 0 - absent or bad
8M, 32M (in MB) */
} PPC_MEM;
typedef enum _MEM_USAGE {
Other = 0x8000,
ResumeBlock = 0x4000, /* for use by power management */
SystemROM = 0x2000, /* Flash memory (populated) */
UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */
IOMemory = 0x0800,
SystemIO = 0x0400,
SystemRegs = 0x0200,
PCIAddr = 0x0100,
PCIConfig = 0x80,
ISAAddr = 0x40,
Unpopulated = 0x20, /* Unpopulated part of System Memory */
Free = 0x10, /* Free part of System Memory */
BootImage = 0x08, /* BootImage part of System Memory */
FirmwareCode = 0x04, /* FirmwareCode part of System Memory */
FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */
FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/
} MEM_USAGE;
typedef struct _MEM_MAP {
unsigned long Usage; /* See MEM_USAGE above */
unsigned long BasePage; /* Page number measured in 4KB pages */
unsigned long PageCount; /* Page count measured in 4KB pages */
} MEM_MAP;
typedef struct _RESIDUAL {
unsigned long ResidualLength; /* Length of Residual */
unsigned char Version; /* of this data structure */
unsigned char Revision; /* of this data structure */
unsigned short EC; /* of this data structure */
/* VPD */
VPD VitalProductData;
/* CPU */
unsigned short MaxNumCpus; /* Max CPUs in this system */
unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */
/* that there are unpopulated or */
/* otherwise unusable cpu locations */
PPC_CPU Cpus[MAX_CPUS];
/* Memory */
unsigned long TotalMemory; /* Total amount of memory installed */
unsigned long GoodMemory; /* Total amount of good memory */
unsigned long ActualNumMemSegs;
MEM_MAP Segs[MAX_MEM_SEGS];
unsigned long ActualNumMemories;
PPC_MEM Memories[MAX_MEMS];
/* Devices */
unsigned long ActualNumDevices;
PPC_DEVICE Devices[MAX_DEVICES];
unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
} RESIDUAL;
extern RESIDUAL *res;
extern void print_residual_device_info(void);
extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
unsigned char * DevID, int BaseType,
int SubType, int Interface, int n);
extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
int n);
extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
unsigned packet_type,
int n);
extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
unsigned packet_type,
int n);
#endif /* __ASSEMBLY__ */
#endif /* ndef _RESIDUAL_ */

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#ifndef _ASM_PPC_SIGCONTEXT_H
#define _ASM_PPC_SIGCONTEXT_H
#include <asm/ptrace.h>
struct sigcontext_struct {
unsigned long _unused[4];
int signal;
unsigned long handler;
unsigned long oldmask;
struct pt_regs *regs;
};
#endif

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#ifndef _ASMPPC_SIGNAL_H
#define _ASMPPC_SIGNAL_H
#include <linux/types.h>
/* Avoid too many header ordering problems. */
struct siginfo;
/* Most things should be clean enough to redefine this at will, if care
is taken to make libc match. */
#define _NSIG 64
#define _NSIG_BPW 32
#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
typedef unsigned long old_sigset_t; /* at least 32 bits */
typedef struct {
unsigned long sig[_NSIG_WORDS];
} sigset_t;
#define SIGHUP 1
#define SIGINT 2
#define SIGQUIT 3
#define SIGILL 4
#define SIGTRAP 5
#define SIGABRT 6
#define SIGIOT 6
#define SIGBUS 7
#define SIGFPE 8
#define SIGKILL 9
#define SIGUSR1 10
#define SIGSEGV 11
#define SIGUSR2 12
#define SIGPIPE 13
#define SIGALRM 14
#define SIGTERM 15
#define SIGSTKFLT 16
#define SIGCHLD 17
#define SIGCONT 18
#define SIGSTOP 19
#define SIGTSTP 20
#define SIGTTIN 21
#define SIGTTOU 22
#define SIGURG 23
#define SIGXCPU 24
#define SIGXFSZ 25
#define SIGVTALRM 26
#define SIGPROF 27
#define SIGWINCH 28
#define SIGIO 29
#define SIGPOLL SIGIO
/*
#define SIGLOST 29
*/
#define SIGPWR 30
#define SIGSYS 31
#define SIGUNUSED 31
/* These should not be considered constants from userland. */
#define SIGRTMIN 32
#define SIGRTMAX (_NSIG-1)
/*
* SA_FLAGS values:
*
* SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
* SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
* SA_RESTART flag to get restarting signals (which were the default long ago)
* SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
* SA_RESETHAND clears the handler when the signal is delivered.
* SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
* SA_NODEFER prevents the current signal from being masked in the handler.
*
* SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
* Unix names RESETHAND and NODEFER respectively.
*/
#define SA_NOCLDSTOP 0x00000001
#define SA_NOCLDWAIT 0x00000002 /* not supported yet */
#define SA_SIGINFO 0x00000004
#define SA_ONSTACK 0x08000000
#define SA_RESTART 0x10000000
#define SA_NODEFER 0x40000000
#define SA_RESETHAND 0x80000000
#define SA_NOMASK SA_NODEFER
#define SA_ONESHOT SA_RESETHAND
#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */
#define SA_RESTORER 0x04000000
/*
* sigaltstack controls
*/
#define SS_ONSTACK 1
#define SS_DISABLE 2
#define MINSIGSTKSZ 2048
#define SIGSTKSZ 8192
#ifdef __KERNEL__
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
* SA_SHIRQ is for shared interrupt support on PCI and EISA.
*/
#define SA_PROBE SA_ONESHOT
#define SA_SAMPLE_RANDOM SA_RESTART
#define SA_SHIRQ 0x04000000
#endif
#define SIG_BLOCK 0 /* for blocking signals */
#define SIG_UNBLOCK 1 /* for unblocking signals */
#define SIG_SETMASK 2 /* for setting the signal mask */
/* Type of a signal handler. */
typedef void (*__sighandler_t)(int);
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
struct old_sigaction {
__sighandler_t sa_handler;
old_sigset_t sa_mask;
unsigned long sa_flags;
void (*sa_restorer)(void);
};
struct sigaction {
__sighandler_t sa_handler;
unsigned long sa_flags;
void (*sa_restorer)(void);
sigset_t sa_mask; /* mask last for extensibility */
};
struct k_sigaction {
struct sigaction sa;
};
typedef struct sigaltstack {
void *ss_sp;
int ss_flags;
size_t ss_size;
} stack_t;
#ifdef __KERNEL__
#include <asm/sigcontext.h>
#endif
#endif

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/*
* asm/status_led.h
*
* MPC8xx/MPC8260/MPC5xx based status led support functions
*/
#ifndef __ASM_STATUS_LED_H__
#define __ASM_STATUS_LED_H__
/* if not overriden */
#ifndef CONFIG_BOARD_SPECIFIC_LED
# if defined(CONFIG_8xx)
# include <mpc8xx.h>
# elif defined(CONFIG_8260)
# include <mpc8260.h>
# elif defined(CONFIG_5xx)
# include <mpc5xx.h>
# else
# error CPU specific Status LED header file missing.
#endif
/* led_id_t is unsigned long mask */
typedef unsigned long led_id_t;
static inline void __led_init (led_id_t mask, int state)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#ifdef STATUS_LED_PAR
immr->STATUS_LED_PAR &= ~mask;
#endif
#ifdef STATUS_LED_ODR
immr->STATUS_LED_ODR &= ~mask;
#endif
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
immr->STATUS_LED_DAT &= ~mask;
else
immr->STATUS_LED_DAT |= mask;
#else
if (state == STATUS_LED_ON)
immr->STATUS_LED_DAT |= mask;
else
immr->STATUS_LED_DAT &= ~mask;
#endif
#ifdef STATUS_LED_DIR
immr->STATUS_LED_DIR |= mask;
#endif
}
static inline void __led_toggle (led_id_t mask)
{
((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask;
}
static inline void __led_set (led_id_t mask, int state)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
immr->STATUS_LED_DAT &= ~mask;
else
immr->STATUS_LED_DAT |= mask;
#else
if (state == STATUS_LED_ON)
immr->STATUS_LED_DAT |= mask;
else
immr->STATUS_LED_DAT &= ~mask;
#endif
}
#endif
#endif /* __ASM_STATUS_LED_H__ */

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#ifndef _PPC_STRING_H_
#define _PPC_STRING_H_
#define __HAVE_ARCH_STRCPY
#define __HAVE_ARCH_STRNCPY
#define __HAVE_ARCH_STRLEN
#define __HAVE_ARCH_STRCMP
#define __HAVE_ARCH_STRCAT
#define __HAVE_ARCH_MEMSET
#define __HAVE_ARCH_BCOPY
#define __HAVE_ARCH_MEMCPY
#define __HAVE_ARCH_MEMMOVE
#define __HAVE_ARCH_MEMCMP
#define __HAVE_ARCH_MEMCHR
extern int strcasecmp(const char *, const char *);
extern int strncasecmp(const char *, const char *, int);
extern char * strcpy(char *,const char *);
extern char * strncpy(char *,const char *, __kernel_size_t);
extern __kernel_size_t strlen(const char *);
extern int strcmp(const char *,const char *);
extern char * strcat(char *, const char *);
extern void * memset(void *,int,__kernel_size_t);
extern void * memcpy(void *,const void *,__kernel_size_t);
extern void * memmove(void *,const void *,__kernel_size_t);
extern int memcmp(const void *,const void *,__kernel_size_t);
extern void * memchr(const void *,int,__kernel_size_t);
#endif

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#ifndef _PPC_TYPES_H
#define _PPC_TYPES_H
#ifndef __ASSEMBLY__
typedef unsigned short umode_t;
typedef __signed__ char __s8;
typedef unsigned char __u8;
typedef __signed__ short __s16;
typedef unsigned short __u16;
typedef __signed__ int __s32;
typedef unsigned int __u32;
#if defined(__GNUC__)
__extension__ typedef __signed__ long long __s64;
__extension__ typedef unsigned long long __u64;
#endif
typedef struct {
__u32 u[4];
} __attribute__((aligned(16))) vector128;
#ifdef __KERNEL__
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
typedef signed char s8;
typedef unsigned char u8;
typedef signed short s16;
typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
#define BITS_PER_LONG 32
/* DMA addresses are 32-bits wide */
typedef u32 dma_addr_t;
#ifdef CONFIG_PHYS_64BIT
typedef unsigned long long phys_addr_t;
typedef unsigned long long phys_size_t;
#else
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
#endif
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif

146
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/*
* (C) Copyright 2000 - 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************
* NOTE: This header file defines an interface to U-Boot. Including
* this (unmodified) header file in another file is considered normal
* use of U-Boot, and does *not* fall under the heading of "derived
* work".
********************************************************************
*/
#ifndef __U_BOOT_H__
#define __U_BOOT_H__
/*
* Board information passed to Linux kernel from U-Boot
*
* include/asm-ppc/u-boot.h
*/
#ifndef __ASSEMBLY__
typedef struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long bi_mbar_base; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
unsigned long bi_immrbar;
#endif
#if defined(CONFIG_MPC8220)
unsigned long bi_mbar_base; /* base of internal registers */
unsigned long bi_inpfreq; /* Input Freq, In MHz */
unsigned long bi_pcifreq; /* PCI Freq, in MHz */
unsigned long bi_pevfreq; /* PEV Freq, in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */
unsigned long bi_vcofreq; /* VCO Freq, in MHz */
#endif
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
#if defined(CONFIG_CPM2)
unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
unsigned long bi_vco; /* VCO Out from PLL, in MHz */
#endif
#if defined(CONFIG_MPC512X)
unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC5xxx)
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
unsigned long bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || \
defined(CONFIG_440)
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
#endif
#if defined(CONFIG_HYMOD)
hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
#ifdef CONFIG_HAS_ETH1
unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */
#endif
#ifdef CONFIG_HAS_ETH2
unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */
#endif
#ifdef CONFIG_HAS_ETH3
unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */
#endif
#ifdef CONFIG_HAS_ETH4
unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */
#endif
#ifdef CONFIG_HAS_ETH5
unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
unsigned int bi_opbfreq; /* OPB clock in Hz */
int bi_iic_fast[2]; /* Use fast i2c mode */
#endif
#if defined(CONFIG_NX823)
unsigned char bi_sernum[8];
#endif
#if defined(CONFIG_4xx)
#if defined(CONFIG_440GX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
int bi_phynum[4]; /* Determines phy mapping */
int bi_phymode[4]; /* Determines phy mode */
#elif defined(CONFIG_405EP) || defined(CONFIG_440)
int bi_phynum[2]; /* Determines phy mapping */
int bi_phymode[2]; /* Determines phy mode */
#else
int bi_phynum[1]; /* Determines phy mapping */
int bi_phymode[1]; /* Determines phy mode */
#endif
#endif /* defined(CONFIG_4xx) */
} bd_t;
#endif /* __ASSEMBLY__ */
#endif /* __U_BOOT_H__ */

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#ifndef _ASM_POWERPC_UNALIGNED_H
#define _ASM_POWERPC_UNALIGNED_H
#ifdef __KERNEL__
/*
* The PowerPC can do unaligned accesses itself in big endian mode.
*/
#include <linux/unaligned/access_ok.h>
#include <linux/unaligned/generic.h>
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_UNALIGNED_H */

36
arch/powerpc/include/asm/xilinx_irq.h Normal file
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/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef XILINX_IRQ_H
#define XILINX_IRQ_H
#define intc XPAR_INTC_0_BASEADDR
#define ISR (intc + (0 * 4)) /* Interrupt Status Register */
#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
#define IER (intc + (2 * 4)) /* Interrupt Enable Register */
#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
#define MER (intc + (7 * 4)) /* Master Enable Register */
#define IRQ_MASK(irq) (1 << (irq & 0x1f))
#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
#endif