mpc512x: Adjust the DRAM init sequence to the datasheet spec

Do maintain a 200 usecs period of stable power and clock before
asserting the CKE signal and sending commands, have at least 200
DRAM clock cycles pass after initialization before data access.

Signed-off-by: Anatolij Gustschin <agust@denx.de>

arch/powerpc/include/asm/immap_512x.h

@@ -351,6 +351,7 @@ typedef struct ddr512x {
 
 /* MDDRC SYS CFG and Timing CFG0 Registers */
 #define MDDRC_SYS_CFG_EN	0xF0000000
+#define MDDRC_SYS_CFG_CKE_MASK	0x40000000
 #define MDDRC_SYS_CFG_CMD_MASK	0x10000000
 #define MDDRC_REFRESH_ZERO_MASK	0x0000FFFF