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clk: mediatek: mt7622: add missing clock PERI_UART4_PD

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Add missing clock PERI_UART4_PD for peri clock gates. This is needed to
match upstream linux clk ID in preparation for OF_UPSTREAM.
Also convert infracfg to mux + gate implementation as now we have mux on
top of gates.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi
2024-08-03 10:43:24 +02:00
committed by Tom Rini
parent a942c0c3f5
commit a776493f4b
2 changed files with 14 additions and 12 deletions
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1
drivers/clk/mediatek/clk-mt7622.c
View File

@@ -472,6 +472,7 @@ static const struct mtk_gate peri_cgs[] = {
GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
GATE_PERI0(CLK_PERI_UART4_PD, CLK_TOP_AXI_SEL, 21),
GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),

25
include/dt-bindings/clock/mt7622-clk.h
View File

@@ -146,18 +146,19 @@
#define CLK_PERI_UART1_PD 13
#define CLK_PERI_UART2_PD 14
#define CLK_PERI_UART3_PD 15
#define CLK_PERI_BTIF_PD 16
#define CLK_PERI_I2C0_PD 17
#define CLK_PERI_I2C1_PD 18
#define CLK_PERI_I2C2_PD 19
#define CLK_PERI_SPI1_PD 20
#define CLK_PERI_AUXADC_PD 21
#define CLK_PERI_SPI0_PD 22
#define CLK_PERI_SNFI_PD 23
#define CLK_PERI_NFI_PD 24
#define CLK_PERI_NFIECC_PD 25
#define CLK_PERI_FLASH_PD 26
#define CLK_PERI_IRTX_PD 27
#define CLK_PERI_UART4_PD 16
#define CLK_PERI_BTIF_PD 17
#define CLK_PERI_I2C0_PD 18
#define CLK_PERI_I2C1_PD 19
#define CLK_PERI_I2C2_PD 20
#define CLK_PERI_SPI1_PD 21
#define CLK_PERI_AUXADC_PD 22
#define CLK_PERI_SPI0_PD 23
#define CLK_PERI_SNFI_PD 24
#define CLK_PERI_NFI_PD 25
#define CLK_PERI_NFIECC_PD 26
#define CLK_PERI_FLASH_PD 27
#define CLK_PERI_IRTX_PD 28
/* APMIXEDSYS */