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doc: device-tree-bindings: alignment with v5.2-rc6 for spi-stm32-qspi.txt

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Align doc/device-tree-bindings/spi/spi-stm32-qspi.txt with kernel v5.2-rc6

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard
2019-06-28 15:03:01 +02:00
committed by Patrick Delaunay
parent 637e288dc7
commit a9afaa42ee
1 changed files with 37 additions and 32 deletions
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69
doc/device-tree-bindings/spi/spi-stm32-qspi.txt
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@@ -1,39 +1,44 @@
STM32 QSPI controller device tree bindings * STMicroelectronics Quad Serial Peripheral Interface(QSPI)
--------------------------------------------
Required properties: Required properties:
- compatible : should be "st,stm32-qspi". - compatible: should be "st,stm32f469-qspi"
- reg : 1. Physical base address and size of SPI registers map. - reg: the first contains the register location and length.
2. Physical base address & size of mapped NOR Flash. the second contains the memory mapping address and length
- spi-max-frequency : Max supported spi frequency. - reg-names: should contain the reg names "qspi" "qspi_mm"
- status : enable in requried dts. - interrupts: should contain the interrupt for the device
- clocks: the phandle of the clock needed by the QSPI controller
- A pinctrl must be defined to set pins in mode of operation for QSPI transfer
Connected flash properties Optional properties:
-------------------------- - resets: must contain the phandle to the reset controller.
- spi-max-frequency : Max supported spi frequency.
- spi-tx-bus-width : Bus width (number of lines) for writing (1-4) A spi flash (NOR/NAND) must be a child of spi node and could have some
- spi-rx-bus-width : Bus width (number of lines) for reading (1-4) properties. Also see jedec,spi-nor.txt.
- memory-map : Address and size for memory-mapping the flash
Required properties:
- reg: chip-Select number (QSPI controller may connect 2 flashes)
- spi-max-frequency: max frequency of spi bus
Optional property:
- spi-rx-bus-width: see ./spi-bus.txt for the description
Example: Example:
qspi: quadspi@A0001000 {
compatible = "st,stm32-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <92>;
spi-max-frequency = <108000000>;
status = "okay";
qflash0: n25q128a { qspi: spi@a0001000 {
#address-cells = <1>; compatible = "st,stm32f469-qspi";
#size-cells = <1>; reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
compatible = "micron,n25q128a13", "jedec,spi-nor"; reg-names = "qspi", "qspi_mm";
spi-max-frequency = <108000000>; interrupts = <91>;
spi-tx-bus-width = <4>; resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
spi-rx-bus-width = <4>; clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
memory-map = <0x90000000 0x1000000>; pinctrl-names = "default";
reg = <0>; pinctrl-0 = <&pinctrl_qspi0>;
};
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
...
}; };
};