From 1f140fefa63b399785528e9a6503f7e0a75f3315 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 5 May 2025 16:47:18 +0200 Subject: [PATCH 01/28] rockchip: rk3399: do not generate u-boot.rom anymore This was only used on RK3399 Gru Chromebooks and their maintainer (Simon) agreed[1] to its removal on the basis that the generic u-boot-rockchip-spi.bin is now enough, so let's do that. At the same time, remove HAS_ROM symbol from the Gru Chromebooks config since they were used only for that. Make sure u-boot-rockchip-spi.bin has the same size of u-boot.rom for Chromebooks as that seems to be important. [1] https://lore.kernel.org/u-boot/CAFLszTh-SewFod8dEOF3+e-wCE1qFF0CyxxR8CbQwy3BRW3k6w@mail.gmail.com/ Reviewed-by: Jonas Karlman Reviewed-by: Kever Yang Tested-by: Simon Glass # chromebook-kevin Signed-off-by: Quentin Schulz --- arch/arm/dts/rk3399-gru-u-boot.dtsi | 4 ++- arch/arm/dts/rk3399-u-boot.dtsi | 35 --------------------------- arch/arm/mach-rockchip/rk3399/Kconfig | 2 -- 3 files changed, 3 insertions(+), 38 deletions(-) diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 5517176aa4a..dfc7be4c621 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -15,11 +15,13 @@ }; }; +#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) &binman { - rom { + simple-bin-spi { size = <0x800000>; }; }; +#endif &cros_ec { ec-interrupt = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 70f35b6c197..587eef9504e 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -29,41 +29,6 @@ }; }; -#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM) -&binman { - multiple-images; - rom { - filename = "u-boot.rom"; - size = <0x400000>; - pad-byte = <0xff>; - - mkimage { - args = "-n rk3399 -T rkspi"; - multiple-data-files; -#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL - rockchip-tpl { - }; -#elif defined(CONFIG_TPL) - u-boot-tpl { - }; -#endif - u-boot-spl { - }; - }; - fit { - type = "blob"; - filename = "u-boot.itb"; - offset = ; - }; - u-boot { - offset = <0x300000>; - }; - fdtmap { - }; - }; -}; -#endif /* CONFIG_ROCKCHIP_SPI_IMAGE && CONFIG_HAS_ROM */ - &cru { bootph-all; }; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index b2430207ee9..5c21b08a5ae 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -5,7 +5,6 @@ choice config TARGET_CHROMEBOOK_BOB bool "Asus Flip C101PA Chromebook (RK3399)" - select HAS_ROM select ROCKCHIP_SPI_IMAGE help Bob is a small RK3299-based device similar in apperance to Minnie. @@ -16,7 +15,6 @@ config TARGET_CHROMEBOOK_BOB config TARGET_CHROMEBOOK_KEVIN bool "Samsung Chromebook Plus (RK3399)" - select HAS_ROM select ROCKCHIP_SPI_IMAGE help Kevin is a RK3399-based convertible chromebook. It has two USB 3.0 From f9b4d051a7357e7da7b2262f8719c555573b0b31 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 5 May 2025 16:47:19 +0200 Subject: [PATCH 02/28] rockchip: rk3288: do not generate u-boot.rom anymore This was only used on RK3288 Chromebooks and the EVB. If it follows the same pattern as for RK3399 Chromebooks where their maintainer (Simon) agreed[1] to removal of u-boot.rom on the basis that the generic u-boot-rockchip-spi.bin is now enough, let's do the same for RK3288 and remove the last Rockchip users of u-boot.rom (and HAS_ROM symbol). At the same time, remove HAS_ROM symbol from the RK3288 Chromebooks and EVB configs since they were used only for that. SYS_SPI_U_BOOT_OFFS offset in rockchip-u-boot.dtsi for the u-boot-img node of simple-bin-spi binman image matches the one used in u-boot.rom except for the EVB. The EVB doesn't have ROCKCHIP_SPI_IMAGE symbol enabled, so HAS_ROM had no effect anyway. Even if it had, this would not have been enough considering that SPL_SPI_LOAD symbol is not set, so U-Boot proper could not be loaded from SPI even if SPL/TPL does. Make sure u-boot-rockchip-spi.bin has the same size of u-boot.rom for Chromebooks as that seems to be important. [1] https://lore.kernel.org/u-boot/CAFLszTh-SewFod8dEOF3+e-wCE1qFF0CyxxR8CbQwy3BRW3k6w@mail.gmail.com/ Reviewed-by: Jonas Karlman Reviewed-by: Kever Yang Tested-by: Simon Glass # chromebook-kevin Signed-off-by: Quentin Schulz --- arch/arm/dts/rk3288-u-boot.dtsi | 24 ------------------------ arch/arm/dts/rk3288-veyron-u-boot.dtsi | 8 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 5 ----- 3 files changed, 8 insertions(+), 29 deletions(-) diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 2205caabc51..bb0078588fe 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -46,30 +46,6 @@ }; }; -#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM) -&binman { - rom { - filename = "u-boot.rom"; - size = <0x400000>; - pad-byte = <0xff>; - - mkimage { - args = "-n rk3288 -T rkspi"; - u-boot-spl { - }; - }; - u-boot-img { - offset = <0x20000>; - }; - u-boot { - offset = <0x300000>; - }; - fdtmap { - }; - }; -}; -#endif - &bus_intmem { ddr_sram: ddr-sram@1000 { compatible = "rockchip,rk3288-ddr-sram"; diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi index 4f9c59c6757..89093e2311c 100644 --- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi @@ -11,6 +11,14 @@ }; }; +#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) +&binman { + simple-bin-spi { + size = <0x400000>; + }; +}; +#endif + &dmc { logic-supply = <&vdd_logic>; rockchip,odt-disable-freq = <333000000>; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index e563bf455e6..128ee362f8a 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -5,7 +5,6 @@ choice config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" - select HAS_ROM select BOARD_LATE_INIT select ROCKCHIP_SPI_IMAGE help @@ -16,7 +15,6 @@ config TARGET_CHROMEBOOK_JERRY config TARGET_CHROMEBIT_MICKEY bool "Google/Rockchip Veyron-Mickey Chromebit" - select HAS_ROM select BOARD_LATE_INIT select ROCKCHIP_SPI_IMAGE help @@ -28,7 +26,6 @@ config TARGET_CHROMEBIT_MICKEY config TARGET_CHROMEBOOK_MINNIE bool "Google/Rockchip Veyron-Minnie Chromebook" - select HAS_ROM select BOARD_LATE_INIT select ROCKCHIP_SPI_IMAGE help @@ -41,7 +38,6 @@ config TARGET_CHROMEBOOK_MINNIE config TARGET_CHROMEBOOK_SPEEDY bool "Google/Rockchip Veyron-Speedy Chromebook" - select HAS_ROM select BOARD_LATE_INIT select ROCKCHIP_SPI_IMAGE help @@ -54,7 +50,6 @@ config TARGET_CHROMEBOOK_SPEEDY config TARGET_EVB_RK3288 bool "Evb-RK3288" - select HAS_ROM select BOARD_LATE_INIT select TPL help From 876df0a57daafce96d28a3965116e2bb29e9e0e4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 13 Apr 2025 19:59:33 +0000 Subject: [PATCH 03/28] rockchip: binman: Correct the OS prop for U-Boot The U-Boot image is currently being identified as an invalid OS in spl_fit_image_get_os() due to case sensitive compare. Use the correct lower-case value to fix this. Fixes: e0c0efff2a02 ("rockchip: Support building the all output files in binman") Signed-off-by: Simon Glass Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Reviewed-by: Quentin Schulz --- arch/arm/dts/rockchip-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index c8c928c7e50..e9ed1d4b573 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -50,7 +50,7 @@ u-boot { description = "U-Boot"; type = "standalone"; - os = "U-Boot"; + os = "u-boot"; #ifdef CONFIG_ARM64 arch = "arm64"; #else From 3810ce1b47a2a65d962c6dc14e8e4ef2c799d2d0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 13 Apr 2025 19:59:34 +0000 Subject: [PATCH 04/28] rockchip: binman: Factor out arch and compression Declare arch and compression at the top of the file to avoid needing ifdefs in every usage. Add a few comments to help with the remaining #ifdefs. Signed-off-by: Simon Glass Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rockchip-u-boot.dtsi | 44 +++++++++++++++---------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index e9ed1d4b573..943d7d87a06 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -5,6 +5,20 @@ #include +#ifdef CONFIG_ARM64 +#define FIT_ARCH "arm64" +#else +#define FIT_ARCH "arm" +#endif + +#if defined(CONFIG_SPL_GZIP) +#define FIT_UBOOT_COMP "gzip" +#elif defined(CONFIG_SPL_LZMA) +#define FIT_UBOOT_COMP "lzma" +#else +#define FIT_UBOOT_COMP "none" +#endif + / { binman: binman { multiple-images; @@ -51,26 +65,12 @@ description = "U-Boot"; type = "standalone"; os = "u-boot"; -#ifdef CONFIG_ARM64 - arch = "arm64"; -#else - arch = "arm"; -#endif -#if defined(CONFIG_SPL_GZIP) - compression = "gzip"; -#elif defined(CONFIG_SPL_LZMA) - compression = "lzma"; -#else - compression = "none"; -#endif + arch = FIT_ARCH; + compression = FIT_UBOOT_COMP; load = ; entry = ; u-boot-nodtb { -#if defined(CONFIG_SPL_GZIP) - compress = "gzip"; -#elif defined(CONFIG_SPL_LZMA) - compress = "lzma"; -#endif + compress = FIT_UBOOT_COMP; }; #ifdef CONFIG_SPL_FIT_SIGNATURE hash { @@ -84,7 +84,7 @@ fit,operation = "split-elf"; description = "ARM Trusted Firmware"; type = "firmware"; - arch = "arm64"; + arch = FIT_ARCH; os = "arm-trusted-firmware"; compression = "none"; fit,load; @@ -103,7 +103,7 @@ fit,operation = "split-elf"; description = "TEE"; type = "tee"; - arch = "arm64"; + arch = FIT_ARCH; os = "tee"; compression = "none"; fit,load; @@ -119,11 +119,11 @@ }; #endif }; -#else +#else /* !CONFIG_ARM64 */ op-tee { description = "OP-TEE"; type = "tee"; - arch = "arm"; + arch = FIT_ARCH; os = "tee"; compression = "none"; load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; @@ -137,7 +137,7 @@ }; #endif }; -#endif +#endif /* CONFIG_ARM64 */ @fdt-SEQ { description = "fdt-NAME"; From 2febe31d6672dfbd02cbcaf1873ed049eaa2d249 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 13 Apr 2025 19:59:35 +0000 Subject: [PATCH 05/28] rockchip: binman: Create a template for the FIT Move the FIT description into a template so that it can be used in both the simple-bin and the simple-bin-spi images. Signed-off-by: Simon Glass Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Reviewed-by: Quentin Schulz --- arch/arm/dts/rockchip-u-boot.dtsi | 64 +++++++++++++++++-------------- 1 file changed, 36 insertions(+), 28 deletions(-) diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index 943d7d87a06..0c074c0ec6b 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -19,6 +19,10 @@ #define FIT_UBOOT_COMP "none" #endif +#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)) +#define HAS_FIT +#endif + / { binman: binman { multiple-images; @@ -27,28 +31,9 @@ #ifdef CONFIG_SPL &binman { - simple-bin { - filename = "u-boot-rockchip.bin"; - pad-byte = <0xff>; - - mkimage { - filename = "idbloader.img"; - args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; - multiple-data-files; - -#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL - rockchip-tpl { - }; -#elif defined(CONFIG_TPL) - u-boot-tpl { - }; -#endif - u-boot-spl { - }; - }; - -#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)) - fit: fit { +#ifdef HAS_FIT + fit_template: template-1 { + type = "fit"; #ifdef CONFIG_ARM64 description = "FIT image for U-Boot with bl31 (TF-A)"; #else @@ -56,10 +41,8 @@ #endif #address-cells = <1>; fit,fdt-list = "of-list"; - filename = "u-boot.itb"; fit,external-offset = ; fit,align = <512>; - offset = ; images { u-boot { description = "U-Boot"; @@ -164,12 +147,38 @@ fit,loadables; }; }; + }; +#endif /* HAS_FIT */ + + simple-bin { + filename = "u-boot-rockchip.bin"; + pad-byte = <0xff>; + + mkimage { + filename = "idbloader.img"; + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + multiple-data-files; + +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL + rockchip-tpl { + }; +#elif defined(CONFIG_TPL) + u-boot-tpl { + }; +#endif + u-boot-spl { + }; }; + +#ifdef HAS_FIT + fit { + filename = "u-boot.itb"; + insert-template = <&fit_template>; #else u-boot-img { +#endif offset = ; }; -#endif }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE @@ -193,10 +202,9 @@ }; }; -#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE) +#ifdef HAS_FIT fit { - type = "blob"; - filename = "u-boot.itb"; + insert-template = <&fit_template>; #else u-boot-img { #endif From 59c253a11f9005223f3f11ad5da101ac13c6e70b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 13 Apr 2025 19:59:36 +0000 Subject: [PATCH 06/28] rockchip: binman: Un-indent the FIT template Fix the indentation on the template. This is done in a separate patch so that it is easier to review. Signed-off-by: Simon Glass Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Reviewed-by: Quentin Schulz --- arch/arm/dts/rockchip-u-boot.dtsi | 180 +++++++++++++++--------------- 1 file changed, 90 insertions(+), 90 deletions(-) diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index 0c074c0ec6b..e97e9d23834 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -33,120 +33,120 @@ &binman { #ifdef HAS_FIT fit_template: template-1 { - type = "fit"; + type = "fit"; #ifdef CONFIG_ARM64 - description = "FIT image for U-Boot with bl31 (TF-A)"; + description = "FIT image for U-Boot with bl31 (TF-A)"; #else - description = "FIT image with OP-TEE"; + description = "FIT image with OP-TEE"; #endif - #address-cells = <1>; - fit,fdt-list = "of-list"; - fit,external-offset = ; - fit,align = <512>; - images { - u-boot { - description = "U-Boot"; - type = "standalone"; - os = "u-boot"; - arch = FIT_ARCH; - compression = FIT_UBOOT_COMP; - load = ; - entry = ; - u-boot-nodtb { + #address-cells = <1>; + fit,fdt-list = "of-list"; + fit,external-offset = ; + fit,align = <512>; + images { + u-boot { + description = "U-Boot"; + type = "standalone"; + os = "u-boot"; + arch = FIT_ARCH; + compression = FIT_UBOOT_COMP; + load = ; + entry = ; + u-boot-nodtb { compress = FIT_UBOOT_COMP; - }; -#ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif }; +#ifdef CONFIG_SPL_FIT_SIGNATURE + hash { + algo = "sha256"; + }; +#endif + }; #ifdef CONFIG_ARM64 - @atf-SEQ { - fit,operation = "split-elf"; - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = FIT_ARCH; - os = "arm-trusted-firmware"; - compression = "none"; - fit,load; - fit,entry; - fit,data; + @atf-SEQ { + fit,operation = "split-elf"; + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = FIT_ARCH; + os = "arm-trusted-firmware"; + compression = "none"; + fit,load; + fit,entry; + fit,data; - atf-bl31 { - }; -#ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif + atf-bl31 { }; - @tee-SEQ { - fit,operation = "split-elf"; - description = "TEE"; - type = "tee"; - arch = FIT_ARCH; - os = "tee"; - compression = "none"; - fit,load; - fit,entry; - fit,data; +#ifdef CONFIG_SPL_FIT_SIGNATURE + hash { + algo = "sha256"; + }; +#endif + }; + @tee-SEQ { + fit,operation = "split-elf"; + description = "TEE"; + type = "tee"; + arch = FIT_ARCH; + os = "tee"; + compression = "none"; + fit,load; + fit,entry; + fit,data; - tee-os { - optional; - }; -#ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif + tee-os { + optional; }; +#ifdef CONFIG_SPL_FIT_SIGNATURE + hash { + algo = "sha256"; + }; +#endif + }; #else /* !CONFIG_ARM64 */ - op-tee { - description = "OP-TEE"; - type = "tee"; - arch = FIT_ARCH; - os = "tee"; - compression = "none"; - load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; - entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + op-tee { + description = "OP-TEE"; + type = "tee"; + arch = FIT_ARCH; + os = "tee"; + compression = "none"; + load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; - tee-os { - }; -#ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif + tee-os { }; +#ifdef CONFIG_SPL_FIT_SIGNATURE + hash { + algo = "sha256"; + }; +#endif + }; #endif /* CONFIG_ARM64 */ - @fdt-SEQ { - description = "fdt-NAME"; - compression = "none"; - type = "flat_dt"; + @fdt-SEQ { + description = "fdt-NAME"; + compression = "none"; + type = "flat_dt"; #ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif + hash { + algo = "sha256"; }; +#endif }; + }; - configurations { - default = "@config-DEFAULT-SEQ"; - @config-SEQ { - description = "NAME.dtb"; - fdt = "fdt-SEQ"; + configurations { + default = "@config-DEFAULT-SEQ"; + @config-SEQ { + description = "NAME.dtb"; + fdt = "fdt-SEQ"; #ifdef CONFIG_ARM64 - fit,firmware = "atf-1", "u-boot"; + fit,firmware = "atf-1", "u-boot"; #else - fit,firmware = "op-tee", "u-boot"; + fit,firmware = "op-tee", "u-boot"; #endif - fit,loadables; - }; + fit,loadables; }; + }; }; #endif /* HAS_FIT */ From ce0dccf4593d2eefcb6b0c3145a2f0dd7490d900 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 13 Apr 2025 19:59:37 +0000 Subject: [PATCH 07/28] rockchip: Add SPL_PAD_TO Kconfig default value Almost all Rockchip boards use the same Kconfig value for SPL_PAD_TO, 0x7f8000. u-boot-rockchip.bin is typically written to offset 64S (32KiB) of MMC media. u-boot.itb (or u-boot.img) is typically expected at offset 16384S (8MiB) of MMC media (SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x4000). SPL_PAD_TO is used as the offset for u-boot.itb (or u-boot.img) in the generated simple-bin binman image, and can be calculated as: SPL_PAD_TO = (16384S - 64S) * 512 = 0x7f8000 Add this value as a default value for ARCH_ROCKCHIP. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Reviewed-by: Quentin Schulz --- common/spl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 0bc96d0a781..aa3a85eea54 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -96,6 +96,7 @@ config SPL_MAX_SIZE config SPL_PAD_TO hex "Offset to which the SPL should be padded before appending the SPL payload" + default 0x7f8000 if ARCH_ROCKCHIP default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB) default 0x10000 if ARCH_KEYSTONE From cbd89fdd03607008dec0b4cb3a8ad1fd017d7df7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 13 Apr 2025 19:59:38 +0000 Subject: [PATCH 08/28] rockchip: binman: Include a compatible string in each configuration Provide a compatible string in the config nodes that U-Boot can use to help decide which configuration to use with SPL_LOAD_FIT_FULL=y and FIT_BEST_MATCH=y. Signed-off-by: Simon Glass Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Reviewed-by: Quentin Schulz --- arch/arm/dts/rockchip-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index e97e9d23834..f60cc31fb1a 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -145,6 +145,7 @@ fit,firmware = "op-tee", "u-boot"; #endif fit,loadables; + fit,compatible; }; }; }; From 24c56a160aaf85fbe113b771a56b9a51f913f823 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 13 Apr 2025 19:59:39 +0000 Subject: [PATCH 09/28] rockchip: binman: Support use of crc32 hash for FIT images Use of SHA256 checksum validation on ARMv7 SoCs can be very time consuming compared to when used on a ARMv8 SoC with Crypto Extensions. Add support for use of the much faster CRC32 hash algo when SHA256 is not supported in SPL. Also use FIT_HASH_ALGO to simplify the ifdefs when no known hash algo has been compiled. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Reviewed-by: Quentin Schulz --- arch/arm/dts/rockchip-u-boot.dtsi | 32 +++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index f60cc31fb1a..cc2feed6464 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -19,6 +19,18 @@ #define FIT_UBOOT_COMP "none" #endif +/* + * SHA256 should be enabled in SPL when signature validation is involved, + * CRC32 should only be used for basic checksum validation of FIT images. + */ +#if defined(CONFIG_SPL_FIT_SIGNATURE) +#if defined(CONFIG_SPL_SHA256) +#define FIT_HASH_ALGO "sha256" +#elif defined(CONFIG_SPL_CRC32) +#define FIT_HASH_ALGO "crc32" +#endif +#endif + #if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)) #define HAS_FIT #endif @@ -55,9 +67,9 @@ u-boot-nodtb { compress = FIT_UBOOT_COMP; }; -#ifdef CONFIG_SPL_FIT_SIGNATURE +#ifdef FIT_HASH_ALGO hash { - algo = "sha256"; + algo = FIT_HASH_ALGO; }; #endif }; @@ -76,9 +88,9 @@ atf-bl31 { }; -#ifdef CONFIG_SPL_FIT_SIGNATURE +#ifdef FIT_HASH_ALGO hash { - algo = "sha256"; + algo = FIT_HASH_ALGO; }; #endif }; @@ -96,9 +108,9 @@ tee-os { optional; }; -#ifdef CONFIG_SPL_FIT_SIGNATURE +#ifdef FIT_HASH_ALGO hash { - algo = "sha256"; + algo = FIT_HASH_ALGO; }; #endif }; @@ -114,9 +126,9 @@ tee-os { }; -#ifdef CONFIG_SPL_FIT_SIGNATURE +#ifdef FIT_HASH_ALGO hash { - algo = "sha256"; + algo = FIT_HASH_ALGO; }; #endif }; @@ -126,9 +138,9 @@ description = "fdt-NAME"; compression = "none"; type = "flat_dt"; -#ifdef CONFIG_SPL_FIT_SIGNATURE +#ifdef FIT_HASH_ALGO hash { - algo = "sha256"; + algo = FIT_HASH_ALGO; }; #endif }; From 96f9e112550cd195fcc712ed5092a6f348ca76d8 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:29 +0100 Subject: [PATCH 10/28] pinctrl: rockchip: fix bank's pin_base computing The logic in the core reads the nr_pins of the controller and uses it as the index of the first pin in the bank (pin_base) it currently parses. It then increments the number of pins in the controller before going to the next bank. This works "fine" for controllers where nr_pins isn't defined in their rockchip_pin_ctrl struct as it defaults to 0. However, when it is already set, it'll make the index pin of each bank offset by the number in nr_pins declared in the struct at initialization, and it'll keep growing while adding banks, which means the total number of pins in the controller will be misrepresented. Additionally, U-Boot proper may probe this driver twice (pre-reloc and true proper) and not reset nr_pins of the controller in-between meaning the second probe will have an offset of the actual correct nr_pins. Instead, let's just store locally the number of pins in the controller and make sure it's reset between probes. Finally, this stops modifying a const struct which will soon be triggering a CPU abort at runtime. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3568.c | 1 - drivers/pinctrl/rockchip/pinctrl-rk3588.c | 1 - drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 5 +++-- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 1 - drivers/pinctrl/rockchip/pinctrl-rv1126.c | 1 - 5 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index 5deedc648a4..c8a91b8bb6e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -345,7 +345,6 @@ static struct rockchip_pin_bank rk3568_pin_banks[] = { static const struct rockchip_pin_ctrl rk3568_pin_ctrl = { .pin_banks = rk3568_pin_banks, .nr_banks = ARRAY_SIZE(rk3568_pin_banks), - .nr_pins = 160, .grf_mux_offset = 0x0, .pmu_mux_offset = 0x0, .iomux_routes = rk3568_mux_route_data, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3588.c b/drivers/pinctrl/rockchip/pinctrl-rk3588.c index 98ababc7c90..fd8e617b910 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3588.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3588.c @@ -324,7 +324,6 @@ static struct rockchip_pin_bank rk3588_pin_banks[] = { static const struct rockchip_pin_ctrl rk3588_pin_ctrl = { .pin_banks = rk3588_pin_banks, .nr_banks = ARRAY_SIZE(rk3588_pin_banks), - .nr_pins = 160, .set_mux = rk3588_set_mux, .set_pull = rk3588_set_pull, .set_drive = rk3588_set_drive, diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index d449d07d32e..4de67aba1c3 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -532,6 +532,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); struct rockchip_pin_bank *bank; int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; + u32 ctrl_nr_pins = 0; grf_offs = ctrl->grf_mux_offset; pmu_offs = ctrl->pmu_mux_offset; @@ -543,8 +544,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d int bank_pins = 0; bank->priv = priv; - bank->pin_base = ctrl->nr_pins; - ctrl->nr_pins += bank->nr_pins; + bank->pin_base = ctrl_nr_pins; + ctrl_nr_pins += bank->nr_pins; /* calculate iomux and drv offsets */ for (j = 0; j < 4; j++) { diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index 5e3c9c90760..ba684baed24 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -503,7 +503,6 @@ struct rockchip_mux_route_data { struct rockchip_pin_ctrl { struct rockchip_pin_bank *pin_banks; u32 nr_banks; - u32 nr_pins; int grf_mux_offset; int pmu_mux_offset; int grf_drv_offset; diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1126.c b/drivers/pinctrl/rockchip/pinctrl-rv1126.c index efa2408b204..3878a5420dc 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1126.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1126.c @@ -381,7 +381,6 @@ static struct rockchip_pin_bank rv1126_pin_banks[] = { static const struct rockchip_pin_ctrl rv1126_pin_ctrl = { .pin_banks = rv1126_pin_banks, .nr_banks = ARRAY_SIZE(rv1126_pin_banks), - .nr_pins = 130, .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ .pmu_mux_offset = 0x0, .iomux_routes = rv1126_mux_route_data, From f6c4dcb1f2907fadef6f47a9336434656b21b0c8 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:30 +0100 Subject: [PATCH 11/28] pinctrl: rockchip: constify rockchip_pin_ctrl for PX30 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-px30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-px30.c b/drivers/pinctrl/rockchip/pinctrl-px30.c index cc7885bae40..4595d8a4a23 100644 --- a/drivers/pinctrl/rockchip/pinctrl-px30.c +++ b/drivers/pinctrl/rockchip/pinctrl-px30.c @@ -324,7 +324,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = { ), }; -static struct rockchip_pin_ctrl px30_pin_ctrl = { +static const struct rockchip_pin_ctrl px30_pin_ctrl = { .pin_banks = px30_pin_banks, .nr_banks = ARRAY_SIZE(px30_pin_banks), .grf_mux_offset = 0x0, From 91b39dd208d76a865bd4e2ce83099c9478599331 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:31 +0100 Subject: [PATCH 12/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3036 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index b14386ccd93..8d0c0e0b655 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -80,7 +80,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = { PIN_BANK(2, 32, "gpio2"), }; -static struct rockchip_pin_ctrl rk3036_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3036_pin_ctrl = { .pin_banks = rk3036_pin_banks, .nr_banks = ARRAY_SIZE(rk3036_pin_banks), .grf_mux_offset = 0xa8, From cb27ad9a101cb0dd371414937d68b3c746a11885 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:32 +0100 Subject: [PATCH 13/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3066 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3066.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c b/drivers/pinctrl/rockchip/pinctrl-rk3066.c index 60e088a9a6f..f773f2a3dab 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3066.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c @@ -82,7 +82,7 @@ static struct rockchip_pin_bank rk3066_pin_banks[] = { PIN_BANK(6, 16, "gpio6"), }; -static struct rockchip_pin_ctrl rk3066_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3066_pin_ctrl = { .pin_banks = rk3066_pin_banks, .nr_banks = ARRAY_SIZE(rk3066_pin_banks), .grf_mux_offset = 0xa8, From 8881eb7317ea07d5cee1ea3ab828449ce7311d56 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:33 +0100 Subject: [PATCH 14/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3128 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3128.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index d00fc3da8b2..9f9c358694a 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -171,7 +171,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3128_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3128_pin_ctrl = { .pin_banks = rk3128_pin_banks, .nr_banks = ARRAY_SIZE(rk3128_pin_banks), .grf_mux_offset = 0xa8, From 8ac01d7965474c902ead017a8efc7d2fb9e741bd Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:34 +0100 Subject: [PATCH 15/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3188 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3188.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 83db51f66ae..3a93db5622d 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -105,7 +105,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3188_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pin_banks = rk3188_pin_banks, .nr_banks = ARRAY_SIZE(rk3188_pin_banks), .grf_mux_offset = 0x60, From 1b85862d7ec56533131de6cdd16fb482046cc5bb Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:35 +0100 Subject: [PATCH 16/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3228 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk322x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index b804597c048..a80978685d4 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -257,7 +257,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3228_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3228_pin_ctrl = { .pin_banks = rk3228_pin_banks, .nr_banks = ARRAY_SIZE(rk3228_pin_banks), .grf_mux_offset = 0x0, From 8475f52604bc189427b77c2a0769379e9f753eac Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:36 +0100 Subject: [PATCH 17/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3288 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 3870c1b7a34..d3ad1f70e5d 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -212,7 +212,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = { PIN_BANK(8, 16, "gpio8"), }; -static struct rockchip_pin_ctrl rk3288_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pin_banks = rk3288_pin_banks, .nr_banks = ARRAY_SIZE(rk3288_pin_banks), .grf_mux_offset = 0x0, From 4d4e4d502be0f5bf101ae608d30bf6616f58767e Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:37 +0100 Subject: [PATCH 18/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3308 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3308.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c b/drivers/pinctrl/rockchip/pinctrl-rk3308.c index 2cd91b10a3b..5c0e34a7baa 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3308.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c @@ -421,7 +421,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = { IOMUX_8WIDTH_2BIT), }; -static struct rockchip_pin_ctrl rk3308_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3308_pin_ctrl = { .pin_banks = rk3308_pin_banks, .nr_banks = ARRAY_SIZE(rk3308_pin_banks), .grf_mux_offset = 0x0, From 046868334433666ef46f6b762039550d41548aa0 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:38 +0100 Subject: [PATCH 19/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3328 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index dd0dc2eff27..1834df6c3d1 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -330,7 +330,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { 0), }; -static struct rockchip_pin_ctrl rk3328_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3328_pin_ctrl = { .pin_banks = rk3328_pin_banks, .nr_banks = ARRAY_SIZE(rk3328_pin_banks), .grf_mux_offset = 0x0, From b8c273247c6c836d6a3065efc8efe0f8a0870b09 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:39 +0100 Subject: [PATCH 20/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3368 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3368.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 9ae06ed19e9..aaf24719a16 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -152,7 +152,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3368_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3368_pin_ctrl = { .pin_banks = rk3368_pin_banks, .nr_banks = ARRAY_SIZE(rk3368_pin_banks), .grf_mux_offset = 0x0, From 60a2c563b7461c567b60fd3af2dd6c06f9d5ce34 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:40 +0100 Subject: [PATCH 21/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RK3399 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index b7a5092c032..928ed59aec6 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -279,7 +279,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { ), }; -static struct rockchip_pin_ctrl rk3399_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pin_banks = rk3399_pin_banks, .nr_banks = ARRAY_SIZE(rk3399_pin_banks), .grf_mux_offset = 0xe000, From 735fb2d7ee4679be9e9fda5c0a33ba4780b2d931 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 31 Jan 2025 11:31:41 +0100 Subject: [PATCH 22/28] pinctrl: rockchip: constify rockchip_pin_ctrl for RV1108 There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rv1108.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index 3eff5f59598..780da1e946e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -263,7 +263,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), }; -static struct rockchip_pin_ctrl rv1108_pin_ctrl = { +static const struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pin_banks = rv1108_pin_banks, .nr_banks = ARRAY_SIZE(rv1108_pin_banks), .grf_mux_offset = 0x10, From 64f670f75fabbfb2a1e4d517b761f976de022133 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 29 Apr 2025 21:28:40 +0800 Subject: [PATCH 23/28] rockchip: io-domain: Enable by default for all supported SoCs The IO domain driver controls the I/O voltage for various pins, MMC included. Enable it by default for all supported Rockchip SoCs. Signed-off-by: Chen-Yu Tsai Reviewed-by: Quentin Schulz Reviewed-by: Paul Kocialkowski Reviewed-by: Jonas Karlman Reviewed-by: Anand Moon --- configs/chromebook_bob_defconfig | 1 - configs/chromebook_kevin_defconfig | 1 - configs/eaidk-610-rk3399_defconfig | 1 - configs/evb-rk3399_defconfig | 1 + configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig | 1 - configs/leez-rk3399_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-2gb-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-m4b-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/nanopi-r4s-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/pinebook-pro-rk3399_defconfig | 1 - configs/pinephone-pro-rk3399_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/ringneck-px30_defconfig | 1 - configs/roc-pc-mezzanine-rk3399_defconfig | 1 - configs/roc-pc-rk3399_defconfig | 1 - configs/rock-4c-plus-rk3399_defconfig | 1 - configs/rock-4se-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock-pi-4c-rk3399_defconfig | 1 - configs/rock-pi-n10-rk3399pro_defconfig | 1 - configs/rock-pi-s-rk3308_defconfig | 1 - configs/rock-s0-rk3308_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 1 - drivers/misc/Kconfig | 6 +++++- 33 files changed, 6 insertions(+), 32 deletions(-) diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 5b8c0d35de6..2c44afeddcd 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -58,7 +58,6 @@ CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_I2C_MUX=y CONFIG_CROS_EC_KEYB=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index a29a04aadde..e7c42befe97 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -59,7 +59,6 @@ CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_I2C_MUX=y CONFIG_CROS_EC_KEYB=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 8f9a76157f1..45a2d901683 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -31,7 +31,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 9481dfae7e4..87b4949de06 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +# CONFIG_ROCKCHIP_IODOMAIN is not set CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index b32ca726b6c..3a72156d389 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -37,7 +37,6 @@ CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 3871627318b..be8cde09446 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -34,7 +34,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 89611a0535e..ce425eb9b20 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -45,7 +45,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 3816f4327a6..10a20d749ba 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -43,7 +43,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 35e20942572..d3345c12fe2 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -45,7 +45,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 57b097377fa..f12f39857e0 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -31,7 +31,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 26c12c51078..40844753ccd 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -34,7 +34,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index d24b7bc6d17..31b0e83cdea 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -38,7 +38,6 @@ CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index da3e44af841..1a9b770c169 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -37,7 +37,6 @@ CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 247056ab58b..d3a8b5bb6d1 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -37,7 +37,6 @@ CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 305877d2079..1e422befdf8 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -32,7 +32,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index a6dafe3d9eb..04642bca7cb 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -32,7 +32,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index fdf3d698939..d5091ee8a0c 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -32,7 +32,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index dfa927ccb17..676d1e71894 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -51,7 +51,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 5e16749ba7d..85833c654b8 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -47,7 +47,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 7a180b14130..95ed6eea953 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -64,7 +64,6 @@ CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index b6b3d3e2b3f..a334d822e9e 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -82,7 +82,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_ROCKCHIP_OTP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 3ab5fd69c62..9c063ce82d3 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -45,7 +45,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 0ef86748778..68c4267d242 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -43,7 +43,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 0c73a212ea1..2f1ea314302 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -49,7 +49,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 3ae19692155..7387130ecc1 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -53,7 +53,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index f3a5c2c45f3..97a7db3730d 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -54,7 +54,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 9bda50c8c77..7da7ee4bce1 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -54,7 +54,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index a9c6d8a907a..a38670d95d0 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -35,7 +35,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index 4b08af309b1..907b999b274 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -40,7 +40,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/rock-s0-rk3308_defconfig b/configs/rock-s0-rk3308_defconfig index 063e0b921d7..d46977b34a4 100644 --- a/configs/rock-s0-rk3308_defconfig +++ b/configs/rock-s0-rk3308_defconfig @@ -41,7 +41,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index aebfa73459c..607aa61ba17 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -41,7 +41,6 @@ CONFIG_SYS_MMC_ENV_DEV=1 # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 75322073285..1b887cd9f3e 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -49,7 +49,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0911d2fc0cc..ffc5868c0dd 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -104,7 +104,11 @@ config ROCKCHIP_OTP config ROCKCHIP_IODOMAIN bool "Rockchip IO-domain driver support" depends on DM_REGULATOR && ARCH_ROCKCHIP - default y if ROCKCHIP_RK3328 || ROCKCHIP_RK3568 + default y if ROCKCHIP_PX30 + default y if ROCKCHIP_RK3308 + default y if ROCKCHIP_RK3328 + default y if ROCKCHIP_RK3399 + default y if ROCKCHIP_RK3568 help Enable support for IO-domains in Rockchip SoCs. It is necessary for the IO-domain setting of the SoC to match the voltage supplied From 2d6346d9017b4227faee765bddd232928195d10a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 6 May 2025 10:55:31 +0200 Subject: [PATCH 24/28] configs: rockchip: sync ENV_MEM_LAYOUT_SETTINGS for px30 to rk3308/etc Loading a FIT image for kernel, initrd and rootfs on px30 can result in an memory overlap, resulting in the not 100% helpful message of "This will not be a case any time" from lmb_fix_over_lap_regions(). Adding a bit of debug info to lmb_fix_over_lap_regions() brings: lmb_fix_over_lap_regions: base1 0x280000-0x6005ac > base2 0x600000-0x6000d1 So this is because the FIT image gets loaded to the kernel_addr_r at 0x280000 while the pxe-file is already living at 0x600000, only 3.5MB behind. In commit 4acc8bb044a4 ("configs: rockchip: sync ENV_MEM_LAYOUT_SETTINGS for rk3308, rk3328, and rk3399") FUKAUMI Naoki already brought the memory layouts for the mentioned socs in sync. Adjusting the env-layout on px30 to this scheme, magically solves the overlap issue and also brings px30 more in line with the other mentioned SoCs. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- include/configs/px30_common.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index d0539003fd5..2a3dc362f98 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -18,12 +18,14 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x08300000\0" \ - "fdtoverlay_addr_r=0x08400000\0" \ - "kernel_addr_r=0x00280000\0" \ - "ramdisk_addr_r=0x0a200000\0" \ - "kernel_comp_addr_r=0x03e80000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02080000\0" \ + "ramdisk_addr_r=0x06000000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ "kernel_comp_size=0x2000000\0" #define CFG_EXTRA_ENV_SETTINGS \ From 15d76136fb6fe939d5ad3738919a241fe09ce116 Mon Sep 17 00:00:00 2001 From: Ilya Katsnelson Date: Wed, 23 Apr 2025 18:36:40 +0300 Subject: [PATCH 25/28] board: rockchip: add Xunlong Orange Pi 5 Max The 5 Max is another board in the Orange Pi 5 family. It's overall similar to the 5 Plus, but in a smaller form factor, which leads to some I/O being reshuffled, but nothing relevant to u-boot. So, just reuse the config for the 5 Plus and adjust the DT names. Reviewed-by: Jonas Karlman Signed-off-by: Ilya Katsnelson Reviewed-by: Kever Yang --- .../arm/dts/rk3588-orangepi-5-max-u-boot.dtsi | 20 +++++ board/rockchip/evb_rk3588/MAINTAINERS | 6 ++ configs/orangepi-5-max-rk3588_defconfig | 89 +++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 4 files changed, 116 insertions(+) create mode 100644 arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi create mode 100644 configs/orangepi-5-max-rk3588_defconfig diff --git a/arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi new file mode 100644 index 00000000000..afd33dd3248 --- /dev/null +++ b/arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim2_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index a858ab163f3..1232f05a387 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -36,6 +36,12 @@ F: configs/orangepi-5-rk3588s_defconfig F: arch/arm/dts/rk3588s-orangepi-5.dts F: arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi +ORANGEPI-5-MAX-RK3588 +M: Ilya Katsnelson +S: Maintained +F: configs/orangepi-5-max-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi + ORANGEPI-5-PLUS-RK3588 M: Jonas Karlman S: Maintained diff --git a/configs/orangepi-5-max-rk3588_defconfig b/configs/orangepi-5-max-rk3588_defconfig new file mode 100644 index 00000000000..a655dfe2d64 --- /dev/null +++ b/configs/orangepi-5-max-rk3588_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-orangepi-5-max" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-max.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b06f87b137c..13e06095333 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -158,6 +158,7 @@ List of mainline supported Rockchip boards: - Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588) - Turing Machines RK1 (turing-rk1-rk3588) - Xunlong Orange Pi 5 (orangepi-5-rk3588s) + - Xunlong Orange Pi 5 Max (orangepi-5-max-rk3588) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s) - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588) From 656b70b5ffe69d2a23a63a32360af6374ad96c96 Mon Sep 17 00:00:00 2001 From: Jiehui He Date: Tue, 15 Apr 2025 03:36:50 -0400 Subject: [PATCH 26/28] board: rockchip: Add LCKFB TaishanPi RK3566 Board The LCKFB TaishanPi is a single-board computer based on the RK3566 SoC. Specification: - 1/2 Gib RAM - Optinal EMMC - SD-Card - HDMI / MIPI CSI / MIPI DSI - USB 2.0 Host (Type-A) - USB 2.0 Host / OTG (Type-C) - No Ethernet This patch adds U-Boot support for the LCKFB TaishanPi RK3566 board, including: - U-Boot device tree - Default defconfig - Board documentation - MAINTAINERS entry Changes in v2: - Removed unused configs from `lckfb-tspi-rk3566_defconfig` - Reordered TaishanPi entry in `doc/board/rockchip/rockchip.rst` alphabetically Link to v1: https://lore.kernel.org/u-boot/tencent_95ED0C0545D87B6A8C4B62EC045D53AD2406@qq.com/ Signed-off-by: Jiehui He Reviewed-by: Kever Yang --- arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi | 11 +++ board/rockchip/evb_rk3568/MAINTAINERS | 6 ++ configs/lckfb-tspi-rk3566_defconfig | 78 ++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 4 files changed, 96 insertions(+) create mode 100644 arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi create mode 100644 configs/lckfb-tspi-rk3566_defconfig diff --git a/arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi b/arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi new file mode 100644 index 00000000000..0c8e7018f13 --- /dev/null +++ b/arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" + +&rgb_led_r { + default-state = "off"; +}; + +&rgb_led_b { + default-state = "off"; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index b2780401a39..6cf568ad150 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -89,3 +89,9 @@ M: Maxim Moskalets S: Maintained F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi F: configs/rock-3c-rk3566_defconfig + +LCKFB-TaishanPi +M: Jiehui He +S: Maintained +F: configs/lckfb-tspi-rk3566_defconfig +F: arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi diff --git a/configs/lckfb-tspi-rk3566_defconfig b/configs/lckfb-tspi-rk3566_defconfig new file mode 100644 index 00000000000..bc54be5ca53 --- /dev/null +++ b/configs/lckfb-tspi-rk3566_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-lckfb-tspi" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-lckfb-tspi.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_GENERIC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 13e06095333..b88299cbba2 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -107,6 +107,7 @@ List of mainline supported Rockchip boards: - Anbernic RGxx3 (anbernic-rgxx3-rk3566) - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566) - Hardkernel ODROID-M1S (odroid-m1s-rk3566) + - LCKFB TaishanPi (lckfb-tspi-rk3566) - Pine64 PineTab2 (pinetab2-rk3566) - Pine64 Quartz64-A Board (quartz64-a-rk3566) - Pine64 Quartz64-B Board (quartz64-b-rk3566) From b8ce3eb8bfab6532fb4aa5569d3d064b94588ac1 Mon Sep 17 00:00:00 2001 From: Christoph Fritz Date: Wed, 16 Apr 2025 13:44:13 +0200 Subject: [PATCH 27/28] rockchip: rk3288: grf: Unify speed/flowctrl fields for clarity Update GMAC speed and flow control fields in GRF_SOC_CON1 to use RK3288_GMAC_* prefix, ensuring a consistent naming convention. It also shifts each mask/bit definition to match the actual hardware bits, which makes future usage easier. Signed-off-by: Christoph Fritz Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 894d3a40b09..0111b3a0ded 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -934,21 +934,21 @@ enum { RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT), RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT), - GMAC_SPEED_SHIFT = 0xa, - GMAC_SPEED_MASK = 1, - GMAC_SPEED_10M = 0, - GMAC_SPEED_100M, + RK3288_GMAC_SPEED_SHIFT = 0xa, + RK3288_GMAC_SPEED_MASK = (1 << RK3288_GMAC_SPEED_SHIFT), + RK3288_GMAC_SPEED_10M = (0 << RK3288_GMAC_SPEED_SHIFT), + RK3288_GMAC_SPEED_100M = (1 << RK3288_GMAC_SPEED_SHIFT), - GMAC_FLOWCTRL_SHIFT = 0x9, - GMAC_FLOWCTRL_MASK = 1, + RK3288_GMAC_FLOWCTRL_SHIFT = 0x9, + RK3288_GMAC_FLOWCTRL_MASK = (1 << RK3288_GMAC_FLOWCTRL_SHIFT), RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6, RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), - HOST_REMAP_SHIFT = 0x5, - HOST_REMAP_MASK = 1 + RK3288_HOST_REMAP_SHIFT = 0x5, + RK3288_HOST_REMAP_MASK = (1 << RK3288_HOST_REMAP_SHIFT), }; /* GRF_SOC_CON2 */ From 115a0cb9a28e0e85c9bf8680c537f087e3b15abc Mon Sep 17 00:00:00 2001 From: Christoph Fritz Date: Wed, 16 Apr 2025 13:45:35 +0200 Subject: [PATCH 28/28] net: gmac_rockchip: Add RMII support for rk3288 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add RMII-specific handling to rk3288_gmac_fix_mac_speed() so that it properly sets the RMII clock (2.5 MHz vs. 25 MHz) and speed bits (10 Mbps vs. 100 Mbps). Also define a new rk3288_gmac_set_to_rmii() function to set the PHY interface field and RMII_MODE bit. Signed-off-by: Christoph Fritz Reviewed-by: Kever Yang --- drivers/net/gmac_rockchip.c | 69 ++++++++++++++++++++++++++++--------- 1 file changed, 53 insertions(+), 16 deletions(-) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 8cfeeffe95b..c8cfe7448d4 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -151,26 +151,51 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) { + struct dw_eth_pdata *dw_pdata = dev_get_plat(priv->dev); + struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; struct rk3288_grf *grf; + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); int clk; - switch (priv->phydev->speed) { - case 10: - clk = RK3288_GMAC_CLK_SEL_2_5M; - break; - case 100: - clk = RK3288_GMAC_CLK_SEL_25M; - break; - case 1000: - clk = RK3288_GMAC_CLK_SEL_125M; - break; - default: - debug("Unknown phy speed: %d\n", priv->phydev->speed); - return -EINVAL; - } + if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { + switch (priv->phydev->speed) { + case 10: + rk_clrsetreg(&grf->soc_con1, + RK3288_RMII_CLK_SEL_MASK | + RK3288_GMAC_SPEED_MASK, + RK3288_RMII_CLK_SEL_2_5M | + RK3288_GMAC_SPEED_10M); + break; + case 100: + rk_clrsetreg(&grf->soc_con1, + RK3288_RMII_CLK_SEL_MASK | + RK3288_GMAC_SPEED_MASK, + RK3288_RMII_CLK_SEL_25M | + RK3288_GMAC_SPEED_100M); + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + } else { + switch (priv->phydev->speed) { + case 10: + clk = RK3288_GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = RK3288_GMAC_CLK_SEL_25M; + break; + case 1000: + clk = RK3288_GMAC_CLK_SEL_125M; + break; - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); + } return 0; } @@ -401,6 +426,17 @@ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata) pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); } +static void rk3288_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) +{ + struct rk3288_grf *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + rk_clrsetreg(&grf->soc_con1, + RK3288_GMAC_PHY_INTF_SEL_MASK | RK3288_RMII_MODE_MASK, + RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_RMII_MODE); +} + static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata) { struct rk3288_grf *grf; @@ -703,6 +739,7 @@ const struct rk_gmac_ops rk3228_gmac_ops = { const struct rk_gmac_ops rk3288_gmac_ops = { .fix_mac_speed = rk3288_gmac_fix_mac_speed, .set_to_rgmii = rk3288_gmac_set_to_rgmii, + .set_to_rmii = rk3288_gmac_set_to_rmii, }; const struct rk_gmac_ops rk3308_gmac_ops = {