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clk: zynqmp: Add set_rate support for display clocks

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If "assigned-clock-rates" property is included in the
device tree, display driver probe is getting failed, as dp_video_ref
till dp_stc_ref clocks are missing from set rate function, adding
them to fix the probe failure.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240711082939.29260-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Venkatesh Yadav Abbarapu
2024-07-11 13:59:39 +05:30
committed by Michal Simek
parent 6becf9ba1a
commit aceac0c52b
1 changed files with 1 additions and 0 deletions
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drivers/clk/clk_zynqmp.c
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@@ -726,6 +726,7 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
case gem_tsu:
case qspi_ref ... can1_ref:
case usb0_bus_ref ... usb3_dual_ref:
case dp_video_ref ... dp_stc_ref:
return zynqmp_clk_set_peripheral_rate(priv, id,
rate, two_divs);
default: