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ram: k3-ddrss: do not touch ctrl regs during training

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During LPDDR initialization we will loop through a series of frequency
changes in order to train at the various operating frequencies. During
this training, accessing the DRAM_CLASS bitfield could happen during a
frequency change and cause the read to hang.

Store the DRAM type into the main structure to avoid multiple readings
while the independent phy is training.

Signed-off-by: Bryan Brattlof <bb@ti.com>
This commit is contained in:
Bryan Brattlof
2023-07-17 17:15:26 -05:00
committed by Tom Rini
parent 7c97b715e9
commit af7c33c103
1 changed files with 4 additions and 7 deletions
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11
drivers/ram/k3-ddrss/k3-ddrss.c
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@@ -138,6 +138,7 @@ struct k3_ddrss_desc {
u32 ddr_freq1; u32 ddr_freq1;
u32 ddr_freq2; u32 ddr_freq2;
u32 ddr_fhs_cnt; u32 ddr_fhs_cnt;
u32 dram_class;
struct udevice *vtt_supply; struct udevice *vtt_supply;
u32 instance; u32 instance;
lpddr4_obj *driverdt; lpddr4_obj *driverdt;
@@ -243,14 +244,11 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
{ {
u32 dram_class;
struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
dram_class = k3_lpddr4_read_ddr_type(pd); switch (ddrss->dram_class) {
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4: case DENALI_CTL_0_DRAM_CLASS_DDR4:
break; break;
case DENALI_CTL_0_DRAM_CLASS_LPDDR4: case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
@@ -263,13 +261,12 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
{ {
u32 dram_class;
int ret; int ret;
lpddr4_privatedata *pd = &ddrss->pd; lpddr4_privatedata *pd = &ddrss->pd;
dram_class = k3_lpddr4_read_ddr_type(pd); ddrss->dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) { switch (ddrss->dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4: case DENALI_CTL_0_DRAM_CLASS_DDR4:
/* Set to ddr_freq1 from DT for DDR4 */ /* Set to ddr_freq1 from DT for DDR4 */
ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);