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powerpc/QorIQ: fix network frame manager TBI PHY address settings

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TBI PHY address (TBIPA) register has been set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c

So remove the duplicate code on QorIQ frame manager Ethernet related
platforms, which include Hydra board, P4080DS board and P2041rdb board.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Roy Zang
2011-10-28 13:15:36 +08:00
committed by Kumar Gala
parent 5721385b18
commit afc52db2f7
3 changed files with 0 additions and 24 deletions
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8
board/freescale/corenet_ds/eth_hydra.c
View File

@@ -377,7 +377,6 @@ void fdt_fixup_board_enet(void *fdt)
int board_eth_init(bd_t *bis) int board_eth_init(bd_t *bis)
{ {
#ifdef CONFIG_FMAN_ENET #ifdef CONFIG_FMAN_ENET
struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info; struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info; struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot; unsigned int i, slot;
@@ -387,13 +386,6 @@ int board_eth_init(bd_t *bis)
initialize_lane_to_slot(); initialize_lane_to_slot();
/*
* Set TBIPA on FM1@DTSEC1. This is needed for configurations
* where FM1@DTSEC1 isn't used directly, since it provides
* MDIO for other ports.
*/
out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
/* We want to use the PIXIS to configure MUX routing, not GPIOs. */ /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);

8
board/freescale/corenet_ds/eth_p4080.c
View File

@@ -301,7 +301,6 @@ int board_eth_init(bd_t *bis)
{ {
#ifdef CONFIG_FMAN_ENET #ifdef CONFIG_FMAN_ENET
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
int i; int i;
struct fsl_pq_mdio_info dtsec_mdio_info; struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info; struct tgec_mdio_info tgec_mdio_info;
@@ -327,13 +326,6 @@ int board_eth_init(bd_t *bis)
SLOT5, /* 17 - Bank 3:D */ SLOT5, /* 17 - Bank 3:D */
}; };
/*
* Set TBIPA on FM1@DTSEC1. This is needed for configurations
* where FM1@DTSEC1 isn't used directly, since it provides
* MDIO for other ports.
*/
out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
/* Initialize the mdio_mux array so we can recognize empty elements */ /* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++) for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE; mdio_mux[i] = EMI_NONE;

8
board/freescale/p2041rdb/eth.c
View File

@@ -139,7 +139,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
int board_eth_init(bd_t *bis) int board_eth_init(bd_t *bis)
{ {
#ifdef CONFIG_FMAN_ENET #ifdef CONFIG_FMAN_ENET
struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info; struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info; struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot; unsigned int i, slot;
@@ -149,13 +148,6 @@ int board_eth_init(bd_t *bis)
initialize_lane_to_slot(); initialize_lane_to_slot();
/*
* Set TBIPA on FM1@DTSEC1. This is needed for configurations
* where FM1@DTSEC1 isn't used directly, since it provides
* MDIO for other ports.
*/
out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
dtsec_mdio_info.regs = dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;