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clk: mediatek: fix uninitialized fields issue in INFRA_MUX struct

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This patch adds missing initialization of fields in INFRA_MUX struct
which caused uart broken after any other infra mux being enabled by
'clk_prepare_enable'

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
2025-01-17 17:16:38 +08:00
committed by Tom Rini
parent 92090b92fa
commit b033dfb21d
3 changed files with 3 additions and 0 deletions
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1
drivers/clk/mediatek/clk-mt7981.c
View File

@@ -359,6 +359,7 @@ static const struct mtk_parent infra_pcie_parents[] = {
.id = _id, .mux_reg = (_reg) + 0x8, \ .id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
.gate_shift = -1, .upd_shift = -1, \
.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
} }

1
drivers/clk/mediatek/clk-mt7986.c
View File

@@ -366,6 +366,7 @@ static const struct mtk_parent infra_pcie_parents[] = {
.id = _id, .mux_reg = (_reg) + 0x8, \ .id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
.gate_shift = -1, .upd_shift = -1, \
.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
} }

1
drivers/clk/mediatek/clk-mt7988.c
View File

@@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
.id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \
.mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .parent = _parents, \ .mux_mask = BIT(_width) - 1, .parent = _parents, \
.gate_shift = -1, .upd_shift = -1, \
.num_parents = ARRAY_SIZE(_parents), \ .num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \
} }