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arch: arm: dts: agilex5: Set SDIO_SEL GPIO pin as output

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Use GPIO hogging method in device tree to set SDIO_SEL pin (portb3)
direction as output with value 0 after power-on reset.

This is to ensure stable 0V voltage reading from SDIO_SEL GPIO pin
after board init.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This commit is contained in:
Alif Zakuan Yuslaimi
2025-04-16 01:42:12 -07:00
committed by Tien Fong Chee
parent 577a60760e
commit b0dbc9fcb7
2 changed files with 14 additions and 0 deletions
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11
arch/arm/dts/socfpga_agilex5-u-boot.dtsi
View File

@@ -673,6 +673,17 @@
bootph-all; bootph-all;
}; };
&gpio1 {
/* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */
portb: gpio-controller@0{
sdio_sel {
gpio-hog;
gpios = <3 GPIO_ACTIVE_HIGH>;
output-low;
};
};
};
&i2c0 { &i2c0 {
reset-names = "i2c"; reset-names = "i2c";
}; };

3
configs/socfpga_agilex5_defconfig
View File

@@ -1,6 +1,7 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_TEXT_BASE=0x80200000 CONFIG_TEXT_BASE=0x80200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=3 CONFIG_NR_DRAM_BANKS=3
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000
@@ -75,6 +76,8 @@ CONFIG_BOOTFILE="kernel.itb"
CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y CONFIG_SPL_ALTERA_SDRAM=y
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_DWAPB_GPIO=y CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y CONFIG_SYS_I2C_DW=y