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drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue

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Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue

Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Oliver Chen
2020-04-21 14:48:09 +08:00
committed by Peng Fan
parent 3f63d27c17
commit b335966958
4 changed files with 177 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/include/asm/arch-imx8m/ddr.h
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@@ -721,6 +721,9 @@ int wait_ddrphy_training_complete(void);
void ddrphy_init_set_dfi_clk(unsigned int drate);
void ddrphy_init_read_msg_block(enum fw_type type);
void update_umctl2_rank_space_setting(unsigned int pstat_num);
void get_trained_CDD(unsigned int fsp);
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);

3
drivers/ddr/imx/imx8m/ddr_init.c
View File

@@ -190,6 +190,9 @@ int ddr_init(struct dram_timing_info *dram_timing)
/* Step15: Set SWCTL.sw_done to 0 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
/* Apply rank-to-rank workaround */
update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1);
/* Step16: Set DFIMISC.dfi_init_start to 1 */
setbits_le32(DDRC_DFIMISC(0), (0x1 << 5));

7
drivers/ddr/imx/imx8m/ddrphy_train.c
View File

@@ -8,6 +8,7 @@
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
#include <asm/arch/sys_proto.h>
int ddr_cfg_phy(struct dram_timing_info *dram_timing)
{
@@ -71,9 +72,15 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
/* Read the Message Block results */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
ddrphy_init_read_msg_block(fsp_msg->fw_type);
if(fsp_msg->fw_type != FW_2D_IMAGE)
get_trained_CDD(i);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
fsp_msg++;
}

164
drivers/ddr/imx/imx8m/ddrphy_utils.c
View File

@@ -11,6 +11,12 @@
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
#include <asm/arch/sys_proto.h>
static unsigned int g_cdd_rr_max[4];
static unsigned int g_cdd_rw_max[4];
static unsigned int g_cdd_wr_max[4];
static unsigned int g_cdd_ww_max[4];
static inline void poll_pmu_message_ready(void)
{
@@ -193,3 +199,161 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
return tmp;
}
unsigned int look_for_max(unsigned int data[],
unsigned int addr_start, unsigned int addr_end)
{
unsigned int i, imax = 0;
for (i = addr_start; i <= addr_end; i++) {
if (((data[i] >> 7) == 0) && (data[i] > imax))
imax = data[i];
}
return imax;
}
void get_trained_CDD(u32 fsp)
{
unsigned int i, ddr_type, tmp;
unsigned int cdd_cha[12], cdd_chb[12];
unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
if (ddr_type == 0x20) {
for (i = 0; i < 6; i++) {
tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4);
cdd_cha[i * 2] = tmp & 0xff;
cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
}
for (i = 0; i < 7; i++) {
tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4);
if (i == 0) {
cdd_cha[0] = (tmp >> 8) & 0xff;
} else if (i == 6) {
cdd_cha[11]=tmp & 0xff;
} else {
cdd_chb[ i * 2 - 1] = tmp & 0xff;
cdd_chb[i * 2] = (tmp >> 8) & 0xff;
}
}
cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
} else {
unsigned int ddr4_cdd[64];
for( i = 0; i < 29; i++) {
tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
ddr4_cdd[i * 2] = tmp & 0xff;
ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
}
g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
}
}
void update_umctl2_rank_space_setting(unsigned int pstat_num)
{
unsigned int i,ddr_type;
unsigned int addr_slot, rdata, tmp, tmp_t;
unsigned int ddrc_w2r,ddrc_r2w,ddrc_wr_gap,ddrc_rd_gap;
ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
for (i = 0; i < pstat_num; i++) {
addr_slot = i ? (i + 1) * 0x1000 : 0;
if (ddr_type == 0x20) {
/* update r2w:[13:8], w2r:[5:0] */
rdata=reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
ddrc_w2r = rdata & 0x3f;
if(is_imx8mp())
tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
else
tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
ddrc_r2w = (rdata >> 8) & 0x3f;
if (is_imx8mp())
tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
else
tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
} else {
/* update w2r:[5:0] */
rdata=reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
ddrc_w2r = rdata & 0x3f;
if (is_imx8mp())
tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
else
tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
/* update r2w:[13:8] */
rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
ddrc_r2w = (rdata >> 8) & 0x3f;
if(is_imx8mp())
tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
else
tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
}
if (!is_imx8mq()) {
/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
ddrc_wr_gap = (rdata >> 8) & 0xf;
if(is_imx8mp())
tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
else
tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
ddrc_rd_gap = (rdata >> 4) & 0xf;
if (is_imx8mp())
tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
else
tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
}
}
if(is_imx8mq()) {
/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
rdata = reg32_read(DDRC_RANKCTL(0));
ddrc_wr_gap = (rdata >> 8) & 0xf;
tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
ddrc_rd_gap = (rdata >> 4) & 0xf;
tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
reg32_write(DDRC_RANKCTL(0), tmp_t);
}
}