From 967eebcd85865b795351bfe4e77399b9f414c6c5 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 16 May 2025 14:53:14 +0530 Subject: [PATCH 1/5] pci: zynqmp: Fix the pcireg base The pcireg base is not assigned to any address, reading the pcireg base with PS_LINKUP_OFFSET which is incorrect and giving random values. So update the pcireg base from devicetree so that we can read the valid PCIE link status and PHY ready status. Signed-off-by: Venkatesh Yadav Abbarapu Reviewed-by: Stefan Roese Link: https://lore.kernel.org/r/20250516092314.939424-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/pci/pcie-xilinx-nwl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c index 7ef2bdf57b5..e03ab3be912 100644 --- a/drivers/pci/pcie-xilinx-nwl.c +++ b/drivers/pci/pcie-xilinx-nwl.c @@ -303,6 +303,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie) return PTR_ERR(pcie->breg_base); pcie->phys_breg_base = res.start; + ret = dev_read_resource_byname(dev, "pcireg", &res); + if (ret) + return ret; + pcie->pcireg_base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(pcie->pcireg_base)) + return PTR_ERR(pcie->pcireg_base); + ret = dev_read_resource_byname(dev, "cfg", &res); if (ret) return ret; From 85f181b194c7d3810db4a0df8ea2386287b26be0 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 5 May 2025 18:28:51 -0700 Subject: [PATCH 2/5] drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration FPGA configuration encounters failure when the cache is not flushed. Add cache flushing to the memory region that holds the FPGA configuration bitstream. Signed-off-by: Naresh Kumar Ravulapalli Link: https://lore.kernel.org/r/20250506012851.30039-1-nareshkumar.ravulapalli@altera.com Signed-off-by: Michal Simek --- drivers/fpga/intel_sdm_mb.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 5fe4dbdfd32..a2f3b160a73 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018 Intel Corporation + * Copyright (C) 2025 Altera Corporation */ #include @@ -9,6 +10,8 @@ #include #include #include +#include +#include #include #include #include @@ -738,6 +741,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) debug("Invoking FPGA_CONFIG_START...\n"); + flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size)); + ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0); if (ret) { @@ -1023,6 +1028,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) u32 resp_len = 2; u32 resp_buf[2]; + flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size)); + debug("Sending MBOX_RECONFIG...\n"); ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0, NULL, 0, &resp_len, resp_buf); From 90df44fb4f0e1cbe18b02080ef8bf9e365f867b8 Mon Sep 17 00:00:00 2001 From: Frantisek Bohacek Date: Thu, 22 May 2025 08:07:03 +0200 Subject: [PATCH 3/5] phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift The bitshift in GEM_CLK_CTRL register is five bits, not two. There are four bits for each GEM, and one bit reserved in between. This has caused that using more than one GEM is impossible, additionally corrupting the GEM0's configuration, leaving GEM0 unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is going to write to GEM0's registers wrong value, leaving GEM0 unusable) Signed-off-by: Frantisek Bohacek Link: https://lore.kernel.org/r/20250522060703.4863-1-rutherther@ditigal.xyz Signed-off-by: Michal Simek --- drivers/phy/phy-zynqmp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c index 7049e740d56..9649e660220 100644 --- a/drivers/phy/phy-zynqmp.c +++ b/drivers/phy/phy-zynqmp.c @@ -138,6 +138,7 @@ #define PROT_BUS_WIDTH_40 0x2 #define PROT_BUS_WIDTH_MASK 0x3 #define PROT_BUS_WIDTH_SHIFT 2 +#define GEM_CLK_CTRL_WIDTH_SHIFT 5 /* Number of GT lanes */ #define NUM_LANES 4 @@ -400,6 +401,7 @@ static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy) { struct xpsgtr_dev *gtr_dev = gtr_phy->dev; u32 shift = gtr_phy->lane * PROT_BUS_WIDTH_SHIFT; + u32 clk_ctrl_shift = gtr_phy->lane * GEM_CLK_CTRL_WIDTH_SHIFT; /* Set SGMII protocol TX and RX bus width to 10 bits. */ xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, PROT_BUS_WIDTH_MASK << shift, @@ -417,9 +419,9 @@ static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy) */ /* GEM I/O Clock Control */ clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CLK_CTRL, - 0xf << shift, + 0xf << clk_ctrl_shift, (GEM_CTRL_GEM_SGMII_MODE | GEM_CTRL_GEM_REF_SRC_SEL) << - shift); + clk_ctrl_shift); /* Setup signal detect */ clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CTRL, From 6759bd73e9cf491c5049f87b84e627920efb5824 Mon Sep 17 00:00:00 2001 From: Martin Kaistra Date: Tue, 15 Apr 2025 17:04:00 +0200 Subject: [PATCH 4/5] net: gem: ignore tx_clk if MII is used If the MII interface is used, the PHY is the clock master, thus don't set the clock rate. On Zynq-7000, this will prevent the following error: zynq_gem ethernet@e000b000: failed to set tx clock rate 25000000 Signed-off-by: Martin Kaistra Link: https://lore.kernel.org/r/20250415150400.136723-1-martin.kaistra@linutronix.de Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 461805ae53f..703e22479d2 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -567,12 +567,14 @@ static int zynq_gem_init(struct udevice *dev) } #endif - ret = clk_get_rate(&priv->tx_clk); - if (ret != clk_rate) { - ret = clk_set_rate(&priv->tx_clk, clk_rate); - if (IS_ERR_VALUE(ret)) { - dev_err(dev, "failed to set tx clock rate %ld\n", clk_rate); - return ret; + if (priv->interface != PHY_INTERFACE_MODE_MII) { + ret = clk_get_rate(&priv->tx_clk); + if (ret != clk_rate) { + ret = clk_set_rate(&priv->tx_clk, clk_rate); + if (IS_ERR_VALUE(ret)) { + dev_err(dev, "failed to set tx clock rate %ld\n", clk_rate); + return ret; + } } } From 77b053502f396e83f6a0ea38d747d6836dc501f0 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Fri, 11 Apr 2025 07:55:38 +0200 Subject: [PATCH 5/5] usb: onboard-hub: Fix return type for regulator APIs Apart from ENOENT observing return value as ENOSYS when !DM_REGULATOR that's why cover both configurations. Changed code is not working as operation should be "&&" not "||" (ret != -ENOENT && ret != -ENOSYS). Also fix the remove function where the regulator_set_enable_if_allowed() function is returning an error. Signed-off-by: Padmarao Begari Reviewed-by: Marek Vasut Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a2d520f14efc30fc28ec59881205e156dabbfcd9.1744350937.git.michal.simek@amd.com --- common/usb_onboard_hub.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c index 7fe62b043e6..d17c85dd622 100644 --- a/common/usb_onboard_hub.c +++ b/common/usb_onboard_hub.c @@ -146,7 +146,7 @@ static int usb_onboard_hub_probe(struct udevice *dev) int ret; ret = device_get_supply_regulator(dev, "vdd-supply", &hub->vdd); - if (ret && ret != -ENOENT) { + if (ret && ret != -ENOENT && ret != -ENOSYS) { dev_err(dev, "can't get vdd-supply: %d\n", ret); return ret; } @@ -204,14 +204,16 @@ static int usb_onboard_hub_bind(struct udevice *dev) static int usb_onboard_hub_remove(struct udevice *dev) { struct onboard_hub *hub = dev_get_priv(dev); - int ret; + int ret = 0; if (hub->reset_gpio) dm_gpio_free(hub->reset_gpio->dev, hub->reset_gpio); - ret = regulator_set_enable_if_allowed(hub->vdd, false); - if (ret) - dev_err(dev, "can't disable vdd-supply: %d\n", ret); + if (hub->vdd) { + ret = regulator_set_enable_if_allowed(hub->vdd, false); + if (ret) + dev_err(dev, "can't disable vdd-supply: %d\n", ret); + } return ret; }