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arm:mx6sx add QSPI support

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Add QSPI support for mx6solox.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This commit is contained in:
Peng Fan
2014-12-31 11:01:38 +08:00
committed by Jagannadha Sutradharudu Teki
parent ed0c81c654
commit b93ab2ee75
4 changed files with 76 additions and 6 deletions
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1
arch/arm/include/asm/arch-mx6/clock.h
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@@ -67,5 +67,6 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);
#endif /* __ASM_ARCH_CLOCK_H */

12
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@@ -92,10 +92,10 @@
#define AIPS3_END_ADDR 0x022FFFFF
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI1_ARB_BASE_ADDR 0x60000000
#define QSPI1_ARB_END_ADDR 0x6FFFFFFF
#define QSPI2_ARB_BASE_ADDR 0x70000000
#define QSPI2_ARB_END_ADDR 0x7FFFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
#define QSPI1_AMBA_BASE 0x70000000
#define QSPI1_AMBA_END 0x7FFFFFFF
#else
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
@@ -262,8 +262,8 @@
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#ifdef CONFIG_MX6SX
#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#else
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)