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dts: qcs404-evb: Add I2C controller nodes

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Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg
2023-02-01 19:29:01 +05:30
committed by Tom Rini
parent 9bdec960b2
commit baf0677b74
1 changed files with 97 additions and 0 deletions
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97
arch/arm/dts/qcs404-evb.dts
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@@ -23,6 +23,11 @@
aliases {
serial0 = &debug_uart;
i2c0 = &blsp1_i2c0;
i2c1 = &blsp1_i2c1;
i2c2 = &blsp1_i2c2;
i2c3 = &blsp1_i2c3;
i2c4 = &blsp1_i2c4;
};
memory {
@@ -49,6 +54,38 @@
function = "blsp_uart2";
};
blsp1_i2c0_default: blsp1-i2c0-default {
pins = "GPIO_32", "GPIO_33";
function = "blsp_i2c0";
};
blsp1_i2c1_default: blsp1-i2c1-default {
pins = "GPIO_24", "GPIO_25";
function = "blsp_i2c1";
};
blsp1_i2c2_default: blsp1-i2c2-default {
sda {
pins = "GPIO_19";
function = "blsp_i2c_sda_a2";
};
scl {
pins = "GPIO_20";
function = "blsp_i2c_scl_a2";
};
};
blsp1_i2c3_default: blsp1-i2c3-default {
pins = "GPIO_84", "GPIO_85";
function = "blsp_i2c3";
};
blsp1_i2c4_default: blsp1-i2c4-default {
pins = "GPIO_117", "GPIO_118";
function = "blsp_i2c4";
};
ethernet_defaults: ethernet-defaults {
int {
pins = "GPIO_61";
@@ -105,6 +142,66 @@
};
};
blsp1_i2c0: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c0_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c1: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c1_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c2: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c2_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c3: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c3_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c4: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c4_default>;
#address-cells = <1>;
#size-cells = <0>;
};
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-qcs404";
reg = <0x1800000 0x80000>;