Merge branch 'master' into hpc2
This commit is contained in:
roy zang
@@ -36,6 +36,8 @@
|
||||
/* include armadillo specific hardware file if there was one */
|
||||
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
|
||||
/* include IntegratorCP/CM720T specific hardware file if there was one */
|
||||
#elif defined(CONFIG_LPC2292)
|
||||
#include <asm-arm/arch-arm720t/lpc2292_registers.h>
|
||||
#else
|
||||
#error No hardware file defined for this configuration
|
||||
#endif
|
||||
|
||||
225
include/asm-arm/arch-arm720t/lpc2292_registers.h
Normal file
225
include/asm-arm/arch-arm720t/lpc2292_registers.h
Normal file
@@ -0,0 +1,225 @@
|
||||
#ifndef __LPC2292_REGISTERS_H
|
||||
#define __LPC2292_REGISTERS_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* Macros for reading/writing registers */
|
||||
#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
|
||||
#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
|
||||
#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
|
||||
#define GET8(reg) (*(volatile unsigned char*)(reg))
|
||||
#define GET16(reg) (*(volatile unsigned short*)(reg))
|
||||
#define GET32(reg) (*(volatile unsigned int*)(reg))
|
||||
|
||||
/* External Memory Controller */
|
||||
|
||||
#define BCFG0 0xFFE00000 /* 32-bits */
|
||||
#define BCFG1 0xFFE00004 /* 32-bits */
|
||||
#define BCFG2 0xFFE00008 /* 32-bits */
|
||||
#define BCFG3 0xFFE0000c /* 32-bits */
|
||||
|
||||
/* System Control Block */
|
||||
|
||||
#define EXTINT 0xE01FC140
|
||||
#define EXTWAKE 0xE01FC144
|
||||
#define EXTMODE 0xE01FC148
|
||||
#define EXTPOLAR 0xE01FC14C
|
||||
#define MEMMAP 0xE01FC040
|
||||
#define PLLCON 0xE01FC080
|
||||
#define PLLCFG 0xE01FC084
|
||||
#define PLLSTAT 0xE01FC088
|
||||
#define PLLFEED 0xE01FC08C
|
||||
#define PCON 0xE01FC0C0
|
||||
#define PCONP 0xE01FC0C4
|
||||
#define VPBDIV 0xE01FC100
|
||||
|
||||
/* Memory Acceleration Module */
|
||||
|
||||
#define MAMCR 0xE01FC000
|
||||
#define MAMTIM 0xE01FC004
|
||||
|
||||
/* Vectored Interrupt Controller */
|
||||
|
||||
#define VICIRQStatus 0xFFFFF000
|
||||
#define VICFIQStatus 0xFFFFF004
|
||||
#define VICRawIntr 0xFFFFF008
|
||||
#define VICIntSelect 0xFFFFF00C
|
||||
#define VICIntEnable 0xFFFFF010
|
||||
#define VICIntEnClr 0xFFFFF014
|
||||
#define VICSoftInt 0xFFFFF018
|
||||
#define VICSoftIntClear 0xFFFFF01C
|
||||
#define VICProtection 0xFFFFF020
|
||||
#define VICVectAddr 0xFFFFF030
|
||||
#define VICDefVectAddr 0xFFFFF034
|
||||
#define VICVectAddr0 0xFFFFF100
|
||||
#define VICVectAddr1 0xFFFFF104
|
||||
#define VICVectAddr2 0xFFFFF108
|
||||
#define VICVectAddr3 0xFFFFF10C
|
||||
#define VICVectAddr4 0xFFFFF110
|
||||
#define VICVectAddr5 0xFFFFF114
|
||||
#define VICVectAddr6 0xFFFFF118
|
||||
#define VICVectAddr7 0xFFFFF11C
|
||||
#define VICVectAddr8 0xFFFFF120
|
||||
#define VICVectAddr9 0xFFFFF124
|
||||
#define VICVectAddr10 0xFFFFF128
|
||||
#define VICVectAddr11 0xFFFFF12C
|
||||
#define VICVectAddr12 0xFFFFF130
|
||||
#define VICVectAddr13 0xFFFFF134
|
||||
#define VICVectAddr14 0xFFFFF138
|
||||
#define VICVectAddr15 0xFFFFF13C
|
||||
#define VICVectCntl0 0xFFFFF200
|
||||
#define VICVectCntl1 0xFFFFF204
|
||||
#define VICVectCntl2 0xFFFFF208
|
||||
#define VICVectCntl3 0xFFFFF20C
|
||||
#define VICVectCntl4 0xFFFFF210
|
||||
#define VICVectCntl5 0xFFFFF214
|
||||
#define VICVectCntl6 0xFFFFF218
|
||||
#define VICVectCntl7 0xFFFFF21C
|
||||
#define VICVectCntl8 0xFFFFF220
|
||||
#define VICVectCntl9 0xFFFFF224
|
||||
#define VICVectCntl10 0xFFFFF228
|
||||
#define VICVectCntl11 0xFFFFF22C
|
||||
#define VICVectCntl12 0xFFFFF230
|
||||
#define VICVectCntl13 0xFFFFF234
|
||||
#define VICVectCntl14 0xFFFFF238
|
||||
#define VICVectCntl15 0xFFFFF23C
|
||||
|
||||
/* Pin connect block */
|
||||
|
||||
#define PINSEL0 0xE002C000 /* 32 bits */
|
||||
#define PINSEL1 0xE002C004 /* 32 bits */
|
||||
#define PINSEL2 0xE002C014 /* 32 bits */
|
||||
|
||||
/* GPIO */
|
||||
|
||||
#define IO0PIN 0xE0028000
|
||||
#define IO0SET 0xE0028004
|
||||
#define IO0DIR 0xE0028008
|
||||
#define IO0CLR 0xE002800C
|
||||
#define IO1PIN 0xE0028010
|
||||
#define IO1SET 0xE0028014
|
||||
#define IO1DIR 0xE0028018
|
||||
#define IO1CLR 0xE002801C
|
||||
#define IO2PIN 0xE0028020
|
||||
#define IO2SET 0xE0028024
|
||||
#define IO2DIR 0xE0028028
|
||||
#define IO2CLR 0xE002802C
|
||||
#define IO3PIN 0xE0028030
|
||||
#define IO3SET 0xE0028034
|
||||
#define IO3DIR 0xE0028038
|
||||
#define IO3CLR 0xE002803C
|
||||
|
||||
/* Uarts */
|
||||
|
||||
#define U0RBR 0xE000C000
|
||||
#define U0THR 0xE000C000
|
||||
#define U0IER 0xE000C004
|
||||
#define U0IIR 0xE000C008
|
||||
#define U0FCR 0xE000C008
|
||||
#define U0LCR 0xE000C00C
|
||||
#define U0LSR 0xE000C014
|
||||
#define U0SCR 0xE000C01C
|
||||
#define U0DLL 0xE000C000
|
||||
#define U0DLM 0xE000C004
|
||||
|
||||
#define U1RBR 0xE0010000
|
||||
#define U1THR 0xE0010000
|
||||
#define U1IER 0xE0010004
|
||||
#define U1IIR 0xE0010008
|
||||
#define U1FCR 0xE0010008
|
||||
#define U1LCR 0xE001000C
|
||||
#define U1MCR 0xE0010010
|
||||
#define U1LSR 0xE0010014
|
||||
#define U1MSR 0xE0010018
|
||||
#define U1SCR 0xE001001C
|
||||
#define U1DLL 0xE0010000
|
||||
#define U1DLM 0xE0010004
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define I2CONSET 0xE001C000
|
||||
#define I2STAT 0xE001C004
|
||||
#define I2DAT 0xE001C008
|
||||
#define I2ADR 0xE001C00C
|
||||
#define I2SCLH 0xE001C010
|
||||
#define I2SCLL 0xE001C014
|
||||
#define I2CONCLR 0xE001C018
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define S0SPCR 0xE0020000
|
||||
#define S0SPSR 0xE0020004
|
||||
#define S0SPDR 0xE0020008
|
||||
#define S0SPCCR 0xE002000C
|
||||
#define S0SPINT 0xE002001C
|
||||
|
||||
#define S1SPCR 0xE0030000
|
||||
#define S1SPSR 0xE0030004
|
||||
#define S1SPDR 0xE0030008
|
||||
#define S1SPCCR 0xE003000C
|
||||
#define S1SPINT 0xE003001C
|
||||
|
||||
/* CAN controller */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define T0IR 0xE0004000
|
||||
#define T0TCR 0xE0004004
|
||||
#define T0TC 0xE0004008
|
||||
#define T0PR 0xE000400C
|
||||
#define T0PC 0xE0004010
|
||||
#define T0MCR 0xE0004014
|
||||
#define T0MR0 0xE0004018
|
||||
#define T0MR1 0xE000401C
|
||||
#define T0MR2 0xE0004020
|
||||
#define T0MR3 0xE0004024
|
||||
#define T0CCR 0xE0004028
|
||||
#define T0CR0 0xE000402C
|
||||
#define T0CR1 0xE0004030
|
||||
#define T0CR2 0xE0004034
|
||||
#define T0CR3 0xE0004038
|
||||
#define T0EMR 0xE000403C
|
||||
|
||||
#define T1IR 0xE0008000
|
||||
#define T1TCR 0xE0008004
|
||||
#define T1TC 0xE0008008
|
||||
#define T1PR 0xE000800C
|
||||
#define T1PC 0xE0008010
|
||||
#define T1MCR 0xE0008014
|
||||
#define T1MR0 0xE0008018
|
||||
#define T1MR1 0xE000801C
|
||||
#define T1MR2 0xE0008020
|
||||
#define T1MR3 0xE0008024
|
||||
#define T1CCR 0xE0008028
|
||||
#define T1CR0 0xE000802C
|
||||
#define T1CR1 0xE0008030
|
||||
#define T1CR2 0xE0008034
|
||||
#define T1CR3 0xE0008038
|
||||
#define T1EMR 0xE000803C
|
||||
|
||||
/* PWM */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* A/D converter */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* Real Time Clock */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* Watchdog */
|
||||
|
||||
#define WDMOD 0xE0000000
|
||||
#define WDTC 0xE0000004
|
||||
#define WDFEED 0xE0000008
|
||||
#define WDTV 0xE000000C
|
||||
|
||||
/* EmbeddedICE LOGIC */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
#endif
|
||||
22
include/asm-arm/arch-arm720t/mmc.h
Normal file
22
include/asm-arm/arch-arm720t/mmc.h
Normal file
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* A dummy header file for use with the LPC2292 port to keep the
|
||||
* compiler happy.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MMC_ARM_TDM_H_
|
||||
#define _MMC_ARM_TDM_H_
|
||||
#endif /* _MMC_ARM_TDM_H_ */
|
||||
@@ -57,6 +57,12 @@
|
||||
#define MCF_GPIO_PAR_FECI2C 0x100047
|
||||
#define MCF_GPIO_PAR_UART 0x100048
|
||||
|
||||
#define MCF_CCM_CIR 0x11000A
|
||||
#define MCF_CCM_CIR_PRN_MASK 0x3F
|
||||
#define MCF_CCM_CIR_PIN_LEN 6
|
||||
#define MCF_CCM_CIR_PIN_MCF5270 0x2e
|
||||
#define MCF_CCM_CIR_PIN_MCF5271 0x80
|
||||
|
||||
#define MCF_GPIO_AD_ADDR23 0x80
|
||||
#define MCF_GPIO_AD_ADDR22 0x40
|
||||
#define MCF_GPIO_AD_ADDR21 0x20
|
||||
|
||||
@@ -83,8 +83,8 @@
|
||||
*/
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_MII) & \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_NET) & \
|
||||
~(CFG_CMD_LOADS | \
|
||||
CFG_CMD_LOADB))
|
||||
|
||||
@@ -194,4 +194,20 @@
|
||||
|
||||
/* Port configuration */
|
||||
#define CFG_FECI2C 0xF0
|
||||
|
||||
|
||||
/* Dynamic MTD partition support */
|
||||
#define CONFIG_JFFS2_CMDLINE
|
||||
#define MTDIDS_DEFAULT "nor0=idmr-0"
|
||||
|
||||
#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \
|
||||
"64k(env)," \
|
||||
"640k(kernel)," \
|
||||
"2m(rootfs)," \
|
||||
"-(user)";
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_MII)
|
||||
#error MII commands don't work on iDMR board and sholud not be enabled.
|
||||
#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */
|
||||
|
||||
#endif /* _IDMR_H */
|
||||
|
||||
158
include/configs/lpc2292sodimm.h
Normal file
158
include/configs/lpc2292sodimm.h
Normal file
@@ -0,0 +1,158 @@
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* Configuation settings for the EP7312 board.
|
||||
*
|
||||
* Modified to work on Armadillo HT1070 ARM720T board
|
||||
* (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#undef CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
|
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
|
||||
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
|
||||
#define CONFIG_LPC2292
|
||||
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
|
||||
|
||||
#undef CONFIG_USE_IRQ /* don't need them anymore */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_MMC | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_PING)
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "LPC2292SODIMM # " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x40000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x40000000 /* 4 ... 8 MB in DRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/
|
||||
|
||||
#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
|
||||
#define CFG_HZ 2048 /* decrementer freq in Hz */
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x81000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB SDRAM */
|
||||
|
||||
#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_SIZE 0x00200000 /* 2 MB */
|
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
|
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (0x0 + 0x3C000) /* Addr of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_MMC 1
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -304,6 +304,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
||||
|
||||
#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */
|
||||
#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */
|
||||
#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal FLASH identification codes
|
||||
|
||||
Reference in New Issue
Block a user