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arm: socfpga: Disable GIC for Agilex5

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Status polling is used instead of using interrupt controller for Agilex5.

Disabling GICV3 in Agilex5 target, as well as disabling GICV2 enabled by
default for all SoCFPGA devices.

All the other SoCFPGA devices uses GICV2, thus enabling GICV2 in each of
the devices.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This commit is contained in:
Alif Zakuan Yuslaimi
2025-02-18 16:34:52 +08:00
committed by Tom Rini
parent 9288e0b446
commit cad50a19f5
2 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
View File

@@ -1128,7 +1128,6 @@ config ARCH_SOCFPGA
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM select DM
select DM_SERIAL select DM_SERIAL
select GICV2
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL select OF_CONTROL

5
arch/arm/mach-socfpga/Kconfig
View File

@@ -55,6 +55,7 @@ config TARGET_SOCFPGA_AGILEX
select BINMAN if SPL_ATF select BINMAN if SPL_ATF
select CLK select CLK
select FPGA_INTEL_SDM_MAILBOX select FPGA_INTEL_SDM_MAILBOX
select GICV2
select NCORE_CACHE select NCORE_CACHE
select SPL_CLK if SPL select SPL_CLK if SPL
select TARGET_SOCFPGA_SOC64 select TARGET_SOCFPGA_SOC64
@@ -64,7 +65,6 @@ config TARGET_SOCFPGA_AGILEX5
select BINMAN if SPL_ATF select BINMAN if SPL_ATF
select CLK select CLK
select FPGA_INTEL_SDM_MAILBOX select FPGA_INTEL_SDM_MAILBOX
select GICV3
select SPL_CLK if SPL select SPL_CLK if SPL
select TARGET_SOCFPGA_SOC64 select TARGET_SOCFPGA_SOC64
@@ -74,6 +74,7 @@ config TARGET_SOCFPGA_ARRIA5
config TARGET_SOCFPGA_ARRIA10 config TARGET_SOCFPGA_ARRIA10
bool bool
select GICV2
select SPL_ALTERA_SDRAM select SPL_ALTERA_SDRAM
select SPL_BOARD_INIT if SPL select SPL_BOARD_INIT if SPL
select SPL_CACHE if SPL select SPL_CACHE if SPL
@@ -118,6 +119,7 @@ config TARGET_SOCFPGA_N5X
select ARMV8_SET_SMPEN select ARMV8_SET_SMPEN
select BINMAN if SPL_ATF select BINMAN if SPL_ATF
select CLK select CLK
select GICV2
select FPGA_INTEL_SDM_MAILBOX select FPGA_INTEL_SDM_MAILBOX
select NCORE_CACHE select NCORE_CACHE
select SPL_ALTERA_SDRAM select SPL_ALTERA_SDRAM
@@ -137,6 +139,7 @@ config TARGET_SOCFPGA_STRATIX10
select ARMV8_SET_SMPEN select ARMV8_SET_SMPEN
select BINMAN if SPL_ATF select BINMAN if SPL_ATF
select FPGA_INTEL_SDM_MAILBOX select FPGA_INTEL_SDM_MAILBOX
select GICV2
select TARGET_SOCFPGA_SOC64 select TARGET_SOCFPGA_SOC64
choice choice