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arm: a37xx: pci: Cleanup macro names

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Remove "PCI_" prefix from all macros which are aardvark specific to not
conflict with macros defined in global include file pci.h. Instead add
"ADVK_" prefix for them so it is visible that they are aardvark specific.

After "ADVK_" prefix append keyword which describes register group, so it
would be clear to which register each macro value belongs.

Rename some macros for consistency with other macros.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár
2022-02-10 14:53:43 +01:00
committed by Stefan Roese
parent 819a43c90a
commit cf2a589a89
1 changed files with 188 additions and 198 deletions
Download Patch File Download Diff File Expand all files Collapse all files

386
drivers/pci/pci-aardvark.c
View File

@@ -40,113 +40,104 @@
#define ADVK_ROOT_PORT_PCI_EXP_OFF 0xc0 #define ADVK_ROOT_PORT_PCI_EXP_OFF 0xc0
#define ADVK_ROOT_PORT_PCI_ERR_OFF 0x100 #define ADVK_ROOT_PORT_PCI_ERR_OFF 0x100
/* PIO registers base address and register offsets */ /* PIO registers */
#define PIO_BASE_ADDR 0x4000 #define ADVK_PIO_BASE_ADDR 0x4000
#define PIO_CTRL (PIO_BASE_ADDR + 0x0) #define ADVK_PIO_CTRL (ADVK_PIO_BASE_ADDR + 0x0)
#define PIO_CTRL_TYPE_MASK GENMASK(3, 0) #define ADVK_PIO_CTRL_TYPE_MASK GENMASK(3, 0)
#define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) #define ADVK_PIO_CTRL_TYPE_SHIFT 0
#define PIO_STAT (PIO_BASE_ADDR + 0x4) #define ADVK_PIO_CTRL_TYPE_RD_TYPE0 0x8
#define PIO_COMPLETION_STATUS_SHIFT 7 #define ADVK_PIO_CTRL_TYPE_RD_TYPE1 0x9
#define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) #define ADVK_PIO_CTRL_TYPE_WR_TYPE0 0xa
#define PIO_COMPLETION_STATUS_OK 0 #define ADVK_PIO_CTRL_TYPE_WR_TYPE1 0xb
#define PIO_COMPLETION_STATUS_UR 1 #define ADVK_PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
#define PIO_COMPLETION_STATUS_CRS 2 #define ADVK_PIO_STAT (ADVK_PIO_BASE_ADDR + 0x4)
#define PIO_COMPLETION_STATUS_CA 4 #define ADVK_PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
#define PIO_NON_POSTED_REQ BIT(10) #define ADVK_PIO_COMPLETION_STATUS_SHIFT 7
#define PIO_ERR_STATUS BIT(11) #define ADVK_PIO_COMPLETION_STATUS_OK 0
#define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) #define ADVK_PIO_COMPLETION_STATUS_UR 1
#define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) #define ADVK_PIO_COMPLETION_STATUS_CRS 2
#define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) #define ADVK_PIO_COMPLETION_STATUS_CA 4
#define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) #define ADVK_PIO_NON_POSTED_REQ BIT(10)
#define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) #define ADVK_PIO_ERR_STATUS BIT(11)
#define PIO_START (PIO_BASE_ADDR + 0x1c) #define ADVK_PIO_ADDR_LS (ADVK_PIO_BASE_ADDR + 0x8)
#define PIO_ISR (PIO_BASE_ADDR + 0x20) #define ADVK_PIO_ADDR_MS (ADVK_PIO_BASE_ADDR + 0xc)
#define ADVK_PIO_WR_DATA (ADVK_PIO_BASE_ADDR + 0x10)
#define ADVK_PIO_WR_DATA_STRB (ADVK_PIO_BASE_ADDR + 0x14)
#define ADVK_PIO_RD_DATA (ADVK_PIO_BASE_ADDR + 0x18)
#define ADVK_PIO_START (ADVK_PIO_BASE_ADDR + 0x1c)
#define ADVK_PIO_ISR (ADVK_PIO_BASE_ADDR + 0x20)
/* Aardvark Control registers */ /* Global Control registers */
#define CONTROL_BASE_ADDR 0x4800 #define ADVK_GLOBAL_CTRL_BASE_ADDR 0x4800
#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) #define ADVK_GLOBAL_CTRL0 (ADVK_GLOBAL_CTRL_BASE_ADDR + 0x0)
#define PCIE_GEN_SEL_MSK 0x3 #define ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK GENMASK(1, 0)
#define PCIE_GEN_SEL_SHIFT 0x0 #define ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT 0
#define SPEED_GEN_1 0 #define ADVK_GLOBAL_CTRL0_SPEED_GEN_1 0
#define SPEED_GEN_2 1 #define ADVK_GLOBAL_CTRL0_SPEED_GEN_2 1
#define SPEED_GEN_3 2 #define ADVK_GLOBAL_CTRL0_SPEED_GEN_3 2
#define IS_RC_MSK 1 #define ADVK_GLOBAL_CTRL0_IS_RC BIT(2)
#define IS_RC_SHIFT 2 #define ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK GENMASK(4, 3)
#define LANE_CNT_MSK 0x18 #define ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT 3
#define LANE_CNT_SHIFT 0x3 #define ADVK_GLOBAL_CTRL0_LANE_COUNT_1 0
#define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) #define ADVK_GLOBAL_CTRL0_LANE_COUNT_2 1
#define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) #define ADVK_GLOBAL_CTRL0_LANE_COUNT_4 2
#define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) #define ADVK_GLOBAL_CTRL0_LANE_COUNT_8 3
#define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) #define ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN BIT(6)
#define LINK_TRAINING_EN BIT(6) #define ADVK_GLOBAL_CTRL2 (ADVK_GLOBAL_CTRL_BASE_ADDR + 0x8)
#define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) #define ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN BIT(5)
#define PCIE_CORE_CTRL2_RESERVED 0x7 #define ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN BIT(6)
#define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
#define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
/* PCIe window configuration */ /* PCIe window configuration registers */
#define OB_WIN_BASE_ADDR 0x4c00 #define ADVK_OB_WIN_BASE_ADDR 0x4c00
#define OB_WIN_BLOCK_SIZE 0x20 #define ADVK_OB_WIN_BLOCK_SIZE 0x20
#define OB_WIN_COUNT 8 #define ADVK_OB_WIN_COUNT 8
#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \ #define ADVK_OB_WIN_REG_ADDR(win, offset) (ADVK_OB_WIN_BASE_ADDR + ADVK_OB_WIN_BLOCK_SIZE * (win) + (offset))
OB_WIN_BLOCK_SIZE * (win) + \ #define ADVK_OB_WIN_MATCH_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x00)
(offset)) #define ADVK_OB_WIN_ENABLE BIT(0)
#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00) #define ADVK_OB_WIN_MATCH_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x04)
#define OB_WIN_ENABLE BIT(0) #define ADVK_OB_WIN_REMAP_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x08)
#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04) #define ADVK_OB_WIN_REMAP_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x0c)
#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08) #define ADVK_OB_WIN_MASK_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x10)
#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c) #define ADVK_OB_WIN_MASK_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x14)
#define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10) #define ADVK_OB_WIN_ACTIONS(win) ADVK_OB_WIN_REG_ADDR(win, 0x18)
#define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14) #define ADVK_OB_WIN_DEFAULT_ACTIONS (ADVK_OB_WIN_ACTIONS(ADVK_OB_WIN_COUNT-1) + 0x4)
#define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18) #define ADVK_OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
#define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4) #define ADVK_OB_WIN_FUNC_NUM_SHIFT 24
#define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24) #define ADVK_OB_WIN_FUNC_NUM_ENABLE BIT(23)
#define OB_WIN_FUNC_NUM_SHIFT 24 #define ADVK_OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
#define OB_WIN_FUNC_NUM_ENABLE BIT(23) #define ADVK_OB_WIN_BUS_NUM_BITS_SHIFT 20
#define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20) #define ADVK_OB_WIN_MSG_CODE_ENABLE BIT(22)
#define OB_WIN_BUS_NUM_BITS_SHIFT 20 #define ADVK_OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
#define OB_WIN_MSG_CODE_ENABLE BIT(22) #define ADVK_OB_WIN_MSG_CODE_SHIFT 14
#define OB_WIN_MSG_CODE_MASK GENMASK(21, 14) #define ADVK_OB_WIN_MSG_PAYLOAD_LEN BIT(12)
#define OB_WIN_MSG_CODE_SHIFT 14 #define ADVK_OB_WIN_ATTR_ENABLE BIT(11)
#define OB_WIN_MSG_PAYLOAD_LEN BIT(12) #define ADVK_OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
#define OB_WIN_ATTR_ENABLE BIT(11) #define ADVK_OB_WIN_ATTR_TC_SHIFT 8
#define OB_WIN_ATTR_TC_MASK GENMASK(10, 8) #define ADVK_OB_WIN_ATTR_RELAXED BIT(7)
#define OB_WIN_ATTR_TC_SHIFT 8 #define ADVK_OB_WIN_ATTR_NOSNOOP BIT(6)
#define OB_WIN_ATTR_RELAXED BIT(7) #define ADVK_OB_WIN_ATTR_POISON BIT(5)
#define OB_WIN_ATTR_NOSNOOP BIT(6) #define ADVK_OB_WIN_ATTR_IDO BIT(4)
#define OB_WIN_ATTR_POISON BIT(5) #define ADVK_OB_WIN_TYPE_MASK GENMASK(3, 0)
#define OB_WIN_ATTR_IDO BIT(4) #define ADVK_OB_WIN_TYPE_SHIFT 0
#define OB_WIN_TYPE_MASK GENMASK(3, 0) #define ADVK_OB_WIN_TYPE_MEM 0x0
#define OB_WIN_TYPE_SHIFT 0 #define ADVK_OB_WIN_TYPE_IO 0x4
#define OB_WIN_TYPE_MEM 0x0 #define ADVK_OB_WIN_TYPE_CONFIG_TYPE0 0x8
#define OB_WIN_TYPE_IO 0x4 #define ADVK_OB_WIN_TYPE_CONFIG_TYPE1 0x9
#define OB_WIN_TYPE_CONFIG_TYPE0 0x8 #define ADVK_OB_WIN_TYPE_MSG 0xc
#define OB_WIN_TYPE_CONFIG_TYPE1 0x9
#define OB_WIN_TYPE_MSG 0xc
/* LMI registers base address and register offsets */ /* Local Management Interface registers */
#define LMI_BASE_ADDR 0x6000 #define ADVK_LMI_BASE_ADDR 0x6000
#define CFG_REG (LMI_BASE_ADDR + 0x0) #define ADVK_LMI_PHY_CFG0 (ADVK_LMI_BASE_ADDR + 0x0)
#define LTSSM_SHIFT 24 #define ADVK_LMI_PHY_CFG0_LTSSM_MASK GENMASK(29, 24)
#define LTSSM_MASK 0x3f #define ADVK_LMI_PHY_CFG0_LTSSM_SHIFT 24
#define LTSSM_L0 0x10 #define ADVK_LMI_PHY_CFG0_LTSSM_L0 0x10
#define LTSSM_DISABLED 0x20 #define ADVK_LMI_PHY_CFG0_LTSSM_DISABLED 0x20
#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) #define ADVK_LMI_VENDOR_ID (ADVK_LMI_BASE_ADDR + 0x44)
/* PCIe core controller registers */ /* Core Control registers */
#define CTRL_CORE_BASE_ADDR 0x18000 #define ADVK_CORE_CTRL_BASE_ADDR 0x18000
#define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) #define ADVK_CORE_CTRL_CONFIG (ADVK_CORE_CTRL_BASE_ADDR + 0x0)
#define CTRL_MODE_SHIFT 0x0 #define ADVK_CORE_CTRL_CONFIG_COMMAND_MODE BIT(0)
#define CTRL_MODE_MASK 0x1
#define PCIE_CORE_MODE_DIRECT 0x0
#define PCIE_CORE_MODE_COMMAND 0x1
/* Transaction types */
#define PCIE_CONFIG_RD_TYPE0 0x8
#define PCIE_CONFIG_RD_TYPE1 0x9
#define PCIE_CONFIG_WR_TYPE0 0xa
#define PCIE_CONFIG_WR_TYPE1 0xb
/* PCIe Retries & Timeout definitions */ /* PCIe Retries & Timeout definitions */
#define PIO_MAX_RETRIES 1500 #define PIO_MAX_RETRIES 1500
@@ -154,7 +145,7 @@
#define LINK_MAX_RETRIES 10 #define LINK_MAX_RETRIES 10
#define LINK_WAIT_TIMEOUT 100000 #define LINK_WAIT_TIMEOUT 100000
#define CFG_RD_CRS_VAL 0xFFFF0001 #define CFG_RD_CRS_VAL 0xFFFF0001
/** /**
* struct pcie_advk - Advk PCIe controller state * struct pcie_advk - Advk PCIe controller state
@@ -234,8 +225,8 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
uint count; uint count;
for (count = 1; count <= PIO_MAX_RETRIES; count++) { for (count = 1; count <= PIO_MAX_RETRIES; count++) {
start = advk_readl(pcie, PIO_START); start = advk_readl(pcie, ADVK_PIO_START);
isr = advk_readl(pcie, PIO_ISR); isr = advk_readl(pcie, ADVK_PIO_ISR);
if (!start && isr) if (!start && isr)
return count; return count;
/* /*
@@ -267,29 +258,29 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
unsigned int status; unsigned int status;
char *strcomp_status, *str_posted; char *strcomp_status, *str_posted;
reg = advk_readl(pcie, PIO_STAT); reg = advk_readl(pcie, ADVK_PIO_STAT);
status = (reg & PIO_COMPLETION_STATUS_MASK) >> status = (reg & ADVK_PIO_COMPLETION_STATUS_MASK) >>
PIO_COMPLETION_STATUS_SHIFT; ADVK_PIO_COMPLETION_STATUS_SHIFT;
switch (status) { switch (status) {
case PIO_COMPLETION_STATUS_OK: case ADVK_PIO_COMPLETION_STATUS_OK:
if (reg & PIO_ERR_STATUS) { if (reg & ADVK_PIO_ERR_STATUS) {
strcomp_status = "COMP_ERR"; strcomp_status = "COMP_ERR";
ret = -EFAULT; ret = -EFAULT;
break; break;
} }
/* Get the read result */ /* Get the read result */
if (read_val) if (read_val)
*read_val = advk_readl(pcie, PIO_RD_DATA); *read_val = advk_readl(pcie, ADVK_PIO_RD_DATA);
/* No error */ /* No error */
strcomp_status = NULL; strcomp_status = NULL;
ret = 0; ret = 0;
break; break;
case PIO_COMPLETION_STATUS_UR: case ADVK_PIO_COMPLETION_STATUS_UR:
strcomp_status = "UR"; strcomp_status = "UR";
ret = -EOPNOTSUPP; ret = -EOPNOTSUPP;
break; break;
case PIO_COMPLETION_STATUS_CRS: case ADVK_PIO_COMPLETION_STATUS_CRS:
if (allow_crs && read_val) { if (allow_crs && read_val) {
/* For reading, CRS is not an error status. */ /* For reading, CRS is not an error status. */
*read_val = CFG_RD_CRS_VAL; *read_val = CFG_RD_CRS_VAL;
@@ -300,7 +291,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
ret = -EAGAIN; ret = -EAGAIN;
} }
break; break;
case PIO_COMPLETION_STATUS_CA: case ADVK_PIO_COMPLETION_STATUS_CA:
strcomp_status = "CA"; strcomp_status = "CA";
ret = -ECANCELED; ret = -ECANCELED;
break; break;
@@ -313,14 +304,14 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
if (!strcomp_status) if (!strcomp_status)
return ret; return ret;
if (reg & PIO_NON_POSTED_REQ) if (reg & ADVK_PIO_NON_POSTED_REQ)
str_posted = "Non-posted"; str_posted = "Non-posted";
else else
str_posted = "Posted"; str_posted = "Posted";
dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n", dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
str_posted, strcomp_status, reg, str_posted, strcomp_status, reg,
advk_readl(pcie, PIO_ADDR_LS)); advk_readl(pcie, ADVK_PIO_ADDR_LS));
return ret; return ret;
} }
@@ -418,7 +409,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
*/ */
allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve; allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve;
if (advk_readl(pcie, PIO_START)) { if (advk_readl(pcie, ADVK_PIO_START)) {
dev_err(pcie->dev, dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n"); "Previous PIO read/write transfer is still running\n");
if (allow_crs) { if (allow_crs) {
@@ -430,28 +421,28 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
} }
/* Program the control register */ /* Program the control register */
reg = advk_readl(pcie, PIO_CTRL); reg = advk_readl(pcie, ADVK_PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK; reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
if (busno == pcie->sec_busno) if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_RD_TYPE0; reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
else else
reg |= PCIE_CONFIG_RD_TYPE1; reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
advk_writel(pcie, reg, PIO_CTRL); advk_writel(pcie, reg, ADVK_PIO_CTRL);
/* Program the address registers */ /* Program the address registers */
reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3)); reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS); advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
/* Program the data strobe */ /* Program the data strobe */
advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); advk_writel(pcie, 0xf, ADVK_PIO_WR_DATA_STRB);
retry_count = 0; retry_count = 0;
retry: retry:
/* Start the transfer */ /* Start the transfer */
advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, ADVK_PIO_ISR);
advk_writel(pcie, 1, PIO_START); advk_writel(pcie, 1, ADVK_PIO_START);
ret = pcie_advk_wait_pio(pcie); ret = pcie_advk_wait_pio(pcie);
if (ret < 0) { if (ret < 0) {
@@ -582,43 +573,43 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
return 0; return 0;
} }
if (advk_readl(pcie, PIO_START)) { if (advk_readl(pcie, ADVK_PIO_START)) {
dev_err(pcie->dev, dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n"); "Previous PIO read/write transfer is still running\n");
return -EAGAIN; return -EAGAIN;
} }
/* Program the control register */ /* Program the control register */
reg = advk_readl(pcie, PIO_CTRL); reg = advk_readl(pcie, ADVK_PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK; reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
if (busno == pcie->sec_busno) if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_WR_TYPE0; reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
else else
reg |= PCIE_CONFIG_WR_TYPE1; reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
advk_writel(pcie, reg, PIO_CTRL); advk_writel(pcie, reg, ADVK_PIO_CTRL);
/* Program the address registers */ /* Program the address registers */
reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3)); reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS); advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg); dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
/* Program the data register */ /* Program the data register */
reg = pci_conv_size_to_32(0, value, offset, size); reg = pci_conv_size_to_32(0, value, offset, size);
advk_writel(pcie, reg, PIO_WR_DATA); advk_writel(pcie, reg, ADVK_PIO_WR_DATA);
dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg); dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
/* Program the data strobe */ /* Program the data strobe */
reg = pcie_calc_datastrobe(offset, size); reg = pcie_calc_datastrobe(offset, size);
advk_writel(pcie, reg, PIO_WR_DATA_STRB); advk_writel(pcie, reg, ADVK_PIO_WR_DATA_STRB);
dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg); dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
retry_count = 0; retry_count = 0;
retry: retry:
/* Start the transfer */ /* Start the transfer */
advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, ADVK_PIO_ISR);
advk_writel(pcie, 1, PIO_START); advk_writel(pcie, 1, ADVK_PIO_START);
ret = pcie_advk_wait_pio(pcie); ret = pcie_advk_wait_pio(pcie);
if (ret < 0) if (ret < 0)
@@ -645,9 +636,9 @@ static int pcie_advk_link_up(struct pcie_advk *pcie)
{ {
u32 val, ltssm_state; u32 val, ltssm_state;
val = advk_readl(pcie, CFG_REG); val = advk_readl(pcie, ADVK_LMI_PHY_CFG0);
ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; ltssm_state = (val & ADVK_LMI_PHY_CFG0_LTSSM_MASK) >> ADVK_LMI_PHY_CFG0_LTSSM_SHIFT;
return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; return ltssm_state >= ADVK_LMI_PHY_CFG0_LTSSM_L0 && ltssm_state < ADVK_LMI_PHY_CFG0_LTSSM_DISABLED;
} }
/** /**
@@ -687,25 +678,25 @@ static void pcie_advk_set_ob_win(struct pcie_advk *pcie, u8 win_num,
phys_addr_t match, phys_addr_t remap, phys_addr_t match, phys_addr_t remap,
phys_addr_t mask, u32 actions) phys_addr_t mask, u32 actions)
{ {
advk_writel(pcie, OB_WIN_ENABLE | advk_writel(pcie, ADVK_OB_WIN_ENABLE |
lower_32_bits(match), OB_WIN_MATCH_LS(win_num)); lower_32_bits(match), ADVK_OB_WIN_MATCH_LS(win_num));
advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); advk_writel(pcie, upper_32_bits(match), ADVK_OB_WIN_MATCH_MS(win_num));
advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); advk_writel(pcie, lower_32_bits(remap), ADVK_OB_WIN_REMAP_LS(win_num));
advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); advk_writel(pcie, upper_32_bits(remap), ADVK_OB_WIN_REMAP_MS(win_num));
advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); advk_writel(pcie, lower_32_bits(mask), ADVK_OB_WIN_MASK_LS(win_num));
advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); advk_writel(pcie, upper_32_bits(mask), ADVK_OB_WIN_MASK_MS(win_num));
advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); advk_writel(pcie, actions, ADVK_OB_WIN_ACTIONS(win_num));
} }
static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num) static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
{ {
advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_LS(win_num));
advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_MS(win_num));
advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_LS(win_num));
advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_MS(win_num));
advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); advk_writel(pcie, 0, ADVK_OB_WIN_MASK_LS(win_num));
advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); advk_writel(pcie, 0, ADVK_OB_WIN_MASK_MS(win_num));
advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); advk_writel(pcie, 0, ADVK_OB_WIN_ACTIONS(win_num));
} }
static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins, static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
@@ -729,7 +720,7 @@ static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
* because lower 16 bits of mask must be zero. Remapped address * because lower 16 bits of mask must be zero. Remapped address
* may have set only bits from the mask. * may have set only bits from the mask.
*/ */
while (*wins < OB_WIN_COUNT && size > 0) { while (*wins < ADVK_OB_WIN_COUNT && size > 0) {
/* Calculate the largest aligned window size */ /* Calculate the largest aligned window size */
win_size = (1ULL << (fls64(size) - 1)) | win_size = (1ULL << (fls64(size) - 1)) |
(phys_start ? (1ULL << __ffs64(phys_start)) : 0); (phys_start ? (1ULL << __ffs64(phys_start)) : 0);
@@ -774,24 +765,23 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
u32 reg; u32 reg;
/* Set to Direct mode */ /* Set to Direct mode */
reg = advk_readl(pcie, CTRL_CONFIG_REG); reg = advk_readl(pcie, ADVK_CORE_CTRL_CONFIG);
reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); reg &= ~ADVK_CORE_CTRL_CONFIG_COMMAND_MODE;
reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); advk_writel(pcie, reg, ADVK_CORE_CTRL_CONFIG);
advk_writel(pcie, reg, CTRL_CONFIG_REG);
/* Set PCI global control register to RC mode */ /* Set PCI global control register to RC mode */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg |= (IS_RC_MSK << IS_RC_SHIFT); reg |= ADVK_GLOBAL_CTRL0_IS_RC;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/* /*
* Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
* VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor * ADVK_LMI_VENDOR_ID contains vendor id in low 16 bits and subsystem vendor
* id in high 16 bits. Updating this register changes readback value of * id in high 16 bits. Updating this register changes readback value of
* read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround * read-only vendor id bits in Root Port PCI_VENDOR_ID register. Workaround
* for erratum 4.1: "The value of device and vendor ID is incorrect". * for erratum 4.1: "The value of device and vendor ID is incorrect".
*/ */
advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG); advk_writel(pcie, 0x11ab11ab, ADVK_LMI_VENDOR_ID);
/* /*
* Change Class Code of PCI Bridge device to PCI Bridge (0x600400), * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
@@ -836,26 +826,26 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL); advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL);
/* Program PCIe Control 2 to disable strict ordering */ /* Program PCIe Control 2 to disable strict ordering */
reg = PCIE_CORE_CTRL2_RESERVED | reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
PCIE_CORE_CTRL2_TD_ENABLE; reg &= ~ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
/* Set GEN2 */ /* Set GEN2 */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg &= ~PCIE_GEN_SEL_MSK; reg &= ~ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK;
reg |= SPEED_GEN_2; reg |= ADVK_GLOBAL_CTRL0_SPEED_GEN_2 << ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/* Set lane X1 */ /* Set lane X1 */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg &= ~LANE_CNT_MSK; reg &= ~ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK;
reg |= LANE_COUNT_1; reg |= ADVK_GLOBAL_CTRL0_LANE_COUNT_1 << ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/* Enable link training */ /* Enable link training */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg |= LINK_TRAINING_EN; reg |= ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
/* /*
* Enable AXI address window location generation: * Enable AXI address window location generation:
@@ -867,9 +857,9 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
* access when default outbound window configuration * access when default outbound window configuration
* is set for memory access. * is set for memory access.
*/ */
reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE; reg |= ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
/* /*
* Bypass the address window mapping for PIO: * Bypass the address window mapping for PIO:
@@ -877,16 +867,16 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
* info over AXI interface by PIO registers, the * info over AXI interface by PIO registers, the
* address window is not required. * address window is not required.
*/ */
reg = advk_readl(pcie, PIO_CTRL); reg = advk_readl(pcie, ADVK_PIO_CTRL);
reg |= PIO_CTRL_ADDR_WIN_DISABLE; reg |= ADVK_PIO_CTRL_ADDR_WIN_DISABLE;
advk_writel(pcie, reg, PIO_CTRL); advk_writel(pcie, reg, ADVK_PIO_CTRL);
/* /*
* Set memory access in Default User Field so it * Set memory access in Default User Field so it
* is not required to configure PCIe address for * is not required to configure PCIe address for
* transparent memory access. * transparent memory access.
*/ */
advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); advk_writel(pcie, ADVK_OB_WIN_TYPE_MEM, ADVK_OB_WIN_DEFAULT_ACTIONS);
/* /*
* Configure PCIe address windows for non-memory or * Configure PCIe address windows for non-memory or
@@ -896,14 +886,14 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
wins = 0; wins = 0;
pci_get_regions(pcie->dev, &io, &mem, &pref); pci_get_regions(pcie->dev, &io, &mem, &pref);
if (io) if (io)
pcie_advk_set_ob_region(pcie, &wins, io, OB_WIN_TYPE_IO); pcie_advk_set_ob_region(pcie, &wins, io, ADVK_OB_WIN_TYPE_IO);
if (mem && mem->phys_start != mem->bus_start) if (mem && mem->phys_start != mem->bus_start)
pcie_advk_set_ob_region(pcie, &wins, mem, OB_WIN_TYPE_MEM); pcie_advk_set_ob_region(pcie, &wins, mem, ADVK_OB_WIN_TYPE_MEM);
if (pref && pref->phys_start != pref->bus_start) if (pref && pref->phys_start != pref->bus_start)
pcie_advk_set_ob_region(pcie, &wins, pref, OB_WIN_TYPE_MEM); pcie_advk_set_ob_region(pcie, &wins, pref, ADVK_OB_WIN_TYPE_MEM);
/* Disable remaining PCIe outbound windows */ /* Disable remaining PCIe outbound windows */
for (i = ((wins >= 0) ? wins : 0); i < OB_WIN_COUNT; i++) for (i = ((wins >= 0) ? wins : 0); i < ADVK_OB_WIN_COUNT; i++)
pcie_advk_disable_ob_win(pcie, i); pcie_advk_disable_ob_win(pcie, i);
if (wins == -1) if (wins == -1)
@@ -971,16 +961,16 @@ static int pcie_advk_remove(struct udevice *dev)
u32 reg; u32 reg;
int i; int i;
for (i = 0; i < OB_WIN_COUNT; i++) for (i = 0; i < ADVK_OB_WIN_COUNT; i++)
pcie_advk_disable_ob_win(pcie, i); pcie_advk_disable_ob_win(pcie, i);
reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND); reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND); advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
reg &= ~LINK_TRAINING_EN; reg &= ~ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
return 0; return 0;
} }