mpc85xx: Adding more registers and options
This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@@ -120,6 +120,11 @@ typedef struct fsl_ddr_cfg_regs_s {
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unsigned int ddr_sdram_rcw_1;
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unsigned int ddr_sdram_rcw_2;
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unsigned int ddr_eor;
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unsigned int ddr_cdr1;
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unsigned int ddr_cdr2;
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unsigned int err_disable;
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unsigned int err_int_en;
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unsigned int debug[32];
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} fsl_ddr_cfg_regs_t;
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typedef struct memctl_options_partial_s {
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@@ -175,6 +180,7 @@ typedef struct memctl_options_s {
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/* mirrior DIMMs for DDR3 */
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unsigned int mirrored_dimm;
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unsigned int quad_rank_present;
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unsigned int ap_en; /* address parity enable for RDIMM */
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/* Global Timing Parameters */
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unsigned int cas_latency_override;
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@@ -210,6 +216,12 @@ typedef struct memctl_options_s {
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unsigned int zq_en;
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/* Write leveling */
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unsigned int wrlvl_en;
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/* RCW override for RDIMM */
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unsigned int rcw_override;
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unsigned int rcw_1;
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unsigned int rcw_2;
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/* control register 1 */
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unsigned int ddr_cdr1;
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} memctl_options_t;
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extern phys_size_t fsl_ddr_sdram(void);
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