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riscv: Add kconfig option to run U-Boot in S-mode

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This patch adds kconfig option RISCV_SMODE to run U-Boot in
S-mode. When this opition is enabled we use s<xyz> CSRs instead
of m<xyz> CSRs.

It is important to note that there is no equivalent S-mode CSR
for misa and mhartid CSRs so we expect M-mode runtime firmware
(BBL or equivalent) to emulate misa and mhartid CSR read.

In-future, we will have more patches to avoid accessing misa and
mhartid CSRs from S-mode.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
This commit is contained in:
Anup Patel
2018-12-03 10:57:40 +05:30
committed by Andes
parent 2e2a2a5d4f
commit d2db2a8fa4
4 changed files with 48 additions and 17 deletions
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31
arch/riscv/lib/interrupts.c
View File

@@ -34,17 +34,30 @@ int disable_interrupts(void)
return 0;
}
ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs)
ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
{
ulong is_int;
ulong is_irq, irq;
is_int = (mcause & MCAUSE_INT);
if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
external_interrupt(0); /* handle_m_ext_interrupt */
else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))
timer_interrupt(0); /* handle_m_timer_interrupt */
else
_exit_trap(mcause, epc, regs);
is_irq = (cause & MCAUSE_INT);
irq = (cause & ~MCAUSE_INT);
if (is_irq) {
switch (irq) {
case IRQ_M_EXT:
case IRQ_S_EXT:
external_interrupt(0); /* handle external interrupt */
break;
case IRQ_M_TIMER:
case IRQ_S_TIMER:
timer_interrupt(0); /* handle timer interrupt */
break;
default:
_exit_trap(cause, epc, regs);
break;
};
} else {
_exit_trap(cause, epc, regs);
}
return epc;
}