Convert CONFIG_USB_EHCI_TXFIFO_THRESH to Kconfig
This converts the following to Kconfig: CONFIG_USB_EHCI_TXFIFO_THRESH Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
3
README
3
README
@@ -793,9 +793,6 @@ The following options need to be configured:
|
|||||||
Supported are USB Keyboards and USB Floppy drives
|
Supported are USB Keyboards and USB Floppy drives
|
||||||
(TEAC FD-05PUB).
|
(TEAC FD-05PUB).
|
||||||
|
|
||||||
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
|
|
||||||
txfilltuning field in the EHCI controller on reset.
|
|
||||||
|
|
||||||
CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
|
CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
|
||||||
HW module registers.
|
HW module registers.
|
||||||
|
|
||||||
|
@@ -268,6 +268,17 @@ config USB_EHCI_FSL
|
|||||||
select EHCI_HCD_INIT_AFTER_RESET
|
select EHCI_HCD_INIT_AFTER_RESET
|
||||||
---help---
|
---help---
|
||||||
Enables support for the on-chip EHCI controller on FSL chips.
|
Enables support for the on-chip EHCI controller on FSL chips.
|
||||||
|
|
||||||
|
config USB_EHCI_TXFIFO_THRESH
|
||||||
|
hex
|
||||||
|
depends on USB_EHCI_TEGRA
|
||||||
|
default 0x10
|
||||||
|
help
|
||||||
|
This parameter affects a TXFILLTUNING field that controls how much
|
||||||
|
data is sent to the latency fifo before it is sent to the wire.
|
||||||
|
Without this parameter, the default (2) causes occasional Data Buffer
|
||||||
|
Errors in OUT packets depending on the buffer address and size.
|
||||||
|
|
||||||
endif # USB_EHCI_HCD
|
endif # USB_EHCI_HCD
|
||||||
|
|
||||||
config USB_OHCI_HCD
|
config USB_OHCI_HCD
|
||||||
|
@@ -55,7 +55,4 @@
|
|||||||
|
|
||||||
/* Defines for SPL */
|
/* Defines for SPL */
|
||||||
|
|
||||||
/* For USB EHCI controller */
|
|
||||||
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
|
|
||||||
|
|
||||||
#endif /* _TEGRA114_COMMON_H_ */
|
#endif /* _TEGRA114_COMMON_H_ */
|
||||||
|
@@ -57,9 +57,6 @@
|
|||||||
|
|
||||||
/* Defines for SPL */
|
/* Defines for SPL */
|
||||||
|
|
||||||
/* For USB EHCI controller */
|
|
||||||
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
|
|
||||||
|
|
||||||
/* GPU needs setup */
|
/* GPU needs setup */
|
||||||
#define CONFIG_TEGRA_GPU
|
#define CONFIG_TEGRA_GPU
|
||||||
|
|
||||||
|
@@ -69,12 +69,4 @@
|
|||||||
#define TEGRA_LP0_VEC
|
#define TEGRA_LP0_VEC
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*
|
|
||||||
* This parameter affects a TXFILLTUNING field that controls how much data is
|
|
||||||
* sent to the latency fifo before it is sent to the wire. Without this
|
|
||||||
* parameter, the default (2) causes occasional Data Buffer Errors in OUT
|
|
||||||
* packets depending on the buffer address and size.
|
|
||||||
*/
|
|
||||||
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
|
|
||||||
|
|
||||||
#endif /* _TEGRA20_COMMON_H_ */
|
#endif /* _TEGRA20_COMMON_H_ */
|
||||||
|
@@ -46,9 +46,6 @@
|
|||||||
"fdt_addr_r=0x83000000\0" \
|
"fdt_addr_r=0x83000000\0" \
|
||||||
"ramdisk_addr_r=0x83420000\0"
|
"ramdisk_addr_r=0x83420000\0"
|
||||||
|
|
||||||
/* For USB EHCI controller */
|
|
||||||
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
|
|
||||||
|
|
||||||
/* GPU needs setup */
|
/* GPU needs setup */
|
||||||
#define CONFIG_TEGRA_GPU
|
#define CONFIG_TEGRA_GPU
|
||||||
|
|
||||||
|
@@ -52,7 +52,4 @@
|
|||||||
|
|
||||||
/* Defines for SPL */
|
/* Defines for SPL */
|
||||||
|
|
||||||
/* For USB EHCI controller */
|
|
||||||
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
|
|
||||||
|
|
||||||
#endif /* _TEGRA30_COMMON_H_ */
|
#endif /* _TEGRA30_COMMON_H_ */
|
||||||
|
Reference in New Issue
Block a user