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Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD
2014-02-13 13:30:54 +01:00
parent 7bc5c8c930 e25bfecf7b
commit d53ccdb341
36 changed files with 11593 additions and 5446 deletions
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84
arch/arm/cpu/armv7/exynos/clock.c
View File

@@ -26,7 +26,7 @@ struct clk_bit_info {
};
/* src_bit div_bit prediv_bit */
static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
static struct clk_bit_info clk_bit_info[] = {
{0, 0, -1},
{4, 4, -1},
{8, 8, -1},
@@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val;
/*
* CLK_DIV_FSYS1
@@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
val = readl(addr);
val &= ~(0xff << ((dev_index << 4) + 8));
val |= (div & 0xff) << ((dev_index << 4) + 8);
writel(val, addr);
clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
(div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos4x12: set the mmc clock */
@@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
struct exynos4x12_clock *clk =
(struct exynos4x12_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val;
/*
* CLK_DIV_FSYS1
@@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
val = readl(addr);
val &= ~(0xff << ((dev_index << 4) + 8));
val |= (div & 0xff) << ((dev_index << 4) + 8);
writel(val, addr);
clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
(div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
@@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val;
/*
* CLK_DIV_FSYS1
@@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
val = readl(addr);
val &= ~(0xff << ((dev_index << 4) + 8));
val |= (div & 0xff) << ((dev_index << 4) + 8);
writel(val, addr);
clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
(div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
@@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val, shift;
unsigned int shift;
/*
* CLK_DIV_FSYS1
@@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
addr = (unsigned int)&clk->div_fsys1;
shift = dev_index * 10;
val = readl(addr);
val &= ~(0x3ff << shift);
val |= (div & 0x3ff) << shift;
writel(val, addr);
clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
}
/* get_lcd_clk: return lcd clock frequency */
@@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
@@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
cfg = readl(&clk->gate_block);
cfg |= 1 << 4;
writel(cfg, &clk->gate_block);
setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
cfg = readl(&clk->src_lcd0);
cfg &= ~(0xf);
cfg |= 0x6;
writel(cfg, &clk->src_lcd0);
clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
@@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
cfg = readl(&clk->gate_ip_lcd0);
cfg |= 1 << 0;
writel(cfg, &clk->gate_ip_lcd0);
setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
/*
* CLK_DIV_LCD0
@@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
cfg &= ~(0xf);
cfg |= 0x1;
writel(cfg, &clk->div_lcd0);
clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
}
void exynos5_set_lcd_clk(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
@@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
cfg = readl(&clk->gate_block);
cfg |= 1 << 4;
writel(cfg, &clk->gate_block);
setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
@@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
cfg = readl(&clk->src_disp1_0);
cfg &= ~(0xf);
cfg |= 0x6;
writel(cfg, &clk->src_disp1_0);
clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
@@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
cfg = readl(&clk->gate_ip_disp1);
cfg |= 1 << 0;
writel(cfg, &clk->gate_ip_disp1);
setbits_le32(&clk->gate_ip_disp1, 1 << 0);
/*
* CLK_DIV_LCD0
@@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
cfg &= ~(0xf);
cfg |= 0x0;
writel(cfg, &clk->div_disp1_0);
clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int cfg = 0;
/*
* CLK_SRC_LCD0
@@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_SEL [12:15]
* set mipi0 src clock 0x6: SCLK_MPLL
*/
cfg = readl(&clk->src_lcd0);
cfg &= ~(0xf << 12);
cfg |= (0x6 << 12);
writel(cfg, &clk->src_lcd0);
clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
/*
* CLK_SRC_MASK_LCD0
@@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_MASK [12]
* set src mask mipi0 0x1: Unmask
*/
cfg = readl(&clk->src_mask_lcd0);
cfg |= (0x1 << 12);
writel(cfg, &clk->src_mask_lcd0);
setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
/*
* CLK_GATE_IP_LCD0
@@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for MIPI0
*/
cfg = readl(&clk->gate_ip_lcd0);
cfg |= 1 << 3;
writel(cfg, &clk->gate_ip_lcd0);
setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
/*
* CLK_DIV_LCD0
@@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set mipi ratio
*/
cfg &= ~(0xf << 16);
cfg |= (0x1 << 16);
writel(cfg, &clk->div_lcd0);
clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
}
/*

7
arch/arm/cpu/armv7/exynos/pinmux.c
View File

@@ -751,12 +751,7 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
if (err)
return PERIPH_ID_NONE;
/* check for invalid peripheral id */
if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
return cell[1];
debug(" invalid peripheral id\n");
return PERIPH_ID_NONE;
return cell[1];
}
int pinmux_decode_periph_id(const void *blob, int node)

8
arch/arm/include/asm/arch-exynos/cpu.h
View File

@@ -185,9 +185,11 @@ static inline int s5p_get_cpu_rev(void)
static inline void s5p_set_cpu_id(void)
{
unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
unsigned int pro_id = readl(EXYNOS4_PRO_ID);
unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
unsigned int cpu_rev = pro_id & 0x000000FF;
switch (pro_id) {
switch (cpu_id) {
case 0x200:
/* Exynos4210 EVT0 */
s5p_cpu_id = 0x4210;
@@ -196,10 +198,12 @@ static inline void s5p_set_cpu_id(void)
case 0x210:
/* Exynos4210 EVT1 */
s5p_cpu_id = 0x4210;
s5p_cpu_rev = cpu_rev;
break;
case 0x412:
/* Exynos4412 */
s5p_cpu_id = 0x4412;
s5p_cpu_rev = cpu_rev;
break;
case 0x520:
/* Exynos5250 */

221
arch/arm/include/asm/arch-exynos/gpio.h
View File

@@ -247,180 +247,81 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
#define S5P_GPIO_PART_SHIFT (24)
#define S5P_GPIO_PART_MASK (0xff)
#define S5P_GPIO_BANK_SHIFT (8)
#define S5P_GPIO_BANK_MASK (0xffff)
#define S5P_GPIO_PIN_MASK (0xff)
#define exynos4_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
EXYNOS4_GPIO_PART1_BASE)->bank)) \
- EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#define S5P_GPIO_SET_PART(x) \
(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define S5P_GPIO_GET_PART(x) \
(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
#define exynos4_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
EXYNOS4_GPIO_PART2_BASE)->bank)) \
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
#define S5P_GPIO_SET_PIN(x) \
((x) & S5P_GPIO_PIN_MASK)
#define exynos4x12_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
- EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#define EXYNOS4_GPIO_SET_BANK(part, bank) \
((((unsigned)&(((struct exynos4_gpio_part##part *) \
EXYNOS4_GPIO_PART##part##_BASE)->bank) \
- EXYNOS4_GPIO_PART##part##_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \
((((unsigned)&(((struct exynos4x12_gpio_part##part *) \
EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \
- EXYNOS4X12_GPIO_PART##part##_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
#define exynos4x12_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
- EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
#define EXYNOS5_GPIO_SET_BANK(part, bank) \
((((unsigned)&(((struct exynos5420_gpio_part##part *) \
EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
- EXYNOS5_GPIO_PART##part##_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define EXYNOS5420_GPIO_SET_BANK(part, bank) \
((((unsigned)&(((struct exynos5420_gpio_part##part *) \
EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
- EXYNOS5420_GPIO_PART##part##_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
#define exynos4x12_gpio_part3_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
- EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
#define exynos4_gpio_get(part, bank, pin) \
(S5P_GPIO_SET_PART(part) | \
EXYNOS4_GPIO_SET_BANK(part, bank) | \
S5P_GPIO_SET_PIN(pin))
#define exynos5_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
EXYNOS5_GPIO_PART1_BASE)->bank)) \
- EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#define exynos4x12_gpio_get(part, bank, pin) \
(S5P_GPIO_SET_PART(part) | \
EXYNOS4X12_GPIO_SET_BANK(part, bank) | \
S5P_GPIO_SET_PIN(pin))
#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define exynos5420_gpio_get(part, bank, pin) \
(S5P_GPIO_SET_PART(part) | \
EXYNOS5420_GPIO_SET_BANK(part, bank) | \
S5P_GPIO_SET_PIN(pin))
#define exynos5_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
EXYNOS5_GPIO_PART2_BASE)->bank)) \
- EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
#define exynos5_gpio_get(part, bank, pin) \
(S5P_GPIO_SET_PART(part) | \
EXYNOS5_GPIO_SET_BANK(part, bank) | \
S5P_GPIO_SET_PIN(pin))
#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define exynos5_gpio_part3_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
EXYNOS5_GPIO_PART3_BASE)->bank)) \
- EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
/* EXYNOS5420 */
#define exynos5420_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
EXYNOS5420_GPIO_PART1_BASE)->bank)) \
- EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define exynos5420_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
EXYNOS5420_GPIO_PART2_BASE)->bank)) \
- EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define exynos5420_gpio_part3_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
EXYNOS5420_GPIO_PART3_BASE)->bank)) \
- EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define exynos5420_gpio_part4_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
EXYNOS5420_GPIO_PART4_BASE)->bank)) \
- EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
static inline unsigned int s5p_gpio_base(int nr)
static inline unsigned int s5p_gpio_base(int gpio)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420()) {
if (nr < EXYNOS5420_GPIO_PART1_MAX)
return EXYNOS5420_GPIO_PART1_BASE;
else if (nr < EXYNOS5420_GPIO_PART2_MAX)
return EXYNOS5420_GPIO_PART2_BASE;
else if (nr < EXYNOS5420_GPIO_PART3_MAX)
return EXYNOS5420_GPIO_PART3_BASE;
else
return EXYNOS5420_GPIO_PART4_BASE;
} else {
if (nr < EXYNOS5_GPIO_PART1_MAX)
return EXYNOS5_GPIO_PART1_BASE;
else if (nr < EXYNOS5_GPIO_PART2_MAX)
return EXYNOS5_GPIO_PART2_BASE;
else
return EXYNOS5_GPIO_PART3_BASE;
}
} else if (cpu_is_exynos4()) {
if (nr < EXYNOS4_GPIO_PART1_MAX)
return EXYNOS4_GPIO_PART1_BASE;
else
return EXYNOS4_GPIO_PART2_BASE;
unsigned gpio_part = S5P_GPIO_GET_PART(gpio);
switch (gpio_part) {
case 1:
return samsung_get_base_gpio_part1();
case 2:
return samsung_get_base_gpio_part2();
case 3:
return samsung_get_base_gpio_part3();
case 4:
return samsung_get_base_gpio_part4();
default:
return 0;
}
return 0;
}
static inline unsigned int s5p_gpio_part_max(int nr)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420()) {
if (nr < EXYNOS5420_GPIO_PART1_MAX)
return 0;
else if (nr < EXYNOS5420_GPIO_PART2_MAX)
return EXYNOS5420_GPIO_PART1_MAX;
else if (nr < EXYNOS5420_GPIO_PART3_MAX)
return EXYNOS5420_GPIO_PART2_MAX;
else if (nr < EXYNOS5420_GPIO_PART4_MAX)
return EXYNOS5420_GPIO_PART3_MAX;
else
return EXYNOS5420_GPIO_PART4_MAX;
} else {
if (nr < EXYNOS5_GPIO_PART1_MAX)
return 0;
else if (nr < EXYNOS5_GPIO_PART2_MAX)
return EXYNOS5_GPIO_PART1_MAX;
else
return EXYNOS5_GPIO_PART2_MAX;
}
} else if (cpu_is_exynos4()) {
if (proid_is_exynos4412()) {
if (nr < EXYNOS4X12_GPIO_PART1_MAX)
return 0;
else if (nr < EXYNOS4X12_GPIO_PART2_MAX)
return EXYNOS4X12_GPIO_PART1_MAX;
else
return EXYNOS4X12_GPIO_PART2_MAX;
} else {
if (nr < EXYNOS4_GPIO_PART1_MAX)
return 0;
else
return EXYNOS4_GPIO_PART1_MAX;
}
}
return 0;
}
#endif

3
arch/arm/include/asm/arch-exynos/periph.h
View File

@@ -36,7 +36,6 @@ enum periph_id {
PERIPH_ID_SDMMC3,
PERIPH_ID_I2C8 = 87,
PERIPH_ID_I2C9,
PERIPH_ID_I2C10 = 203,
PERIPH_ID_I2S0 = 98,
PERIPH_ID_I2S1 = 99,
@@ -54,8 +53,8 @@ enum periph_id {
PERIPH_ID_PWM2,
PERIPH_ID_PWM3,
PERIPH_ID_PWM4,
PERIPH_ID_I2C10 = 203,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
};

7
arch/arm/include/asm/arch-s5pc1xx/cpu.h
View File

@@ -51,10 +51,17 @@
#include <asm/io.h>
/* CPU detection macros */
extern unsigned int s5p_cpu_id;
extern unsigned int s5p_cpu_rev;
static inline int s5p_get_cpu_rev(void)
{
return s5p_cpu_rev;
}
static inline void s5p_set_cpu_id(void)
{
s5p_cpu_id = readl(S5PC100_PRO_ID);
s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
}

47
arch/arm/include/asm/arch-s5pc1xx/gpio.h
View File

@@ -125,20 +125,45 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
#define S5P_GPIO_PART_SHIFT (24)
#define S5P_GPIO_PART_MASK (0xff)
#define S5P_GPIO_BANK_SHIFT (8)
#define S5P_GPIO_BANK_MASK (0xffff)
#define S5P_GPIO_PIN_MASK (0xff)
#define S5P_GPIO_SET_PART(x) \
(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
#define S5P_GPIO_GET_PART(x) \
(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
#define S5P_GPIO_SET_PIN(x) \
((x) & S5P_GPIO_PIN_MASK)
#define S5PC100_SET_BANK(bank) \
(((unsigned)&(((struct s5pc100_gpio *) \
S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
#define S5PC110_SET_BANK(bank) \
((((unsigned)&(((struct s5pc110_gpio *) \
S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
#define s5pc100_gpio_get(bank, pin) \
(S5P_GPIO_SET_PART(0) | \
S5PC100_SET_BANK(bank) | \
S5P_GPIO_SET_PIN(pin))
#define s5pc110_gpio_get(bank, pin) \
(S5P_GPIO_SET_PART(0) | \
S5PC110_SET_BANK(bank) | \
S5P_GPIO_SET_PIN(pin))
static inline unsigned int s5p_gpio_base(int nr)
{
return S5PC110_GPIO_BASE;
return samsung_get_base_gpio();
}
static inline unsigned int s5p_gpio_part_max(int nr)
{
return 0;
}
#define s5pc110_gpio_get_nr(bank, pin) \
((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
- S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#endif
/* Pin configurations */