From e6b1080d1eb7b87c1464f1ef4772b1c67d9cc938 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 24 May 2024 11:23:26 +0200 Subject: [PATCH 01/34] rockchip: evb-px30: Use common bss and stack addresses U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them. Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/evb-px30_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 73a3c6120e0..50ce1d7a9f3 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -2,26 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-evb" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_EVB_PX30=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -39,9 +27,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set From 742c6eb36a2fdbfbe0b95e743b23abbf41a35d91 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 24 May 2024 11:23:27 +0200 Subject: [PATCH 02/34] rockchip: firefly-px30: Use common bss and stack addresses U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them. Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/firefly-px30_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 0a14b393667..063e4211fb7 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-firefly" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_EVB_PX30=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set From 86307b1b04ce1de085fb2a9aa06932306b0633f9 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 24 May 2024 11:23:28 +0200 Subject: [PATCH 03/34] rockchip: odroid-go2: Use common bss and stack addresses U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them. Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR. Tested-by: Heiko Stuebner Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/odroid-go2_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 3c1abb83ed9..f4c9b02e12f 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -2,29 +2,17 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x4000 CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_ODROID_GO2=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -44,11 +32,11 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set From 94537d2f3322c188b847c6d7516a0a40f5459435 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 24 May 2024 11:23:29 +0200 Subject: [PATCH 04/34] rockchip: px30-core-*: Use common bss and stack addresses U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them. Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/px30-core-ctouch2-of10-px30_defconfig | 18 +++--------------- configs/px30-core-ctouch2-px30_defconfig | 18 +++--------------- configs/px30-core-edimm2.2-px30_defconfig | 18 +++--------------- 3 files changed, 9 insertions(+), 45 deletions(-) diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 87a39e115df..dd005f20ff8 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 7162c117beb..f6559fbae3a 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 1182f60358f..a099e9378c9 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set From 7fca4d8914318f6f937f745a1c6ab5bbdd85cc36 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 24 May 2024 11:23:30 +0200 Subject: [PATCH 05/34] rockchip: px30: make UART pinmux accessible to TPL/SPL DTB This adds the default pinmux for UART2 and UART5 to the TPL/SPL DTB (if not removed through the CONFIG_OF_SPL_REMOVE_PROPS symbol) as those two controllers are always made available to all boards. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/dts/px30-u-boot.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 046da022ffe..59fa9f43a97 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -33,11 +33,27 @@ bootph-all; }; +&uart2m0_xfer { + bootph-all; +}; + &uart5 { clock-frequency = <24000000>; bootph-all; }; +&uart5_cts { + bootph-all; +}; + +&uart5_rts { + bootph-all; +}; + +&uart5_xfer { + bootph-all; +}; + &sdmmc { bootph-all; From caa9456d61c4fc557ac4b5cdc751bd7a1100ead6 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 24 May 2024 11:23:31 +0200 Subject: [PATCH 06/34] rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB In order to be able to properly mux UART on PX30 EVB, the pinmux needs to be done at runtime, so let's not remove the pinctrl nodes from the SPL DTB. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/evb-px30_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 50ce1d7a9f3..a5833ad6d09 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y From c1fe76604675d5d1b0f05301ea28ff19d1d7c753 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 24 May 2024 11:23:32 +0200 Subject: [PATCH 07/34] rockchip: evb-px30: make UART5 the debug UART In the Device Tree, UART5 is the system UART, but in the defconfig it currently is UART2. Let's sync the two by making the defconfig use UART5 as well. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/evb-px30_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index a5833ad6d09..abe545625a5 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -10,7 +10,7 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_EVB_PX30=y # CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_BASE=0xff178000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y From f087f7fd277d095484d371609c3a76c45dc4764d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 24 May 2024 11:23:33 +0200 Subject: [PATCH 08/34] rockchip: px30/rk3326: migrate to OF_UPSTREAM Migrate PX30/RK3326 boards that exists in Linux v6.8 to use OF_UPSTREAM. firefly-px30 is not migrated to OF_UPSTREAM because there's no Device Tree in the Linux kernel. Differences between U-Boot's Odroid-Go2 and Linux's are now moved to the -u-boot.dtsi, though I have a gut feeling that the existing cru overrides aren't necessary (anymore?). The U-Boot GPIO led-0 is on GPIO0_C1 but such is the pin of PWM3 which is used for Linux's PWM led-2 so keep Linux's. I also doubt vcc_cam is actually used, though the Odroid-Go2 Black Edition uses this dcdc regulator for WiFi, so let's just move it to the -u-boot.dtsi to play it safe. Signed-off-by: Quentin Schulz --- arch/arm/dts/Makefile | 8 - arch/arm/dts/px30-engicam-common.dtsi | 129 ---- arch/arm/dts/px30-engicam-ctouch2.dtsi | 30 - arch/arm/dts/px30-engicam-edimm2.2.dtsi | 66 -- .../px30-engicam-px30-core-ctouch2-of10.dts | 77 --- .../dts/px30-engicam-px30-core-ctouch2.dts | 22 - .../dts/px30-engicam-px30-core-edimm2.2.dts | 43 -- arch/arm/dts/px30-engicam-px30-core.dtsi | 241 ------- arch/arm/dts/px30-evb.dts | 634 ----------------- arch/arm/dts/px30-ringneck-haikou.dts | 232 ------- arch/arm/dts/px30-ringneck.dtsi | 382 ----------- arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 15 + arch/arm/dts/rk3326-odroid-go2.dts | 642 ------------------ arch/arm/mach-rockchip/Kconfig | 1 + configs/evb-px30_defconfig | 2 +- configs/firefly-px30_defconfig | 1 + configs/odroid-go2_defconfig | 2 +- configs/px30-core-ctouch2-of10-px30_defconfig | 2 +- configs/px30-core-ctouch2-px30_defconfig | 2 +- configs/px30-core-edimm2.2-px30_defconfig | 2 +- configs/ringneck-px30_defconfig | 2 +- 21 files changed, 23 insertions(+), 2512 deletions(-) delete mode 100644 arch/arm/dts/px30-engicam-common.dtsi delete mode 100644 arch/arm/dts/px30-engicam-ctouch2.dtsi delete mode 100644 arch/arm/dts/px30-engicam-edimm2.2.dtsi delete mode 100644 arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts delete mode 100644 arch/arm/dts/px30-engicam-px30-core-ctouch2.dts delete mode 100644 arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts delete mode 100644 arch/arm/dts/px30-engicam-px30-core.dtsi delete mode 100644 arch/arm/dts/px30-evb.dts delete mode 100644 arch/arm/dts/px30-ringneck-haikou.dts delete mode 100644 arch/arm/dts/px30-ringneck.dtsi delete mode 100644 arch/arm/dts/rk3326-odroid-go2.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cef42ab53af..97eb14d3cab 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -52,14 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_PX30) += \ - px30-evb.dtb \ - px30-firefly.dtb \ - px30-engicam-px30-core-ctouch2.dtb \ - px30-engicam-px30-core-ctouch2-of10.dtb \ - px30-engicam-px30-core-edimm2.2.dtb \ - rk3326-odroid-go2.dtb - dtb-$(CONFIG_ROCKCHIP_RK3036) += \ rk3036-sdk.dtb diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi deleted file mode 100644 index 3429e124d95..00000000000 --- a/arch/arm/dts/px30-engicam-common.dtsi +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/ { - aliases { - mmc1 = &sdmmc; - mmc2 = &sdio; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; /* +5V */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&xin32k>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <80>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - }; - - vcc3v3_btreg: vcc3v3-btreg { - compatible = "regulator-gpio"; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&bt_enable_h>; - regulator-name = "btreg-gpio-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - states = <3300000 0x0>; - }; - - vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_rf_aux_mod"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&sdio { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -&gmac { - clock_in_out = "output"; - phy-supply = <&vcc_3v3>; /* +3V3_SOM */ - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; - snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&sdmmc { - cap-sd-highspeed; - card-detect-delay = <800>; - vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ - vqmmc-supply = <&vcc_3v3>; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m1_xfer>; - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi deleted file mode 100644 index bf10a3d29fc..00000000000 --- a/arch/arm/dts/px30-engicam-ctouch2.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions - * Copyright (c) 2020 Amarula Solutions(India) - */ - -#include "px30-engicam-common.dtsi" - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio_pwrseq { - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -}; - -&vcc3v3_btreg { - enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi deleted file mode 100644 index 449b8eb6454..00000000000 --- a/arch/arm/dts/px30-engicam-edimm2.2.dtsi +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -#include "px30-engicam-common.dtsi" - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - }; - - panel { - compatible = "yes-optoelectronics,ytc700tlag-05-201c"; - backlight = <&backlight>; - data-mapping = "vesa-24"; - power-supply = <&vcc3v3_lcd>; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi_dphy { - status = "okay"; -}; - -/* LVDS_B(secondary) */ -&lvds { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts deleted file mode 100644 index 47aa30505a4..00000000000 --- a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "px30.dtsi" -#include "px30-engicam-ctouch2.dtsi" -#include "px30-engicam-px30-core.dtsi" - -/ { - model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame"; - compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core", - "rockchip,px30"; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - panel { - compatible = "ampire,am-1280800n3tzqw-t00h"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd>; - data-mapping = "vesa-24"; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi_dphy { - status = "okay"; -}; - -&lvds { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts deleted file mode 100644 index 5a0ecb8faec..00000000000 --- a/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "px30.dtsi" -#include "px30-engicam-ctouch2.dtsi" -#include "px30-engicam-px30-core.dtsi" - -/ { - model = "Engicam PX30.Core C.TOUCH 2.0"; - compatible = "engicam,px30-core-ctouch2", "engicam,px30-core", - "rockchip,px30"; - - chosen { - stdout-path = "serial2:115200n8"; - }; -}; diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts deleted file mode 100644 index d759478e1c8..00000000000 --- a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "px30.dtsi" -#include "px30-engicam-edimm2.2.dtsi" -#include "px30-engicam-px30-core.dtsi" - -/ { - model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; - compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", - "rockchip,px30"; - - chosen { - stdout-path = "serial2:115200n8"; - }; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio_pwrseq { - reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; -}; - -&vcc3v3_btreg { - enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/dts/px30-engicam-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi deleted file mode 100644 index 7249871530a..00000000000 --- a/arch/arm/dts/px30-engicam-px30-core.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons - * Copyright (c) 2020 Amarula Solutons(India) - */ - -#include -#include - -/ { - compatible = "engicam,px30-core", "rockchip,px30"; - - aliases { - mmc0 = &emmc; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v3: DCDC_REG4 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v3_sys: DCDC_REG5 { - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v0: LDO_REG1 { - regulator-name = "vcc_1v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc3v0_pmu: LDO_REG4 { - regulator-name = "vcc3v0_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v3_lcd: SWITCH_REG1 { - regulator-boot-on; - regulator-name = "vcc3v3_lcd"; - }; - - vcc5v0_host: SWITCH_REG2 { - regulator-name = "vcc5v0_host"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&io_domains { - vccio1-supply = <&vcc_3v3>; - vccio2-supply = <&vcc_3v3>; - vccio3-supply = <&vcc_3v3>; - vccio4-supply = <&vcc_3v3>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - status = "okay"; -}; - -&pinctrl { - pmic { - pmic_int: pmic_int { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc_3v3>; - pmuio2-supply = <&vcc_3v3>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts deleted file mode 100644 index 848bc39cf86..00000000000 --- a/arch/arm/dts/px30-evb.dts +++ /dev/null @@ -1,634 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include -#include -#include -#include "px30.dtsi" - -/ { - model = "Rockchip PX30 EVB"; - compatible = "rockchip,px30-evb", "rockchip,px30"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdio; - mmc2 = &emmc; - }; - - chosen { - stdout-path = "serial5:115200n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - esc-key { - label = "esc"; - linux,code = ; - press-threshold-microvolt = <1310000>; - }; - - home-key { - label = "home"; - linux,code = ; - press-threshold-microvolt = <624000>; - }; - - menu-key { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <987000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <300000>; - }; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 25000 0>; - power-supply = <&vcc3v3_lcd>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ - }; - - vcc5v0_sys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&csi_dphy { - status = "okay"; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi { - status = "okay"; - - ports { - mipi_out: port@1 { - reg = <1>; - - mipi_out_panel: endpoint { - remote-endpoint = <&mipi_in_panel>; - }; - }; - }; - - panel@0 { - compatible = "xinpeng,xpp055c272"; - reg = <0>; - backlight = <&backlight>; - iovcc-supply = <&vcc_1v8>; - vci-supply = <&vcc3v3_lcd>; - - port { - mipi_in_panel: endpoint { - remote-endpoint = <&mipi_out_panel>; - }; - }; - }; -}; - -&dsi_dphy { - status = "okay"; -}; - -&emmc { - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v0>; - vqmmc-supply = <&vccio_flash>; - status = "okay"; -}; - -&gmac { - clock_in_out = "output"; - phy-supply = <&vcc_rmii>; - snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_log>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <0>; - clock-output-names = "xin32k"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v0: vcc_rmii: DCDC_REG4 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_sys: DCDC_REG5 { - regulator-name = "vcc3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v0: LDO_REG1 { - regulator-name = "vcc_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc3v0_pmu: LDO_REG4 { - regulator-name = "vcc3v0_pmu"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: LDO_REG6 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc2v8_dvp: LDO_REG7 { - regulator-name = "vcc2v8_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <2800000>; - }; - }; - - vcc1v8_dvp: LDO_REG8 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v5_dvp: LDO_REG9 { - regulator-name = "vcc1v5_dvp"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcc3v3_lcd: SWITCH_REG1 { - regulator-name = "vcc3v3_lcd"; - regulator-boot-on; - }; - - vcc5v0_host: SWITCH_REG2 { - regulator-name = "vcc5v0_host"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - sensor@d { - compatible = "asahi-kasei,ak8963"; - reg = <0x0d>; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - vdd-supply = <&vcc3v0_pmu>; - mount-matrix = "1", /* x0 */ - "0", /* y0 */ - "0", /* z0 */ - "0", /* x1 */ - "1", /* y1 */ - "0", /* z1 */ - "0", /* x2 */ - "0", /* y2 */ - "1"; /* z2 */ - }; - - touchscreen@14 { - compatible = "goodix,gt1151"; - reg = <0x14>; - interrupt-parent = <&gpio0>; - interrupts = ; - irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - VDDIO-supply = <&vcc3v3_lcd>; - }; - - sensor@4c { - compatible = "fsl,mma7660"; - reg = <0x4c>; - interrupt-parent = <&gpio0>; - interrupts = ; - }; -}; - -&i2c2 { - status = "okay"; - - clock-frequency = <100000>; - - /* These are relatively safe rise/fall times; TODO: measure */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - ov5695: ov5695@36 { - compatible = "ovti,ov5695"; - reg = <0x36>; - avdd-supply = <&vcc2v8_dvp>; - clocks = <&cru SCLK_CIF_OUT>; - clock-names = "xvclk"; - dvdd-supply = <&vcc1v5_dvp>; - dovdd-supply = <&vcc1v8_dvp>; - pinctrl-names = "default"; - pinctrl-0 = <&cif_clkout_m0>; - reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - - port { - ucam_out: endpoint { - remote-endpoint = <&mipi_in_ucam>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2s1_2ch { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_sdio>; - vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_3v0>; - vccio4-supply = <&vcc3v0_pmu>; - vccio5-supply = <&vcc_3v0>; - vccio6-supply = <&vccio_flash>; -}; - -&isp { - status = "okay"; - - ports { - port@0 { - mipi_in_ucam: endpoint@0 { - reg = <0>; - data-lanes = <1 2>; - remote-endpoint = <&ucam_out>; - }; - }; - }; -}; - -&isp_mmu { - status = "okay"; -}; - -&pinctrl { - headphone { - hp_det: hp-det { - rockchip,pins = - <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - soc_slppin_gpio: soc_slppin_gpio { - rockchip,pins = - <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; - }; - - soc_slppin_slp: soc_slppin_slp { - rockchip,pins = - <0 RK_PA4 1 &pcfg_pull_none>; - }; - - soc_slppin_rst: soc_slppin_rst { - rockchip,pins = - <0 RK_PA4 2 &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - status = "okay"; - - pmuio1-supply = <&vcc3v0_pmu>; - pmuio2-supply = <&vcc3v0_pmu>; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc { - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <800>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdio { - cap-sd-highspeed; - keep-power-in-suspend; - non-removable; - mmc-pwrseq = <&sdio_pwrseq>; - sd-uhs-sdr104; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts>; - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-ringneck-haikou.dts b/arch/arm/dts/px30-ringneck-haikou.dts deleted file mode 100644 index 08a3ad3e7ae..00000000000 --- a/arch/arm/dts/px30-ringneck-haikou.dts +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "px30-ringneck.dtsi" -#include -#include - -/ { - model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit"; - compatible = "tsd,px30-ringneck-haikou", "rockchip,px30"; - - aliases { - mmc2 = &sdmmc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&haikou_keys_pin>; - pinctrl-names = "default"; - - button-batlow-n { - label = "BATLOW#"; - linux,code = ; - gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - }; - - button-slp-btn-n { - label = "SLP_BTN#"; - linux,code = ; - gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; - }; - - button-wake-n { - label = "WAKE#"; - linux,code = ; - gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - switch-lid-btn-n { - label = "LID_BTN#"; - linux,code = ; - linux,input-type = ; - gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>; - - sd_card_led: led-1 { - gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - function = LED_FUNCTION_SD; - color = ; - }; - }; - - i2s0-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Haikou,I2S-codec"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { - clocks = <&sgtl5000_clk>; - sound-dai = <&sgtl5000>; - }; - - simple-audio-card,cpu { - bitclock-master; - frame-master; - sound-dai = <&i2s0_8ch>; - }; - }; - - sgtl5000_clk: sgtl5000-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_baseboard: vcc3v3-baseboard-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_baseboard: vcc5v0-baseboard-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdda_codec: vdda-codec-regulator { - compatible = "regulator-fixed"; - regulator-name = "vdda_codec"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_baseboard>; - }; - - vddd_codec: vddd-codec-regulator { - compatible = "regulator-fixed"; - regulator-name = "vddd_codec"; - regulator-boot-on; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1600000>; - vin-supply = <&vcc5v0_baseboard>; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&sgtl5000_clk>; - #sound-dai-cells = <0>; - VDDA-supply = <&vdda_codec>; - VDDIO-supply = <&vcc3v3_baseboard>; - VDDD-supply = <&vddd_codec>; - }; -}; - -&i2c3 { - eeprom@50 { - reg = <0x50>; - compatible = "atmel,24c01"; - pagesize = <8>; - size = <128>; - vcc-supply = <&vcc3v3_baseboard>; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&gmac { - status = "okay"; -}; - -&pinctrl { - haikou { - haikou_keys_pin: haikou-keys-pin { - rockchip,pins = - /* WAKE# */ - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, - /* SLP_BTN# */ - <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, - /* LID_BTN */ - <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - /* BATLOW# */ - <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, - /* BIOS_DISABLE# */ - <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - sd_card_led_pin: sd-card-led-pin { - rockchip,pins = - <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&sdmmc { - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <&vcc3v3_baseboard>; - status = "okay"; -}; - -&spi1 { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart5 { - pinctrl-0 = <&uart5_xfer>; - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-ringneck.dtsi b/arch/arm/dts/px30-ringneck.dtsi deleted file mode 100644 index 12397755830..00000000000 --- a/arch/arm/dts/px30-ringneck.dtsi +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "px30.dtsi" -#include - -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdio; - rtc0 = &rtc_twi; - rtc1 = &rk809; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&module_led_pin>; - status = "okay"; - - module_led: led-0 { - gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - linux,default-trigger = "heartbeat"; - color = ; - }; - }; - - vcc5v0_sys: vccsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - supports-emmc; - mmc-pwrseq = <&emmc_pwrseq>; - non-removable; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_emmc>; - - status = "okay"; -}; - -/* On-module TI DP83825I PHY but no connector, enable in carrierboard */ -&gmac { - snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; - phy-supply = <&vcc_3v3>; - clock_in_out = "output"; -}; - -&gpio2 { - /* - * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module - * eMMC powered-down initially (in fact it keeps the reset signal - * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after - * the SPL has been booted from SD Card. - */ - bios-disable-override-hog { - gpios = ; - output-high; - line-name = "bios_disable_override"; - gpio-hog; - }; - - /* - * The BIOS_DISABLE hog is a feedback pin for the actual status of the - * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually - * represents the state of a switch on the baseboard. - */ - bios-disable-n-hog { - gpios = ; - line-name = "bios_disable"; - input; - gpio-hog; - }; -}; - -&gpu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pmic_int>; - pinctrl-names = "default"; - #clock-cells = <0>; - clock-output-names = "xin32k"; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc_3v3>; - vcc6-supply = <&vcc_3v3>; - vcc7-supply = <&vcc_3v3>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { - regulator-name = "vcc_3v0_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_3v3: DCDC_REG5 { - regulator-name = "vcc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v0: LDO_REG3 { - regulator-name = "vcc_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vcc_lcd"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_1v8_lcd: LDO_REG8 { - regulator-name = "vcc_1v8_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_1v8: LDO_REG9 { - regulator-name = "vcca_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - /* SE05x is limited to Fast Mode */ - clock-frequency = <400000>; - - fan: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #cooling-cells = <2>; - }; - - rtc_twi: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2s0_8ch { - rockchip,trcm-sync-tx-only; - - pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx - &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>; -}; - -&io_domains { - vccio1-supply = <&vcc_3v3>; - vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_3v3>; - vccio4-supply = <&vcc_3v3>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_emmc>; - vccio-oscgpi-supply = <&vcc_3v3>; - - status = "okay"; -}; - -&pinctrl { - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - module_led_pin: module-led-pin { - rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = - <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc { - vqmmc-supply = <&vccio_sd>; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -/* Mule UCAN */ -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index 04028bf649f..a31dea8db3e 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -74,6 +74,21 @@ bootph-all; }; +&rk817 { + regulators { + vcc_cam: LDO_REG9 { + regulator-name = "vcc_cam"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; +}; + &saradc { bootph-all; status = "okay"; diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts deleted file mode 100644 index ea0695b51ec..00000000000 --- a/arch/arm/dts/rk3326-odroid-go2.dts +++ /dev/null @@ -1,642 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Hardkernel Co., Ltd - * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include -#include -#include -#include "rk3326.dtsi" - -/ { - model = "ODROID-GO Advance"; - compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326"; - - aliases { - mmc0 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - adc-joystick { - compatible = "adc-joystick"; - io-channels = <&saradc 1>, - <&saradc 2>; - #address-cells = <1>; - #size-cells = <0>; - - axis@0 { - reg = <0>; - abs-flat = <10>; - abs-fuzz = <10>; - abs-range = <172 772>; - linux,code = ; - }; - - axis@1 { - reg = <1>; - abs-flat = <10>; - abs-fuzz = <10>; - abs-range = <278 815>; - linux,code = ; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc_bl>; - pwms = <&pwm1 0 25000 0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&btn_pins>; - - /* - * *** ODROIDGO2-Advance Switch layout *** - * |------------------------------------------------| - * | sw15 sw16 | - * |------------------------------------------------| - * | sw1 |-------------------| sw8 | - * | sw3 sw4 | | sw7 sw5 | - * | sw2 | LCD Display | sw6 | - * | | | | - * | |-------------------| | - * | sw9 sw10 sw11 sw12 sw13 sw14 | - * |------------------------------------------------| - */ - - sw1 { - gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; - label = "DPAD-UP"; - linux,code = ; - }; - sw2 { - gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; - label = "DPAD-DOWN"; - linux,code = ; - }; - sw3 { - gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; - label = "DPAD-LEFT"; - linux,code = ; - }; - sw4 { - gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; - label = "DPAD-RIGHT"; - linux,code = ; - }; - sw5 { - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; - label = "BTN-A"; - linux,code = ; - }; - sw6 { - gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; - label = "BTN-B"; - linux,code = ; - }; - sw7 { - gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; - label = "BTN-Y"; - linux,code = ; - }; - sw8 { - gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; - label = "BTN-X"; - linux,code = ; - }; - sw9 { - gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; - label = "F1"; - linux,code = ; - }; - sw10 { - gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; - label = "F2"; - linux,code = ; - }; - sw11 { - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - label = "F3"; - linux,code = ; - }; - sw12 { - gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; - label = "F4"; - linux,code = ; - }; - sw13 { - gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; - label = "F5"; - linux,code = ; - }; - sw14 { - gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; - label = "F6"; - linux,code = ; - }; - sw15 { - gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; - label = "TOP-LEFT"; - linux,code = ; - }; - sw16 { - gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; - label = "TOP-RIGHT"; - linux,code = ; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&blue_led_pin>; - - blue_led: led-0 { - label = "blue:heartbeat"; - gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - rk817-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Analog"; - simple-audio-card,format = "i2s"; - simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphones", - "Speaker", "Speaker"; - simple-audio-card,routing = - "MICL", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR", - "Speaker", "SPKO"; - - simple-audio-card,codec { - sound-dai = <&rk817>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s1_2ch>; - }; - }; - - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v8_sys"; - regulator-always-on; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - }; - - vcc_host: vcc_host { - compatible = "regulator-fixed"; - regulator-name = "vcc_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - vin-supply = <&usb_midu>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&cru { - assigned-clocks = <&cru PLL_NPLL>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, - <&cru PLL_CPLL>; - - assigned-clock-rates = <1188000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <200000000>, - <17000000>; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi { - status = "okay"; - - ports { - mipi_out: port@1 { - reg = <1>; - - mipi_out_panel: endpoint { - remote-endpoint = <&mipi_in_panel>; - }; - }; - }; - - panel@0 { - compatible = "elida,kd35t133"; - reg = <0>; - backlight = <&backlight>; - iovcc-supply = <&vcc_lcd>; - reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; - rotation = <270>; - vdd-supply = <&vcc_lcd>; - - port { - mipi_in_panel: endpoint { - remote-endpoint = <&mipi_out_panel>; - }; - }; - }; -}; - -&dsi_dphy { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_logic>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <16>; - i2c-scl-rising-time-ns = <280>; - status = "okay"; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - clock-output-names = "rk808-clkout1", "xin32k"; - clock-names = "mclk"; - clocks = <&cru SCLK_I2S1_OUT>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; - wakeup-source; - #clock-cells = <1>; - #sound-dai-cells = <0>; - - vcc1-supply = <&vccsys>; - vcc2-supply = <&vccsys>; - vcc3-supply = <&vccsys>; - vcc4-supply = <&vccsys>; - vcc5-supply = <&vccsys>; - vcc6-supply = <&vccsys>; - vcc7-supply = <&vccsys>; - vcc8-supply = <&vccsys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v3: DCDC_REG4 { - regulator-name = "vcc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc3v3_pmu: LDO_REG4 { - regulator-name = "vcc3v3_pmu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: LDO_REG6 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_bl: LDO_REG7 { - regulator-name = "vcc_bl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lcd: LDO_REG8 { - regulator-name = "vcc_lcd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <2800000>; - }; - }; - - vcc_cam: LDO_REG9 { - regulator-name = "vcc_cam"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - usb_midu: BOOST { - regulator-name = "usb_midu"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5400000>; - regulator-always-on; - regulator-boot-on; - }; - }; - - rk817_codec: codec { - rockchip,mic-in-differential; - }; - }; -}; - -/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */ -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -/* I2S 1 Channel Used */ -&i2s1_2ch { - status = "okay"; -}; - -&io_domains { - vccio1-supply = <&vcc_3v3>; - vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_3v3>; - vccio4-supply = <&vcc_3v3>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_3v3>; - status = "okay"; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc { - cap-sd-highspeed; - card-detect-delay = <200>; - cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/ - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sfc { - pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <1>; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "disabled"; - }; -}; - -&usb20_otg { - status = "okay"; -}; - -/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m1_xfer>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&pinctrl { - btns { - btn_pins: btn-pins { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - blue_led_pin: blue-led-pin { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dc_det: dc-det { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pmic_int: pmic-int { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - soc_slppin_gpio: soc_slppin_gpio { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; - }; - - soc_slppin_rst: soc_slppin_rst { - rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>; - }; - - soc_slppin_slp: soc_slppin_slp { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 661e7fd1c9f..14b3ab1a572 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -3,6 +3,7 @@ if ARCH_ROCKCHIP config ROCKCHIP_PX30 bool "Support Rockchip PX30" select ARM64 + imply OF_UPSTREAM select SUPPORT_SPL select SUPPORT_TPL select SPL diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index abe545625a5..488a259e268 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="px30-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-evb" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y # CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 063e4211fb7..3fe1dc3ab10 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +# CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index f4c9b02e12f..a9af4151014 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x4000 -CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3326-odroid-go2" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y # CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index dd005f20ff8..fdcbd8a0fc0 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-ctouch2-of10" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y # CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index f6559fbae3a..343fd0bf516 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-ctouch2" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y # CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index a099e9378c9..aa0bff4667d 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-edimm2.2" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y # CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 94179dca3ae..dedf35d4347 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-ringneck-haikou" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y # CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set From 9545163b1cb29f9a8269363ff43f3fb47fffc145 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Wed, 29 May 2024 01:03:57 +0800 Subject: [PATCH 09/34] arm64: dts: rockchip: Add rk3588 GPU node Add Mali GPU Node to the RK3588 SoC DT including GPU clock operating points Signed-off-by: Boris Brezillon Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner [ upstream commit: 6fca4edb93d335f29f81e484936f38a5eed6a9b1 ] (cherry picked from commit 3cd15354ea0c8668812bc0b3a4136606c10803e9) Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 87b83c87bd5..89d40cff635 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -501,6 +501,62 @@ status = "disabled"; }; + gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; + }; + pmu1grf: syscon@fd58a000 { compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfd58a000 0x0 0x10000>; From 376b0d051535aab5cd1dac7c2bc342121f7756b6 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Wed, 29 May 2024 01:03:58 +0800 Subject: [PATCH 10/34] arm64: dts: rockchip: Fix ordering of nodes on rk3588s Fix the ordering of the main nodes by sorting them alphabetically and then the ones with a memory address sequentially by that address. Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner [ upstream commit: cbb97fe18e299ece1c0074924c630de6a19b320f ] (cherry picked from commit bbf7c16f2f1208b96349f6f6648b69cfaa1a482b) Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 304 +++++++++---------- 1 file changed, 152 insertions(+), 152 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 89d40cff635..ac5bd630f15 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -347,6 +347,11 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + firmware { optee: optee { compatible = "linaro,optee-tz"; @@ -394,11 +399,6 @@ #clock-cells = <0>; }; - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = , @@ -436,6 +436,62 @@ }; }; + gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; + }; + usb_host0_ehci: usb@fc800000 { compatible = "rockchip,rk3588-ehci", "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; @@ -501,62 +557,6 @@ status = "disabled"; }; - gpu: gpu@fb000000 { - compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; - reg = <0x0 0xfb000000 0x0 0x200000>; - #cooling-cells = <2>; - assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; - assigned-clock-rates = <200000000>; - clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - clock-names = "core", "coregroup", "stacks"; - dynamic-power-coefficient = <2982>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3588_PD_GPU>; - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <700000 700000 850000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <750000 750000 850000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - }; - }; - }; - pmu1grf: syscon@fd58a000 { compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfd58a000 0x0 0x10000>; @@ -702,74 +702,6 @@ status = "disabled"; }; - vop: vop@fdd90000 { - compatible = "rockchip,rk3588-vop"; - reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = ; - clocks = <&cru ACLK_VOP>, - <&cru HCLK_VOP>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", - "pclk_vop"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; - rockchip,pmu = <&pmu>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - vp1: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - vp2: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - vp3: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - vop_mmu: iommu@fdd97e00 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VOP>; - status = "disabled"; - }; - uart0: serial@fd890000 { compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; reg = <0x0 0xfd890000 0x0 0x100>; @@ -1140,6 +1072,87 @@ }; }; + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; + interrupts = ; + interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3588_PD_AV1>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; + }; + + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + i2s4_8ch: i2s@fddc0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc0000 0x0 0x1000>; @@ -1431,6 +1444,16 @@ reg = <0x0 0xfdf82200 0x0 0x20>; }; + dfi: dfi@fe060000 { + reg = <0x00 0xfe060000 0x00 0x10000>; + compatible = "rockchip,rk3588-dfi"; + interrupts = , + , + , + ; + rockchip,pmu = <&pmu1grf>; + }; + pcie2x1l1: pcie@fe180000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; bus-range = <0x30 0x3f>; @@ -1533,16 +1556,6 @@ }; }; - dfi: dfi@fe060000 { - reg = <0x00 0xfe060000 0x00 0x10000>; - compatible = "rockchip,rk3588-dfi"; - interrupts = , - , - , - ; - rockchip,pmu = <&pmu1grf>; - }; - gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; @@ -2543,19 +2556,6 @@ #interrupt-cells = <2>; }; }; - - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - assigned-clock-rates = <400000000>, <400000000>; - clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3588_PD_AV1>; - resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; - }; }; #include "rk3588s-pinctrl.dtsi" From b88ddd5a82d728d8de1a71e2b25a62907b40b0bd Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 29 May 2024 01:03:59 +0800 Subject: [PATCH 11/34] arm64: dts: rockchip: fix usb2phy nodename for rk3588 usb2-phy should be named usb2phy according to the DT binding, so let's fix it up accordingly. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner [ upstream commit: 4e07a95f7402de092cd71b2cb96c69f85c98f251 ] (cherry picked from commit 5a3e4638492497ae81b9bd4a8627f4727e312ccc) Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index ac5bd630f15..87df0902273 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -599,7 +599,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy2: usb2-phy@8000 { + u2phy2: usb2phy@8000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0x8000 0x10>; interrupts = ; @@ -624,7 +624,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy3: usb2-phy@c000 { + u2phy3: usb2phy@c000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0xc000 0x10>; interrupts = ; From e1a374d5845e26016e7b67b0d531a6536c42b76b Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 29 May 2024 01:04:00 +0800 Subject: [PATCH 12/34] arm64: dts: rockchip: reorder usb2phy properties for rk3588 Reorder common DT properties alphabetically for usb2phy, according to latest DT style rules. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner [ upstream commit: abe68e0ca71dddce0e5419e35507cb464d61870d ] (cherry picked from commit f6835a60a8a28ff14ffb3dd80c99ce1c137d06c5) Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 87df0902273..58d12969b7e 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -602,13 +602,13 @@ u2phy2: usb2phy@8000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0x8000 0x10>; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names = "phy", "apb"; + #clock-cells = <0>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names = "phyclk"; clock-output-names = "usb480m_phy2"; - #clock-cells = <0>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; status = "disabled"; u2phy2_host: host-port { @@ -627,13 +627,13 @@ u2phy3: usb2phy@c000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0xc000 0x10>; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names = "phy", "apb"; + #clock-cells = <0>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names = "phyclk"; clock-output-names = "usb480m_phy3"; - #clock-cells = <0>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; status = "disabled"; u2phy3_host: host-port { From db60a2fc448657020f60c86ab5707129e399b22f Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 29 May 2024 01:04:01 +0800 Subject: [PATCH 13/34] arm64: dts: rockchip: add USBDP phys on rk3588 Add both USB3-DisplayPort PHYs to RK3588 SoC DT. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner [ upstream commit: e18e5e8188f2671abf63abe7db5f21555705130f ] (cherry picked from commit 5110caca9865718616cf7093ed4a9a1bc54780db) Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588.dtsi | 52 ++++++++++++++++ dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 63 ++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi index 5519c1430cb..4fdd047c9eb 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi @@ -17,6 +17,36 @@ reg = <0x0 0xfd5c0000 0x0 0x100>; }; + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -310,6 +340,28 @@ }; }; + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + combphy1_ps: phy@fee10000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee10000 0x0 0x100>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 58d12969b7e..9063c0bb0f0 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -572,12 +572,23 @@ reg = <0x0 0xfd5a4000 0x0 0x2000>; }; + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + vo1_grf: syscon@fd5a8000 { compatible = "rockchip,rk3588-vo-grf", "syscon"; reg = <0x0 0xfd5a8000 0x0 0x100>; clocks = <&cru PCLK_VO1GRF>; }; + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + php_grf: syscon@fd5b0000 { compatible = "rockchip,rk3588-php-grf", "syscon"; reg = <0x0 0xfd5b0000 0x0 0x1000>; @@ -593,6 +604,36 @@ reg = <0x0 0xfd5c4000 0x0 0x100>; }; + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg = <0x0 0xfd5d8000 0x0 0x4000>; @@ -2449,6 +2490,28 @@ status = "disabled"; }; + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; From 99ebe211690528cd988bb57e90b9d6a7922ebd46 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 29 May 2024 01:04:02 +0800 Subject: [PATCH 14/34] arm64: dts: rockchip: add USB3 DRD controllers on rk3588 Add both USB3 dual-role controllers to the RK3588 devicetree. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner [ upstream commit: 33f393a2a990e16f56931ca708295f31d2b44415 ] (cherry picked from commit c7ed588e14f7dd04a92fb55f12680f94c7b14edf) Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588.dtsi | 20 ++++++++++++++++++ dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi index 4fdd047c9eb..5984016b5f9 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi @@ -7,6 +7,26 @@ #include "rk3588-pinctrl.dtsi" / { + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = ; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + pcie30_phy_grf: syscon@fd5b8000 { compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; reg = <0x0 0xfd5b8000 0x0 0x10000>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 9063c0bb0f0..b0a59ec5183 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -492,6 +492,28 @@ }; }; + usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = ; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + usb_host0_ehci: usb@fc800000 { compatible = "rockchip,rk3588-ehci", "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; From 95967c4a7469c24f48d4f9c887ee979c0b5547e7 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Wed, 29 May 2024 01:04:03 +0800 Subject: [PATCH 15/34] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs The mmu600_pcie is connected with the five PCIe controllers. The mmu600_php is connected with the USB3 controller, the GMAC controllers, and the SATA controllers. See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual). The IOMMUs are disabled by default, as further patches are needed to program the SID/SSIDs in to the IOMMUs. iommu: Default domain type: Translated iommu: DMA domain TLB invalidation policy: strict mode arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf) arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs Additionally, the IOMMU correctly triggers an IOMMU fault when a PCIe device performs a write (since the device hasn't been assigned a SID/SSID): arm-smmu-v3 fc900000.iommu: event 0x02 received: arm-smmu-v3 fc900000.iommu: 0x0000010000000002 arm-smmu-v3 fc900000.iommu: 0x0000000000000000 arm-smmu-v3 fc900000.iommu: 0x0000000000000000 arm-smmu-v3 fc900000.iommu: 0x0000000000000000 While this doesn't provide much value as is, having the devices as disabled in the device tree will allow developers to see that the rk3588 actually has IOMMUs on the SoC. Signed-off-by: Niklas Cassel Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org Signed-off-by: Heiko Stuebner [ upstream commit: cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 ] (cherry picked from commit ea9a34aa0d786cbf4b87f1ba528e69b07219738f) Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 24 ++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index b0a59ec5183..6ac5ac8b48a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -579,6 +579,30 @@ status = "disabled"; }; + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + pmu1grf: syscon@fd58a000 { compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfd58a000 0x0 0x10000>; From 809b5167dfaba1771df061d4f0df5539d339fe0b Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Wed, 29 May 2024 01:04:04 +0800 Subject: [PATCH 16/34] arm64: dts: rockchip: Add ArmSom Sige7 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Specification: Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16/32GB Memory LPDDR4/LPDDR4x Mali G610MP4 GPU 2× MIPI-CSI Connector 1× MIPI-DSI Connector 1x M.2 Key M (PCIe 3.0 4-lanes) 2x RTL8125 2.5G Ethernet Onboard AP6275P for WIFI6/BT5 32GB/64GB/128GB eMMC MicroSD card slot 1x USB2.0, 1x USB3.0 Type-A, 1x US3.0 Type-C 1x HDMI Output, 1x type-C DP Output Functions work normally: USB2.0 Host USB3.0 Type-A Host M.2 Key M (PCIe 3.0 4-lanes) 2x RTL8125 2.5G Ethernet eMMC MicroSD card More information can be obtained from the following website https://docs.armsom.org/armsom-sige7 Signed-off-by: Jianfeng Liu Reviewed-by: Weizhao Ouyang Link: https://lore.kernel.org/r/20240420034300.176920-4-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner [ upstream commit: 81c828a67c78bb03ea75819c417c93c7f3d637b5 ] (cherry picked from commit d427a11542bcf5364a5260280e077f0a2e030dcb) Reviewed-by: Kever Yang --- .../arm64/rockchip/rk3588-armsom-sige7.dts | 721 ++++++++++++++++++ 1 file changed, 721 insertions(+) create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts new file mode 100644 index 00000000000..98c622b2764 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts @@ -0,0 +1,721 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3588.dtsi" + +/ { + model = "ArmSoM Sige7"; + compatible = "armsom,sige7", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s0_8ch_p0>; + label = "rk3588-es8316"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_g>; + + led_green: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led_red: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +/* phy1 - right ethernet port */ +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* phy2 - WiFi */ +&pcie2x1l1 { + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* phy0 - left ethernet port */ +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_rgb_g: led-rgb-g { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_r: led-rgb-r { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs200-1_8v; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; From 7a53abb18325979f8efb8ef3daf76951bc807a22 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Wed, 29 May 2024 01:04:05 +0800 Subject: [PATCH 17/34] rockchip: rk3588: Remove USB3 DRD nodes in u-boot.dtsi After we sync USB3 DRD nodes from v6.10-rc1, these obsolete nodes can be removed. Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-u-boot.dtsi | 74 --------------------------- arch/arm/dts/rk3588s-u-boot.dtsi | 85 -------------------------------- 2 files changed, 159 deletions(-) diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 4623580c610..bfe6645c30e 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -4,77 +4,3 @@ */ #include "rk3588s-u-boot.dtsi" - -/ { - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG1>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - usbdpphy1_grf: syscon@fd5cc000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5cc000 0x0 0x4000>; - }; - - usb2phy1_grf: syscon@fd5d4000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d4000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy1: usb2phy@4000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x4000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usbdp_phy1: phy@fed90000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed90000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY1_IMMORTAL>, - <&cru PCLK_USBDPPHY1>, - <&u2phy1>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, - <&cru SRST_USBDP_COMBO_PHY1_CMN>, - <&cru SRST_USBDP_COMBO_PHY1_LANE>, - <&cru SRST_USBDP_COMBO_PHY1_PCS>, - <&cru SRST_P_USBDPPHY1>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy1_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy1_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; -}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index e9d38d5c83b..09d8b311cec 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -19,95 +19,10 @@ bootph-all; }; - usb_host0_xhci: usb@fc000000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc000000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG0>; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - vo0_grf: syscon@fd5a6000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a6000 0x0 0x2000>; - clocks = <&cru PCLK_VO0GRF>; - }; - - usb_grf: syscon@fd5ac000 { - compatible = "rockchip,rk3588-usb-grf", "syscon"; - reg = <0x0 0xfd5ac000 0x0 0x4000>; - }; - - usbdpphy0_grf: syscon@fd5c8000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5c8000 0x0 0x4000>; - }; - - usb2phy0_grf: syscon@fd5d0000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d0000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy0: usb2phy@0 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x0 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - rng: rng@fe378000 { compatible = "rockchip,trngv1"; reg = <0x0 0xfe378000 0x0 0x200>; }; - - usbdp_phy0: phy@fed80000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed80000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY0_IMMORTAL>, - <&cru PCLK_USBDPPHY0>, - <&u2phy0>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, - <&cru SRST_USBDP_COMBO_PHY0_CMN>, - <&cru SRST_USBDP_COMBO_PHY0_LANE>, - <&cru SRST_USBDP_COMBO_PHY0_PCS>, - <&cru SRST_P_USBDPPHY0>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy0_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy0_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE From 40b573e4f6ed629eab54633f8836a2be5e5aa75a Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Wed, 29 May 2024 01:04:06 +0800 Subject: [PATCH 18/34] board: rockchip: add ArmSoM Sige7 Rk3588 board ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by ArmSoM. There are two variants depending on the DRAM size : 8G and 16G. Specification: Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB memory LPDDR4x Mali G610MC4 GPU 2x MIPI CSI 2 multiple lanes connector 64GB/128GB on board eMMC uSD slot 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C 1x HDMI 2.1 output 2x 2.5 Gbps Ethernet port 40-pin IO header including UART, SPI and I2C USB PD over USB Type-C Size: 92mm x 62mm Kernel commit: 81c828a67c78 (arm64: dts: rockchip: Add ArmSom Sige7 board) Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang --- MAINTAINERS | 1 + arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 6 ++ arch/arm/mach-rockchip/rk3588/Kconfig | 26 ++++++ board/armsom/sige7-rk3588/Kconfig | 12 +++ board/armsom/sige7-rk3588/MAINTAINERS | 7 ++ configs/sige7-rk3588_defconfig | 93 ++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/sige7-rk3588.h | 15 ++++ 8 files changed, 161 insertions(+) create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi create mode 100644 board/armsom/sige7-rk3588/Kconfig create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS create mode 100644 configs/sige7-rk3588_defconfig create mode 100644 include/configs/sige7-rk3588.h diff --git a/MAINTAINERS b/MAINTAINERS index 66783d636e3..6b32a6d9464 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -534,6 +534,7 @@ F: arch/arm/include/asm/arch-rockchip/ F: arch/arm/mach-rockchip/ F: board/amarula/vyasa-rk3288/ F: board/anbernic/rgxx3_rk3566/ +F: board/armsom/sige7-rk3588/ F: board/chipspark/popmetal_rk3288 F: board/engicam/px30_core/ F: board/firefly/ diff --git a/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi new file mode 100644 index 00000000000..af96d2fa8fb --- /dev/null +++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 ArmSoM Technology Co., Ltd. + */ + +#include "rk3588-u-boot.dtsi" diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 820e979abb1..9f82e9f3371 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -161,6 +161,31 @@ config TARGET_ROCK5B_RK3588 USB PD over USB Type-C Size: 100mm x 72mm (Pico-ITX form factor) +config TARGET_SIGE7_RK3588 + bool "ArmSoM Sige7 RK3588 board" + select BOARD_LATE_INIT + help + ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) + by ArmSoM. + + There are two variants depending on the DRAM size : 8G and 16G. + + Specification: + + Rockchip Rk3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB memory LPDDR4x + Mali G610MC4 GPU + 2x MIPI CSI 2 multiple lanes connector + 64GB/128GB on board eMMC + uSD slot + 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C + 1x HDMI 2.1 output + 2x 2.5 Gbps Ethernet port + 40-pin IO header including UART, SPI and I2C + USB PD over USB Type-C + Size: 92mm x 62mm + config TARGET_QUARTZPRO64_RK3588 bool "Pine64 QuartzPro64 RK3588 board" select BOARD_LATE_INIT @@ -230,6 +255,7 @@ config ROCKCHIP_COMMON_STACK_ADDR config TEXT_BASE default 0x00a00000 +source "board/armsom/sige7-rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/indiedroid/nova/Kconfig" diff --git a/board/armsom/sige7-rk3588/Kconfig b/board/armsom/sige7-rk3588/Kconfig new file mode 100644 index 00000000000..793985f531b --- /dev/null +++ b/board/armsom/sige7-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SIGE7_RK3588 + +config SYS_BOARD + default "sige7-rk3588" + +config SYS_VENDOR + default "armsom" + +config SYS_CONFIG_NAME + default "sige7-rk3588" + +endif diff --git a/board/armsom/sige7-rk3588/MAINTAINERS b/board/armsom/sige7-rk3588/MAINTAINERS new file mode 100644 index 00000000000..0fba39b76c2 --- /dev/null +++ b/board/armsom/sige7-rk3588/MAINTAINERS @@ -0,0 +1,7 @@ +SIGE7-RK3588 +M: Jianfeng Liu +S: Maintained +F: board/armsom/sige7-rk3588 +F: include/configs/sige7-rk3588.h +F: configs/sige7-rk3588_defconfig +F: arch/arm/dts/rk3588-armsom-sige7* diff --git a/configs/sige7-rk3588_defconfig b/configs/sige7-rk3588_defconfig new file mode 100644 index 00000000000..d15fc09fc8d --- /dev/null +++ b/configs/sige7-rk3588_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-armsom-sige7" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_SIGE7_RK3588=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-armsom-sige7.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index cfbf641f494..fec8675c8be 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -119,6 +119,7 @@ List of mainline supported Rockchip boards: - Radxa ROCK 3 Model A (rock-3a-rk3568) * rk3588 + - ArmSoM Sige7 (sige7-rk3588) - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) diff --git a/include/configs/sige7-rk3588.h b/include/configs/sige7-rk3588.h new file mode 100644 index 00000000000..fd08da568b1 --- /dev/null +++ b/include/configs/sige7-rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 ArmSoM Technology Co., Ltd. + */ + +#ifndef __SIGE7_RK3588_H +#define __SIGE7_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif /* __SIGE7_RK3588_H */ From 67f87e215c9332d222212da4843cc5a3c0e744cb Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 6 Jun 2024 10:45:31 +0200 Subject: [PATCH 19/34] rockchip: jaguar-rk3588: use default env size for Rockchip on MMC The default env size is 0x8000 when building for Rockchip SoCs with support for environment stored in MMC. Jaguar hasn't entered mass production just yet, so it's a breaking change we can afford in the name of consistency. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/jaguar-rk3588_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index b69cf4cd057..36bf34d97c8 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_ENV_SIZE=0x1f000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-jaguar" CONFIG_ROCKCHIP_RK3588=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 From eeaa46a70e18d1afb27dbf096c2536294d2d0a4d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 6 Jun 2024 10:45:32 +0200 Subject: [PATCH 20/34] rockchip: rk3399-puma: remove default value from defconfig CONFIG_ENV_OFFSET already defaults to 0x3F8000, however it is stored in lowercase hexdigits instead of uppercase like in the defconfig. No change in behavior intended. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/puma-rk3399_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 34a0b575991..42819102d70 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -6,7 +6,6 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_SIZE=0x3000 -CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-puma-haikou" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y From b58e0d304b1896f70ab1ba66a2162d0df9deef6b Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 6 Jun 2024 10:45:33 +0200 Subject: [PATCH 21/34] rockchip: rk3399-puma: remove unnecessary simple-bin:fit:offset override Since commit 6007b69d544e ("rockchip: rk3399-puma: Update SPL_PAD_TO Kconfig option"), SPL_PAD_TO matches (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512 and the default value for simple-bin:fit:offset in rockchip-u-boot.dtsi is SPL_PAD_TO, so let's remove this override. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index 5a9bd320ec4..55895d0dd19 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -33,12 +33,6 @@ }; &binman { - simple-bin { - fit { - offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>; - }; - }; - #ifdef CONFIG_ROCKCHIP_SPI_IMAGE simple-bin-spi { fit { From aefdec52771694dcaac8bcc6f9772c0b375fc1bd Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 6 Jun 2024 10:45:34 +0200 Subject: [PATCH 22/34] rockchip: px30-ringneck: Update SPL_PAD_TO Kconfig option On px30-ringneck the FIT payload is located at sector 0x200 compared to the more Rockchip common sector 0x4000 offset: SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 Because FIT payload is located at sector 0x200 and the TPL+SPL is located at sector 64, the combined size of TPL+SPL cannot take up more than 224KiB: (0x200 - 64) x 512 = 0x38000 (224 KiB) Adjust SPL_PAD_TO to match the used 0x200 sector offset. While at it, update the px30-ringneck-u-boot.dtsi to remove the now unnecessary override of simple-bin:fit:offset since SPL_PAD_TO matches with the current formula. Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi | 8 -------- configs/ringneck-px30_defconfig | 2 +- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi index e04766ad09c..29ea2763636 100644 --- a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi +++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi @@ -15,14 +15,6 @@ }; }; -&binman { - simple-bin { - fit { - offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>; - }; - }; -}; - &emmc_clk { bootph-all; }; diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index dedf35d4347..a22d25e0089 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 -CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_PAD_TO=0x38000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set From 2ce40542e0ebc9b782954ae6df3a23885ff60cf1 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 6 Jun 2024 10:45:35 +0200 Subject: [PATCH 23/34] power: rk8xx: properly print all supported PMICs name The ID of the PMIC is stored in the 2 16b registers but the only part that matters right now is the 3 MSB, which make the 3 digits (in hex) of the part number. Right now, only RK808 was properly displayed, with this all currently supported PMICs should display the proper part number. Additionally, when the PMIC variant is not found, print that value instead of the masked unshifted value as all PMICs we support for now have their LSB ignored to represent the actual part number. Tested on RK806 (RK3588 Jaguar), RK808 (RK3399 Puma) and RK809 (PX30 Ringneck). Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/power/pmic/rk8xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 12ff26a0855..617bb511e4e 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -277,10 +278,9 @@ static int rk8xx_probe(struct udevice *dev) return ret; priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; - show_variant = priv->variant; + show_variant = bitfield_extract_by_mask(priv->variant, RK8XX_ID_MSK); switch (priv->variant) { case RK808_ID: - show_variant = 0x808; /* RK808 hardware ID is 0 */ break; case RK805_ID: case RK816_ID: @@ -311,7 +311,7 @@ static int rk8xx_probe(struct udevice *dev) init_data_num = ARRAY_SIZE(rk806_init_reg); break; default: - printf("Unknown PMIC: RK%x!!\n", priv->variant); + printf("Unknown PMIC: RK%x!!\n", show_variant); return -EINVAL; } From 724d3c686c57b3ce50a39dceb3f3f1ebc9d3e32c Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 6 Jun 2024 10:45:36 +0200 Subject: [PATCH 24/34] rockchip: ringneck-px30: fix TPL_MAX_SIZE Ringneck was mistakenly set to allow up to 128KiB for the TPL code size while PX30 SoC only has 16KiB of SRAM. Therefore, let's use the default value of TPL_MAX_SIZE from the SoC (which is 10KiB) so that the max code size is actually checked and useful. Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit") Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/ringneck-px30_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index a22d25e0089..9965e55d611 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -14,7 +14,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_DEBUG_UART_BASE=0xFF030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y From a764eb156a06fd8ab073bdaa86df41b4ed3c5209 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 10 Jun 2024 15:13:31 +0200 Subject: [PATCH 25/34] arm64: dts: rockchip: enable gpu on rk3588-tiger Enable the mali gpu node and add the som-specific supply-regulator. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240327112120.1181570-2-heiko@sntech.de Signed-off-by: Heiko Stuebner [ upstream commit: f5256f8ed4b729c3ab9d9cd7d406313773484b59 ] (cherry picked from commit 27350b241eafea37dc94743cd9c5dd83295faca9) --- dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi index 1eb2543a5fd..72fe696b003 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi @@ -139,6 +139,11 @@ snps,reset-delays-us = <0 10000 100000>; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c1 { pinctrl-0 = <&i2c1m0_xfer>; }; From d09cd18aedd9fb2abcb6f3003375f680e28ae104 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 10 Jun 2024 15:13:32 +0200 Subject: [PATCH 26/34] arm64: dts: rockchip: move uart2 pinmux to dtsi on rk3588-tiger The association of uart2 to the q7-uart pins is part of the module itself and not the baseboard used. Therefore move the pinctrl over to the tiger dtsi. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240422143356.2596414-1-heiko@sntech.de Signed-off-by: Heiko Stuebner [ upstream commit: 5adbad5c464a708a87cf5ade1bfe2ca947bb2f82 ] (cherry picked from commit f8314a4fbc00a3d651a7e9b4d9462d10c6c02a12) --- dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts | 1 - dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts index d672198c6b6..9bdd14799ef 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts @@ -231,7 +231,6 @@ }; &uart2 { - pinctrl-0 = <&uart2m2_xfer>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi index 72fe696b003..4984e36a8c2 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi @@ -688,6 +688,11 @@ status = "okay"; }; +/* Routed to UART0 on the Q7 connector */ +&uart2 { + pinctrl-0 = <&uart2m2_xfer>; +}; + /* Mule-ATtiny UPDI */ &uart4 { pinctrl-0 = <&uart4m2_xfer>; From 5d12fcf03395527b38d264c3c5bf8b4f77f77ec3 Mon Sep 17 00:00:00 2001 From: Jing Luo Date: Mon, 10 Jun 2024 15:13:33 +0200 Subject: [PATCH 27/34] arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards gpio_pwrctrl2 gets duplicated by both rk806_dvs1_null and rk806_dvs2_null gpio_pwrctrl1 is unset. This typo appears in multiple files. Let's fix them. Note: I haven't had the chance to test them all because I don't own all of these boards (obviously). Please test if it's needed. Signed-off-by: Jing Luo Link: https://lore.kernel.org/r/20240420130355.639406-1-jing@jing.rocks Signed-off-by: Heiko Stuebner [ upstream commit: d7f2039e5321636069baa77ef2f1e5d22cb69a88 ] (cherry picked from commit cb2b6d1d19ed10fcaec5f5859c08a3355d1c66e0) Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi | 2 +- .../src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi | 2 +- dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 2 +- dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi | 2 +- dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi | 2 +- dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts | 2 +- dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts | 2 +- dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts | 2 +- dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi index 94ecb9b4f98..170501a879d 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi @@ -357,7 +357,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi index c0d4a15323e..d9bf67525e8 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -182,7 +182,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts index 39d65002add..7d7303f8ecb 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts @@ -452,7 +452,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi index 4984e36a8c2..29f8e536de1 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi @@ -401,7 +401,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi index dc08da518a7..6b9206ce4a0 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi @@ -318,7 +318,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts index e037bf9db75..7f4d7bb9a07 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts @@ -479,7 +479,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts index ce8119cbb82..a5b76e24ceb 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts @@ -528,7 +528,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts index 25de4362af3..73700d77eed 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts @@ -336,7 +336,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts index 00afb90d4eb..5c99636a1d0 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts @@ -414,7 +414,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; From 192e8d66e3b0c55fdade64ca8ee961945bd5d8b0 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 10 Jun 2024 15:13:34 +0200 Subject: [PATCH 28/34] arm64: dts: rockchip: fix pcie-refclk frequency on rk3588 tiger The clock-generator of course only produces a 100MHz clock rate, not 1GHz. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240423114635.2637310-1-heiko@sntech.de Signed-off-by: Heiko Stuebner [ upstream commit: 0eb2a93518fb4728bd1d55fcd3b57fce4797ef1d ] (cherry picked from commit b574cbafae976cf508692088944e45c9764c0048) --- dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi index 29f8e536de1..a8565720cf5 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi @@ -46,7 +46,7 @@ pcie_refclk_gen: pcie-refclk-gen-clock { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <1000000000>; + clock-frequency = <100000000>; }; pcie_refclk: pcie-refclk-clock { From 34c0f6d223afc2bb835d6e77f9f83daf3c0db644 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 10 Jun 2024 15:13:35 +0200 Subject: [PATCH 29/34] arm64: dts: rockchip: fix comment for upper usb3 port The comment for the host2_xhci points to the wrong port on the board. The upper usb3 port is the correct one, so fix the comment to prevent confusion. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240422163951.2604273-2-heiko@sntech.de Signed-off-by: Heiko Stuebner [ upstream commit: 3482efee1144262dc839792103e6a9e29defecbc ] (cherry picked from commit 56f3031edf22d163f10bc4b631d37a9aaa82d4d4) --- dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts index 9bdd14799ef..2aa43e7430e 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts @@ -239,12 +239,12 @@ status = "okay"; }; -/* host0 on Q7_USB_P2, lower usb3 port */ +/* host0 on Q7_USB_P2, upper usb3 port */ &usb_host0_ehci { status = "okay"; }; -/* host0 on Q7_USB_P2, lower usb3 port */ +/* host0 on Q7_USB_P2, upper usb3 port */ &usb_host0_ohci { status = "okay"; }; @@ -259,7 +259,7 @@ status = "okay"; }; -/* host2 on Q7_USB_P2, lower usb3 port */ +/* host2 on Q7_USB_P2, upper usb3 port */ &usb_host2_xhci { status = "okay"; }; From d00d80e6dd02138ed2e299925c8bd064513a6d3d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 10 Jun 2024 15:13:36 +0200 Subject: [PATCH 30/34] arm64: dts: rockchip: add usb-id extcon on rk3588 tiger The Q7 standard specifies a usb-id pin on the connector to distiuish between host and device mode. Model this via the usb-id extcon binding. While the pin is part of the Q7 standard, so part of the module, the extcon stays disabled in the som dtsi and will only be enabled in a baseboard using it. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240422163951.2604273-3-heiko@sntech.de Signed-off-by: Heiko Stuebner [ upstream commit: eabb53f5dacfd643b5255f35bad30b8f914decdc ] (cherry picked from commit 4843cec4092318ef7feb0999b0d34ef817465b33) --- dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi index a8565720cf5..aebe1fedd2d 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi @@ -23,6 +23,14 @@ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; }; + extcon_usb3: extcon-usb3 { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_id>; + status = "disabled"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -327,6 +335,13 @@ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb3 { + usb3_id: usb3-id { + rockchip,pins = + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &saradc { From b467cb0ec9197072a3628687a9a5095dfd3bff86 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 10 Jun 2024 15:13:37 +0200 Subject: [PATCH 31/34] arm64: dts: rockchip: add dual-role usb3 hosts to rk3588 Tiger-Haikou Apart from the host-only usb3 controller (host2) the rk3588 also provides two dual-role controllers. On the Tiger-Haikou combination these are connected to the lower usb3-host port in host-only mode and the micro-usb3 port for dual-role operation. Add the necessary controllers, phys to the Tiger-Haikou board and enable the usb-id extcon. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240422163951.2604273-4-heiko@sntech.de Signed-off-by: Heiko Stuebner [ upstream commit: d7b83921d098bd76623381f75f5cd2296f1315cc ] (cherry picked from commit 193d3b2a0a98f2dcd8c43bcbf8a766098a9fa75d) --- .../arm64/rockchip/rk3588-tiger-haikou.dts | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts index 2aa43e7430e..e4b7a0a4444 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts @@ -113,6 +113,16 @@ vin-supply = <&dc_12v>; }; + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; + vcc5v0_usb: vcc5v0-usb-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb"; @@ -137,6 +147,10 @@ status = "okay"; }; +&extcon_usb3 { + status = "okay"; +}; + &gmac0 { status = "okay"; }; @@ -199,6 +213,13 @@ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + usb2 { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &sdmmc { @@ -214,6 +235,23 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -236,6 +274,13 @@ &uart5 { rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy1 { status = "okay"; }; @@ -249,6 +294,13 @@ status = "okay"; }; +/* host0_xhci on Q7_USB_P1, usb3-otg port */ +&usb_host0_xhci { + dr_mode = "otg"; + extcon = <&extcon_usb3>; + status = "okay"; +}; + /* host1 on Q7_USB_P3, usb2 port */ &usb_host1_ehci { status = "okay"; @@ -259,6 +311,12 @@ status = "okay"; }; +/* host1_xhci on Q7_USB_P0, lower usb3 port */ +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + /* host2 on Q7_USB_P2, upper usb3 port */ &usb_host2_xhci { status = "okay"; From f0d356610b0854f19f62599024fbeb6fb34c4d57 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 10 Jun 2024 15:13:38 +0200 Subject: [PATCH 32/34] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3588. It provides the following feature set: * up to 16GB LPDDR4x * on-module eMMC * SD card (on a baseboard) via edge connector * Gigabit Ethernet with on-module GbE PHY * HDMI/eDP * MIPI-DSI * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7) * HDMI input over FPC connector * CAN * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 host * PCIe - 1x PCIe 2.1 Gen3, 4 lanes - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes * on-module ATtiny816 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) * on-module Secure Element with Global Platform 2.2.1 compliant JavaCard environment The support is added for Tiger on Haikou devkit, similarly to RK3399 Puma and PX30 Ringneck. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Tested-by: Heiko Stuebner Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 37 ++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 31 +++++ board/theobroma-systems/tiger_rk3588/Kconfig | 16 +++ .../tiger_rk3588/MAINTAINERS | 13 ++ board/theobroma-systems/tiger_rk3588/Makefile | 10 ++ .../tiger_rk3588/tiger_rk3588.c | 53 ++++++++ configs/tiger-rk3588_defconfig | 113 ++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + doc/board/theobroma-systems/index.rst | 1 + doc/board/theobroma-systems/tiger_rk3588.rst | 102 ++++++++++++++++ include/configs/tiger_rk3588.h | 15 +++ 11 files changed, 392 insertions(+) create mode 100644 arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi create mode 100644 board/theobroma-systems/tiger_rk3588/Kconfig create mode 100644 board/theobroma-systems/tiger_rk3588/MAINTAINERS create mode 100644 board/theobroma-systems/tiger_rk3588/Makefile create mode 100644 board/theobroma-systems/tiger_rk3588/tiger_rk3588.c create mode 100644 configs/tiger-rk3588_defconfig create mode 100644 doc/board/theobroma-systems/tiger_rk3588.rst create mode 100644 include/configs/tiger_rk3588.h diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi new file mode 100644 index 00000000000..275ae6fdaea --- /dev/null +++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; + +&emmc_pwrseq { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_reset { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + /* U-Boot currently cannot handle anything below HS200 for eMMC on RK3588 */ + /delete-property/ mmc-ddr-1_8v; + /delete-property/ cap-mmc-highspeed; +}; + +&uart2m2_xfer { + bootph-all; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 9f82e9f3371..9a35c7d9cc2 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -193,6 +193,36 @@ config TARGET_QUARTZPRO64_RK3588 Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board Computer) by Pine64. +config TARGET_TIGER_RK3588 + bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)" + select BOARD_LATE_INIT + help + The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 + connector) system-on-module from Theobroma Systems, featuring the + Rockchip RK3588. + + It provides the following feature set: + * up to 16GB LPDDR4x + * on-module eMMC + * SD card (on a baseboard) via edge connector + * Gigabit Ethernet with on-module GbE PHY + * HDMI/eDP + * MIPI-DSI + * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7) + * HDMI input over FPC connector + * CAN + * USB + - 1x USB 3.0 dual-role (direct connection) + - 2x USB 3.0 host + 1x USB 2.0 host + * PCIe + - 1x PCIe 2.1 Gen3, 4 lanes + - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes + * on-module ATtiny816 companion controller, implementing: + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + * on-module Secure Element with Global Platform 2.2.1 compliant + JavaCard environment + config TARGET_TURINGRK1_RK3588 bool "Turing Machines RK1 RK3588 board" select BOARD_LATE_INIT @@ -266,5 +296,6 @@ source "board/radxa/rock5b-rk3588/Kconfig" source "board/rockchip/evb_rk3588/Kconfig" source "board/rockchip/toybrick_rk3588/Kconfig" source "board/theobroma-systems/jaguar_rk3588/Kconfig" +source "board/theobroma-systems/tiger_rk3588/Kconfig" endif diff --git a/board/theobroma-systems/tiger_rk3588/Kconfig b/board/theobroma-systems/tiger_rk3588/Kconfig new file mode 100644 index 00000000000..2c6ac6a9a83 --- /dev/null +++ b/board/theobroma-systems/tiger_rk3588/Kconfig @@ -0,0 +1,16 @@ +if TARGET_TIGER_RK3588 + +config SYS_BOARD + default "tiger_rk3588" + +config SYS_VENDOR + default "theobroma-systems" + +config SYS_CONFIG_NAME + default "tiger_rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ENV_IS_NOWHERE + +endif diff --git a/board/theobroma-systems/tiger_rk3588/MAINTAINERS b/board/theobroma-systems/tiger_rk3588/MAINTAINERS new file mode 100644 index 00000000000..e5aab4b29f3 --- /dev/null +++ b/board/theobroma-systems/tiger_rk3588/MAINTAINERS @@ -0,0 +1,13 @@ +TIGER-RK3588 (SOM-RK3588-Q7) +M: Klaus Goger +M: Quentin Schulz +M: Heiko Stuebner +S: Maintained +F: board/theobroma-systems/tiger_rk3588 +F: board/theobroma-systems/common +F: doc/board/theobroma-systems/ +F: include/configs/tiger_rk3588.h +F: arch/arm/dts/rk3588-tiger* +F: configs/tiger-rk3588_defconfig +W: https://embedded.cherry.de/product/tiger-som-rk3588-q7/ +T: git git://git.embedded.cherry.de/tiger-u-boot.git diff --git a/board/theobroma-systems/tiger_rk3588/Makefile b/board/theobroma-systems/tiger_rk3588/Makefile new file mode 100644 index 00000000000..5c4c484657a --- /dev/null +++ b/board/theobroma-systems/tiger_rk3588/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += tiger_rk3588.o +ifneq ($(CONFIG_SPL_BUILD),y) +obj-y += ../common/common.o +endif diff --git a/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c b/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c new file mode 100644 index 00000000000..a6d44f10db3 --- /dev/null +++ b/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/common.h" + +#define GPIO2C3_SEL_MASK GENMASK(15, 12) +#define GPIO2C3_ETH0_REFCLKO_25M FIELD_PREP(GPIO2C3_SEL_MASK, 1) + +#define REFCLKO25M_ETH0_OUT_SEL_MASK BIT(15) +#define REFCLKO25M_ETH0_OUT_SEL_CPLL FIELD_PREP(REFCLKO25M_ETH0_OUT_SEL_MASK, 1) +#define REFCLKO25M_ETH0_OUT_DIV_MASK GENMASK(14, 8) +#define REFCLKO25M_ETH0_OUT_DIV(x) FIELD_PREP(REFCLKO25M_ETH0_OUT_DIV_MASK, (x) - 1) + +#define REFCLKO25M_ETH0_OUT_EN BIT(4) + +void setup_eth0refclko(void) +{ + /* Configure and enable ETH0_REFCLKO_25MHz */ + static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE; + static struct rk3588_cru * const cru = (void *)CRU_BASE; + + /* 1. Pinmux */ + rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l, GPIO2C3_SEL_MASK, GPIO2C3_ETH0_REFCLKO_25M); + /* 2. Parent clock selection + divider => CPLL (1.5GHz) / 60 => 25MHz */ + rk_clrsetreg(&cru->clksel_con[15], + REFCLKO25M_ETH0_OUT_SEL_MASK | REFCLKO25M_ETH0_OUT_DIV_MASK, + REFCLKO25M_ETH0_OUT_SEL_CPLL | REFCLKO25M_ETH0_OUT_DIV(60)); + /* 3. Enable clock */ + rk_clrreg(&cru->clkgate_con[5], REFCLKO25M_ETH0_OUT_EN); +} + +int rockchip_early_misc_init_r(void) +{ + setup_boottargets(); + + setup_eth0refclko(); + + return 0; +} diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig new file mode 100644 index 00000000000..8fcdd063a3d --- /dev/null +++ b/configs/tiger-rk3588_defconfig @@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-tiger-haikou" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_TIGER_RK3588=y +CONFIG_DEBUG_UART_BASE=0xfeb50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +# CONFIG_DEBUG_UART_BOARD_INIT is not set +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_BOOTMETH_VBE is not set +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-tiger-haikou.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CYCLIC=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SF is not set +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MII is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EROFS=y +CONFIG_CMD_SQUASHFS=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +# CONFIG_OF_TAG_MIGRATE is not set +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_SPL_CLK=y +CONFIG_CLK_GPIO=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_SPL_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +# CONFIG_SPI_FLASH is not set +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index fec8675c8be..eaf71673b7f 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -131,6 +131,7 @@ List of mainline supported Rockchip boards: - Radxa ROCK 5B (rock5b-rk3588) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) + - Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588) - Turing Machines RK1 (turing-rk1-rk3588) - Xunlong Orange Pi 5 (orangepi-5-rk3588s) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) diff --git a/doc/board/theobroma-systems/index.rst b/doc/board/theobroma-systems/index.rst index b4da2616c37..73e07f7ebfa 100644 --- a/doc/board/theobroma-systems/index.rst +++ b/doc/board/theobroma-systems/index.rst @@ -9,3 +9,4 @@ Theobroma Systems jaguar_rk3588 puma_rk3399 ringneck_px30 + tiger_rk3588 diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst new file mode 100644 index 00000000000..a73eec7fb9b --- /dev/null +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -0,0 +1,102 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +SOM-RK3588-Q7 Tiger +=================== + +The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 +connector) system-on-module from Theobroma Systems, featuring the +Rockchip RK3588. + +It provides the following feature set: + * up to 16GB LPDDR4x + * on-module eMMC + * SD card (on a baseboard) via edge connector + * Gigabit Ethernet with on-module GbE PHY + * HDMI/eDP + * MIPI-DSI + * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7) + * HDMI input over FPC connector + * CAN + * USB + - 1x USB 3.0 dual-role (direct connection) + - 2x USB 3.0 host + 1x USB 2.0 host + * PCIe + - 1x PCIe 2.1 Gen3, 4 lanes + - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes + * on-module ATtiny816 companion controller, implementing: + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + * on-module Secure Element with Global Platform 2.2.1 compliant + JavaCard environment + +Here is the step-by-step to boot to U-Boot on SOM-RK3588-Q7 Tiger from Theobroma +Systems. + +Get the TF-A and DDR init (TPL) binaries +---------------------------------------- + +.. prompt:: bash + + git clone https://github.com/rockchip-linux/rkbin + cd rkbin + export RKBIN=$(pwd) + export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf + export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin + sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt + sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt + ./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL" + ./tools/boot_merger RKBOOT/RK3588MINIALL.ini + export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin + +This will setup all required external dependencies for compiling U-Boot. This will +be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot +gains support for open-source DRAM initialization in TPL. + +Build U-Boot +------------ + +.. prompt:: bash + + cd ../u-boot + make CROSS_COMPILE=aarch64-linux-gnu- tiger-rk3588_defconfig all + +This will build ``u-boot-rockchip.bin`` which can be written to an MMC device +(eMMC or SD card). + +Flash the image +--------------- + +Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC. + +SD-Card +~~~~~~~ + +.. prompt:: bash + + dd if=u-boot-rockchip.bin of=/dev/sdX seek=64 + +.. note:: + + Replace ``/dev/sdX`` to match your SD card kernel device. + +eMMC +~~~~ + +``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface +with help of the Rockchip loader binary. + +To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a +micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into +``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch +back to ``Normal Boot`` mode. A new USB device should have appeared on your PC +(check with ``lsusb -d 2207:350b``). + +To flash U-Boot on the eMMC with ``rkdeveloptool``: + +.. prompt:: bash + + git clone https://github.com/rockchip-linux/rkdeveloptool + cd rkdeveloptool + autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make + ./rkdeveloptool db "$RKDB" + ./rkdeveloptool wl 64 ../u-boot-rockchip.bin diff --git a/include/configs/tiger_rk3588.h b/include/configs/tiger_rk3588.h new file mode 100644 index 00000000000..7a32adfaf2a --- /dev/null +++ b/include/configs/tiger_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#ifndef __TIGER_RK3588_H +#define __TIGER_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif /* __TIGER_RK3588_H */ From 702e29d9e00dcef46b90b26a6d04771b4cec686e Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 12 Jun 2024 16:40:48 +0200 Subject: [PATCH 33/34] rockchip: ringneck-px30: get closer to other Theobroma defconfigs RK3588 Jaguar and Tiger, and RK3399 Puma use standard boot with the full feature set, so let's do that as well for PX30 Ringneck. Disable support for unused OSes as Linux is the primary target. Enable a bunch of commands: - boot/bootd - erofs - gpio - iminfo - imxtract - itest - pmic - regulator - sleep - squashfs that could be useful and are also found in Jaguar and Tiger defconfigs. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/ringneck-px30_defconfig | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 9965e55d611..23204794205 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -19,6 +19,7 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -33,12 +34,15 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_TPL_SYS_MALLOC_SIMPLE is not set -# CONFIG_CMD_BOOTD is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_VBE is not set +# CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set @@ -46,9 +50,11 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EROFS=y +CONFIG_CMD_SQUASHFS=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 From ae4aaa44977cbe522e9f38f2ac2ac07a784bf867 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 12 Jun 2024 16:40:49 +0200 Subject: [PATCH 34/34] rockchip: puma-rk3399: get closer to other Theobroma defconfigs Disable support for unused OSes as Linux is the primary target. Disable support for bootz as zImage isn't a format compatible with Aarch64 machines so it should never be attempted to be booted. Enable a bunch of commands: - erofs - gpio - squashfs that could be useful and are also found in Jaguar and Tiger defconfigs. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- configs/puma-rk3399_defconfig | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 42819102d70..5319239f989 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -28,7 +28,12 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y -CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_VBE is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -40,6 +45,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EROFS=y +CONFIG_CMD_SQUASHFS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_OVERWRITE=y