Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

This commit is contained in:
Albert ARIBAUD
2014-01-29 14:07:50 +01:00
34 changed files with 157 additions and 1144 deletions

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@@ -43,7 +43,7 @@
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
#define MT41J128MJT125_EMIF_TIM3 0x501F830F
@@ -65,7 +65,7 @@
#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
/* Micron MT41J256M8HX-15E */
#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
@@ -97,7 +97,7 @@
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
/* Micron MT41J512M8RH-125 on EVM v1.5 */
#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
@@ -113,7 +113,7 @@
#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
/* Samsung K4B2G1646E-BIH9 */
#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07
#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF

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@@ -140,13 +140,13 @@ struct gpio {
SRAM_OFFSET2)
#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64)
#define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */
#define OMAP3_PUBLIC_SRAM_END 0x40210000
#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
#define NON_SECURE_SRAM_END 0x40210000
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
/* scratch area - accessible on both EMU and GP */
#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA OMAP3_PUBLIC_SRAM_BASE
#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START
#define DEBUG_LED1 149 /* gpio */
#define DEBUG_LED2 150 /* gpio */

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@@ -30,7 +30,6 @@ void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
void set_muxconf_regs_non_essential(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);

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@@ -44,6 +44,7 @@
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
@@ -204,6 +205,8 @@ struct s32ktimer {
/* ABB efuse masks */
#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24)
#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29)
#define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20)
#define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25)
#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)

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@@ -31,7 +31,6 @@ void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
void set_muxconf_regs_non_essential(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);

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@@ -567,7 +567,6 @@ u32 omap_ddr_clk(void);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
void enable_non_essential_clocks(void);
void scale_vcores(struct vcores_data const *);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
@@ -643,6 +642,7 @@ static inline u8 is_dra7xx(void)
/* DRA7XX */
#define DRA752_ES1_0 0x07520100
#define DRA752_ES1_1 0x07520110
/*
* SRAM scratch space entries