From 93d98383382d4911241b8e8f947f08f6fdd8b569 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 15 Apr 2024 09:55:33 +0200 Subject: [PATCH 01/21] xilinx: zynqmp: Clean up xilinx_zynqmp.h Options are moving to Kconfig by running sed and comments are staying in that's why do clean up and remove useless comments. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fa117ac482591d3d5957af54fe99e6acc89972e3.1713167731.git.michal.simek@amd.com --- include/configs/xilinx_zynqmp.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f76b3c6b163..de0db7bb63f 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -42,8 +42,6 @@ # define PARTS_DEFAULT #endif -/* Console I/O Buffer Size */ - /* Ethernet driver */ #define ENV_MEM_LAYOUT_SETTINGS \ @@ -201,10 +199,6 @@ # define CFG_SYS_SPI_ARGS_SIZE 0xa0000 #endif -/* u-boot is like dtb */ - -/* ATF is my kernel image */ - #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" #endif From 5db5b7e2a33605e08aae13a638a97f717aedec6a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 11 Apr 2024 08:04:16 +0200 Subject: [PATCH 02/21] xilinx: Enable NVMEM framework for all platforms Boards which have for example MAC address in eeprom but not in Xilinx format (legacy or FRU) could reference it via nvmem cells. For example: &gem0 { nvmem-cells = <&mac>; nvmem-cell-names = "mac-address"; }; &eeprom { #address-cells = <1>; #size-cells = <1>; mac: mac-address@f0 { reg = <0xf0 6>; }; }; For getting it work above DT changes are required but also CONFIG_NVMEM should be enabled. That's why enable it by default in generic defconfigs to be able to use it directly by changing DT only. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9c8ee7a4c7a16367438a92a4c9581bac9d968f84.1712815454.git.michal.simek@amd.com --- configs/xilinx_versal_net_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 4207974dbdd..73b2e7ad953 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -80,6 +80,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MAILBOX=y CONFIG_ZYNQMP_IPI=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 06c192ce9d0..b986eda7370 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -83,6 +83,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MAILBOX=y CONFIG_ZYNQMP_IPI=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index f30fbdf3f64..9be904fd301 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -107,6 +107,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_I2C_EEPROM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 89187972fec..a5cdb5ca244 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -147,6 +147,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y From 7abd4357a493aaf829214e893b78c941be4ff959 Mon Sep 17 00:00:00 2001 From: Charlie Johnston Date: Wed, 10 Apr 2024 12:50:08 -0700 Subject: [PATCH 03/21] board: zynqmp: Move zynqmp commands from board/ to arch/ The zynqmp cmds.c is currently tied to the board but the commands contained within are more closely tied to the architecture. To allow usage of those commands when the architecture is ZynqMP but the board is not, this change moves the cmds into the arch/ tree. The source file is renamed to zynqmp.c to reflect the command name as well. Signed-off-by: Charlie Johnston Link: https://lore.kernel.org/r/20240410195008.405061-2-charlie.johnston@loftorbital.com Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/Kconfig | 13 ++++++++++++- arch/arm/mach-zynqmp/Makefile | 4 ++++ .../cmds.c => arch/arm/mach-zynqmp/zynqmp.c | 0 board/xilinx/zynqmp/Kconfig | 19 ------------------- board/xilinx/zynqmp/Makefile | 4 ---- 5 files changed, 16 insertions(+), 24 deletions(-) rename board/xilinx/zynqmp/cmds.c => arch/arm/mach-zynqmp/zynqmp.c (100%) delete mode 100644 board/xilinx/zynqmp/Kconfig diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 0d2238ace1e..aea13622b68 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -189,7 +189,18 @@ config SD1_LSHFT_MODE endchoice +config CMD_ZYNQMP + bool "Enable ZynqMP specific commands" + depends on ZYNQMP_FIRMWARE + default y + help + Enable ZynqMP specific commands like "zynqmp secure" + which is used for zynqmp secure image verification. + The secure image is a xilinx specific BOOT.BIN with + either authentication or encryption or both encryption + and authentication feature enabled while generating + BOOT.BIN using Xilinx bootgen tool. + source "board/xilinx/Kconfig" -source "board/xilinx/zynqmp/Kconfig" endif diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 8f897a37d14..38be1627eeb 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -8,3 +8,7 @@ obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_CMD_ZYNQMP) += zynqmp.o +endif # !CONFIG_SPL_BUILD diff --git a/board/xilinx/zynqmp/cmds.c b/arch/arm/mach-zynqmp/zynqmp.c similarity index 100% rename from board/xilinx/zynqmp/cmds.c rename to arch/arm/mach-zynqmp/zynqmp.c diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig deleted file mode 100644 index ffa2f0215d4..00000000000 --- a/board/xilinx/zynqmp/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2018, Xilinx, Inc. -# -# SPDX-License-Identifier: GPL-2.0 - -if ARCH_ZYNQMP - -config CMD_ZYNQMP - bool "Enable ZynqMP specific commands" - depends on ZYNQMP_FIRMWARE - default y - help - Enable ZynqMP specific commands like "zynqmp secure" - which is used for zynqmp secure image verification. - The secure image is a xilinx specific BOOT.BIN with - either authentication or encryption or both encryption - and authentication feature enabled while generating - BOOT.BIN using Xilinx bootgen tool. - -endif diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 204e4fadf0e..9ab50eca400 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -40,10 +40,6 @@ $(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_C endif endif -ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_CMD_ZYNQMP) += cmds.o -endif - # Suppress "warning: function declaration isn't a prototype" CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes From 11716acde9a73c24f1d48869ccefcd564044fab0 Mon Sep 17 00:00:00 2001 From: "Simek, Michal" Date: Wed, 17 Apr 2024 20:06:13 -1200 Subject: [PATCH 04/21] sdhci: zynq: Fix tap delay for SD on Versal NET I can't see any way how tap delays are setup on Versal NET platform because xlnx,versal-8.9a compatible string is also used there but driver is not letting to setup tap delays. Not sure if versal_iclk_phases[] is also valid for Versal NET but the patch is made to investigate it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e535cfc1a59b5146a5c9a3ab389dc770de80440c.1713427490.git.michal.simek@amd.com --- drivers/mmc/zynq_sdhci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 898be5a0913..8a83adef434 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -865,7 +865,8 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase); if (ret) return ret; - } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) && + } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || + IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) && device_is_compatible(dev, "xlnx,versal-8.9a")) { ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase); if (ret) @@ -941,7 +942,8 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) } } - if (IS_ENABLED(CONFIG_ARCH_VERSAL) && + if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || + IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) && device_is_compatible(dev, "xlnx,versal-8.9a")) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_iclk_phases[i]; From 86c46b99a0e96a7281c153ca78c8e8890967997f Mon Sep 17 00:00:00 2001 From: Kory Maincent Date: Wed, 29 May 2024 12:01:06 +0200 Subject: [PATCH 05/21] xilinx: zynqmp: Allow multiboot environment write even in saved environment Once the environment was saved, the current multiboot image information became unreachable. When dealing with firmware updates, this information is necessary alongside the saved environment to know the booted image. Move the multiboot environment set operation before the saved environment check to ensure this information is always available. Signed-off-by: Kory Maincent Link: https://lore.kernel.org/r/20240529100107.137159-1-kory.maincent@bootlin.com Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index c4050af2a5a..63cc6b862e9 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -519,6 +519,10 @@ int board_late_init(void) usb_ether_init(); #endif + multiboot = multi_boot(); + if (multiboot >= 0) + env_set_hex("multiboot", multiboot); + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); return 0; @@ -531,10 +535,6 @@ int board_late_init(void) if (ret) return ret; - multiboot = multi_boot(); - if (multiboot >= 0) - env_set_hex("multiboot", multiboot); - if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) { ret = boot_targets_setup(); if (ret) From 52ef6a9cb88f3202871d14e68980ad102d9dc492 Mon Sep 17 00:00:00 2001 From: Lukas Funke Date: Wed, 27 Mar 2024 13:11:52 +0100 Subject: [PATCH 06/21] spl: Introduce SoC specific init function Some architectures use spl_board_init() in their SoC specific implementation. Board developers should be able to add board specific implementation via spl_board_init(). Hence, introduce a spl_soc_init() method which is called right before spl_board_init() for SoC specific implementation. Signed-off-by: Lukas Funke Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20240327121153.2455126-2-lukas.funke-oss@weidmueller.com Signed-off-by: Michal Simek --- common/spl/Kconfig | 7 +++++++ common/spl/spl.c | 3 +++ include/spl.h | 8 ++++++++ 3 files changed, 18 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 46bacad2d81..0f7797b3a6a 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -272,6 +272,13 @@ config SPL_TEXT_BASE help The address in memory that SPL will be running from. +config SPL_SOC_INIT + bool "Call SoC-specific initialization in SPL" + help + If this option is enabled, U-Boot will call the function + spl_soc_init() from board_init_r(). This function should be + provided by the SoC vendor. + config SPL_BOARD_INIT bool "Call board-specific initialization in SPL" help diff --git a/common/spl/spl.c b/common/spl/spl.c index 9a879e9fb10..7794ddccade 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -710,6 +710,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2) } } + if (CONFIG_IS_ENABLED(SOC_INIT)) + spl_soc_init(); + if (CONFIG_IS_ENABLED(BOARD_INIT)) spl_board_init(); diff --git a/include/spl.h b/include/spl.h index 043875f10f4..5dfdf778d2d 100644 --- a/include/spl.h +++ b/include/spl.h @@ -816,6 +816,14 @@ int spl_early_init(void); */ int spl_init(void); +/* + * spl_soc_init() - Do architecture-specific init in SPL + * + * If SPL_SOC_INIT is enabled, this is called from board_init_r() before + * jumping to the next phase. + */ +void spl_soc_init(void); + /* * spl_board_init() - Do board-specific init in SPL * From 881e04170a07a5cf9679b9bf42aee4a3928bcac6 Mon Sep 17 00:00:00 2001 From: Lukas Funke Date: Wed, 27 Mar 2024 13:11:53 +0100 Subject: [PATCH 07/21] arm64: zynq(mp): Rename spl_board_init() to spl_soc_init() Rename spl_board_init() to spl_soc_init(). SoC specific implementation should be separated from board specific implementation in order to be extended by board developers. Signed-off-by: Lukas Funke Acked-by: Michal Simek Link: https://lore.kernel.org/r/20240327121153.2455126-3-lukas.funke-oss@weidmueller.com Signed-off-by: Michal Simek --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-zynq/spl.c | 4 ++-- arch/arm/mach-zynqmp/spl.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 39ad03acd2e..6d9a4c993c3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1272,7 +1272,7 @@ config ARCH_ZYNQ select OF_CONTROL select MTD select SPI - select SPL_BOARD_INIT if SPL + select SPL_SOC_INIT if SPL select SPL_CLK if SPL select SPL_DM if SPL select SPL_DM_SPI if SPL @@ -1315,7 +1315,7 @@ config ARCH_ZYNQMP imply FIRMWARE select GICV2 select OF_CONTROL - select SPL_BOARD_INIT if SPL + select SPL_SOC_INIT if SPL select SPL_CLK if SPL select SPL_DM if SPL select SPL_DM_SPI if SPI && SPL_DM diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 8ef12ed65ce..dc964dc2f9f 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -31,8 +31,8 @@ void board_init_f(ulong dummy) arch_cpu_init(); } -#ifdef CONFIG_SPL_BOARD_INIT -void spl_board_init(void) +#ifdef CONFIG_SPL_SOC_INIT +void spl_soc_init(void) { preloader_console_init(); #if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 6b67245f348..4a2d240abbb 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -56,8 +56,8 @@ static void ps_mode_reset(ulong mode) # define MODE_RESET PS_MODE1 #endif -#ifdef CONFIG_SPL_BOARD_INIT -void spl_board_init(void) +#ifdef CONFIG_SPL_SOC_INIT +void spl_soc_init(void) { preloader_console_init(); ps_mode_reset(MODE_RESET); From fd5e18db0aedb7bc34b9c1c1ef20e653fd86cb6c Mon Sep 17 00:00:00 2001 From: Prasad Kummari Date: Wed, 8 May 2024 10:57:50 +0530 Subject: [PATCH 08/21] mtd: spi-nor: Add SPI_NOR_OCTAL_READ flag for mx66uw2g345gx0 flash part Added SPI_NOR_OCTAL_READ flag for Macronix mx66uw2g345gx0 2Gb(256MB) NOR Flash memory. Initial testing was conducted on the Versal NET board using SDR mode, which included basic erase, write, and read-back operations. Signed-off-by: Prasad Kummari Link: https://lore.kernel.org/r/20240508052749.214286-1-prasad.kummari@amd.com Signed-off-by: Michal Simek --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 684206ea07d..2206d734810 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -274,7 +274,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, - { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_READ) }, { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, From 454f948ff4828ebd5361e9976a8c51087d7cfab1 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 10 May 2024 08:22:38 +0200 Subject: [PATCH 09/21] xilinx: versal: Do not prioritize boot device if driver is not enabled SOC can boot out of the device which is not accessible from APU and running this is detected as a warning, as the device is not accessible.For example getting below warning when the boot mode is OSPI and OSPI is not enabled in device tree. Invalid bus 0 (err=-19) Failed to initialize SPI flash at 0:0 (error -19) Ignoring the prioritization of the boot device which driver is not enabled and continue with the default boot_targets. Recommendation is to use custom boot_targets via environment file as is done for example for Kria via zynqmp_kria.env file. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8b7cca5c7b84cb4854104e0c48f8aa63c4ec5ace.1715322156.git.michal.simek@amd.com --- board/xilinx/versal/board.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 77ba783501e..39474674cca 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -150,14 +150,29 @@ static int boot_targets_setup(void) break; case QSPI_MODE_24BIT: puts("QSPI_MODE_24\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } mode = "xspi0"; break; case QSPI_MODE_32BIT: puts("QSPI_MODE_32\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } mode = "xspi0"; break; case OSPI_MODE: puts("OSPI_MODE\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1010000", &dev)) { + debug("OSPI driver for OSPI device is not present\n"); + break; + } mode = "xspi0"; break; case EMMC_MODE: From efff3976e3a68c922bb7f7730e2c15ead442e60d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 30 May 2024 12:39:23 +0200 Subject: [PATCH 10/21] arm64: zynqmp: Update rproc node remoteproc node should be updated to be aligned with the latest dt-schema. Reviewed-by: Tanmay Shah Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d8247a46f486a612f85767de9b832ad33fa980fe.1717065556.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 67 +++++++++++++++++-- include/dt-bindings/power/xlnx-zynqmp-power.h | 17 ++--- 2 files changed, 68 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 53a606c340a..34f592c1a85 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -314,19 +314,76 @@ ranges; }; - remoteproc { + rproc_lockstep: remoteproc@ffe00000 { compatible = "xlnx,zynqmp-r5fss"; xlnx,cluster-mode = <1>; + xlnx,tcm-mode = <1>; - r5f-0 { + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, + <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; + + r5f@0 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_0>; + reg = <0x0 0x0 0x0 0x10000>, + <0x0 0x20000 0x0 0x10000>, + <0x0 0x10000 0x0 0x10000>, + <0x0 0x30000 0x0 0x10000>; + reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; memory-region = <&rproc_0_fw_image>; }; - r5f-1 { + r5f@1 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_1>; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>; + }; + }; + + rproc_split: remoteproc-split@ffe00000 { + status = "disabled"; + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <0>; + xlnx,tcm-mode = <0>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; memory-region = <&rproc_1_fw_image>; }; }; diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h index e7eb0960480..618024cbb20 100644 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -6,16 +6,12 @@ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H -#define PD_RPU_0 6 -#define PD_RPU_1 7 -#define PD_OCM_BANK_0 11 -#define PD_OCM_BANK_1 12 -#define PD_OCM_BANK_2 13 -#define PD_OCM_BANK_3 14 -#define PD_TCM_BANK_0 15 -#define PD_TCM_BANK_1 16 -#define PD_TCM_BANK_2 17 -#define PD_TCM_BANK_3 18 +#define PD_RPU_0 7 +#define PD_RPU_1 8 +#define PD_R5_0_ATCM 15 +#define PD_R5_0_BTCM 16 +#define PD_R5_1_ATCM 17 +#define PD_R5_1_BTCM 18 #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 @@ -45,6 +41,5 @@ #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 -#define PD_PL 69 #endif From 40f5046c221a7b2719c49b51acefe12914b213e5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 29 May 2024 16:47:58 +0200 Subject: [PATCH 11/21] arm64: versal2: Add support for AMD Versal Gen 2 Add support for AMD Versal Gen 2. SoC is based on Cortex-a78ae 4 cluster/2 cpu core each. A lot of IPs are shared with previous families. There are couple of new IP blocks where the most interesting from user point of view is UFS. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/bc2b70831ce1031bd0fac32357bff84936e1310f.1716994063.git.michal.simek@amd.com --- arch/arm/Kconfig | 14 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/amd-versal2-virt.dts | 11 + arch/arm/mach-versal2/Kconfig | 55 +++ arch/arm/mach-versal2/Makefile | 10 + arch/arm/mach-versal2/clk.c | 34 ++ arch/arm/mach-versal2/cpu.c | 93 +++++ arch/arm/mach-versal2/include/mach/hardware.h | 97 +++++ .../arm/mach-versal2/include/mach/sys_proto.h | 9 + board/amd/common | 1 + board/amd/versal2/Kconfig | 16 + board/amd/versal2/MAINTAINERS | 7 + board/amd/versal2/Makefile | 11 + board/amd/versal2/board.c | 343 ++++++++++++++++++ board/amd/versal2/cmds.c | 81 +++++ board/xilinx/Kconfig | 6 +- configs/amd_versal2_virt_defconfig | 145 ++++++++ drivers/gpio/Kconfig | 2 +- drivers/mailbox/Kconfig | 2 +- env/Kconfig | 6 +- include/configs/amd_versal2.h | 143 ++++++++ 22 files changed, 1081 insertions(+), 8 deletions(-) create mode 100644 arch/arm/dts/amd-versal2-virt.dts create mode 100644 arch/arm/mach-versal2/Kconfig create mode 100644 arch/arm/mach-versal2/Makefile create mode 100644 arch/arm/mach-versal2/clk.c create mode 100644 arch/arm/mach-versal2/cpu.c create mode 100644 arch/arm/mach-versal2/include/mach/hardware.h create mode 100644 arch/arm/mach-versal2/include/mach/sys_proto.h create mode 120000 board/amd/common create mode 100644 board/amd/versal2/Kconfig create mode 100644 board/amd/versal2/MAINTAINERS create mode 100644 board/amd/versal2/Makefile create mode 100644 board/amd/versal2/board.c create mode 100644 board/amd/versal2/cmds.c create mode 100644 configs/amd_versal2_virt_defconfig create mode 100644 include/configs/amd_versal2.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6d9a4c993c3..db692b2d215 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1235,6 +1235,18 @@ config ARCH_VERSAL imply BOARD_LATE_INIT imply ENV_VARS_UBOOT_RUNTIME_CONFIG +config ARCH_VERSAL2 + bool "Support AMD Versal Gen 2 Platform" + select ARM64 + select CLK + select DM + select DM_MMC if MMC + select DM_SERIAL + select OF_CONTROL + imply BOARD_LATE_INIT + imply ENV_VARS_UBOOT_RUNTIME_CONFIG + imply ZYNQMP_FIRMWARE + config ARCH_VERSAL_NET bool "Support Xilinx Versal NET Platform" select ARM64 @@ -2317,6 +2329,8 @@ source "arch/arm/mach-zynqmp/Kconfig" source "arch/arm/mach-versal/Kconfig" +source "arch/arm/mach-versal2/Kconfig" + source "arch/arm/mach-versal-net/Kconfig" source "arch/arm/mach-zynqmp-r5/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 734c6d69926..dbeedbe544b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -90,6 +90,7 @@ machine-$(CONFIG_ARCH_OCTEONTX) += octeontx machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2 machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSAL) += versal +machine-$(CONFIG_ARCH_VERSAL2) += versal2 machine-$(CONFIG_ARCH_VERSAL_NET) += versal-net machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cef42ab53af..14e851b900c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -341,6 +341,8 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini-qspi-x2-single.dtb \ versal-mini-qspi-x2-stacked.dtb \ xilinx-versal-virt.dtb +dtb-$(CONFIG_ARCH_VERSAL2) += \ + amd-versal2-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ versal-net-mini-emmc.dtb \ diff --git a/arch/arm/dts/amd-versal2-virt.dts b/arch/arm/dts/amd-versal2-virt.dts new file mode 100644 index 00000000000..3b6cbbac582 --- /dev/null +++ b/arch/arm/dts/amd-versal2-virt.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Empty device tree for amd-versal2-virt board + * + * Copyright (C) 2024, Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +/ { +}; diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig new file mode 100644 index 00000000000..3f18e3351aa --- /dev/null +++ b/arch/arm/mach-versal2/Kconfig @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 + +if ARCH_VERSAL2 + +config SYS_BOARD + string "Board name" + default "versal2" + +config SYS_VENDOR + string "Vendor name" + default "amd" + +config SYS_SOC + default "versal2" + +config SYS_CONFIG_NAME + string "Board configuration name" + default "amd_versal2" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. + +config COUNTER_FREQUENCY + int "Timer clock frequency" + default 0 + help + Setup time clock frequency for certain platform + +config IOU_SWITCH_DIVISOR0 + hex "IOU switch divisor0" + default 0x20 + help + Setup time clock divisor for input clock. + +config SYS_MEM_RSVD_FOR_MMU + bool "Reserve memory for MMU Table" + help + If defined this option is used to setup different space for + MMU table than the one which will be allocated during + relocation. + +config GICV3 + def_bool y + +config SYS_MALLOC_LEN + default 0x2000000 + +config ZYNQ_SDHCI_MAX_FREQ + default 200000000 + +source "board/xilinx/Kconfig" +source "board/amd/versal2/Kconfig" + +endif diff --git a/arch/arm/mach-versal2/Makefile b/arch/arm/mach-versal2/Makefile new file mode 100644 index 00000000000..96497b1dfd0 --- /dev/null +++ b/arch/arm/mach-versal2/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2021 - 2022, Xilinx, Inc. +# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. +# +# Michal Simek +# + +obj-y += clk.o +obj-y += cpu.o diff --git a/arch/arm/mach-versal2/clk.c b/arch/arm/mach-versal2/clk.c new file mode 100644 index 00000000000..e73ae9af076 --- /dev/null +++ b/arch/arm/mach-versal2/clk.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CLOCKS +/** + * set_cpu_clk_info - Initialize clock framework + * + * Return: 0 always. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + gd->cpu_clk = get_tbclk(); + + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + gd->bd->bi_dsp_freq = 0; + + return 0; +} +#endif diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c new file mode 100644 index 00000000000..2dfcadb369e --- /dev/null +++ b/arch/arm/mach-versal2/cpu.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define VERSAL2_MEM_MAP_USED 5 + +#define DRAM_BANKS CONFIG_NR_DRAM_BANKS + +/* +1 is end of list which needs to be empty */ +#define VERSAL2_MEM_MAP_MAX (VERSAL2_MEM_MAP_USED + DRAM_BANKS + 1) + +static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x70000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x0fe00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x600000000UL, + .phys = 0x600000000UL, + .size = 0x800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe00000000UL, + .phys = 0xe00000000UL, + .size = 0xf200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + } +}; + +void mem_map_fill(void) +{ + int banks = VERSAL2_MEM_MAP_USED; + + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + /* Zero size means no more DDR that's this is end */ + if (!gd->bd->bi_dram[i].size) + break; + + versal2_mem_map[banks].virt = gd->bd->bi_dram[i].start; + versal2_mem_map[banks].phys = gd->bd->bi_dram[i].start; + versal2_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + banks = banks + 1; + } +} + +struct mm_region *mem_map = versal2_mem_map; + +u64 get_page_table_size(void) +{ + return 0x14000; +} + +U_BOOT_DRVINFO(soc_amd_versal2) = { + .name = "soc_amd_versal2", +}; diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h new file mode 100644 index 00000000000..42e3061a0ae --- /dev/null +++ b/arch/arm/mach-versal2/include/mach/hardware.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + */ + +#ifndef __ASSEMBLY__ +#include +#endif + +struct crlapb_regs { + u32 reserved0[67]; + u32 cpu_r5_ctrl; + u32 reserved; + u32 iou_switch_ctrl; /* 0x114 */ + u32 reserved1[13]; + u32 timestamp_ref_ctrl; /* 0x14c */ + u32 reserved3[108]; + u32 rst_cpu_r5; + u32 reserved2[17]; + u32 rst_timestamp; /* 0x348 */ +}; + +struct iou_scntrs_regs { + u32 counter_control_register; /* 0x0 */ + u32 reserved0[7]; + u32 base_frequency_id_register; /* 0x20 */ +}; + +struct crp_regs { + u32 reserved0[128]; + u32 boot_mode_usr; /* 0x200 */ +}; + +#define VERSAL2_CRL_APB_BASEADDR 0xEB5E0000 +#define VERSAL2_CRP_BASEADDR 0xF1260000 +#define VERSAL2_IOU_SCNTR_SECURE 0xEC920000 + +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25) +#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25) +#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define IOU_SCNTRS_CONTROL_EN 1 + +#define crlapb_base ((struct crlapb_regs *)VERSAL2_CRL_APB_BASEADDR) +#define crp_base ((struct crp_regs *)VERSAL2_CRP_BASEADDR) +#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL2_IOU_SCNTR_SECURE) + +#define PMC_TAP 0xF11A0000 + +#define PMC_TAP_IDCODE (PMC_TAP + 0) +#define PMC_TAP_VERSION (PMC_TAP + 0x4) +# define PMC_VERSION_MASK GENMASK(7, 0) +# define PS_VERSION_MASK GENMASK(15, 8) +# define PS_VERSION_PRODUCTION 0x20 +# define RTL_VERSION_MASK GENMASK(23, 16) +# define PLATFORM_MASK GENMASK(27, 24) +# define PLATFORM_VERSION_MASK GENMASK(31, 28) +#define PMC_TAP_USERCODE (PMC_TAP + 0x8) + +/* Bootmode setting values */ +#define BOOT_MODES_MASK 0x0000000F +#define QSPI_MODE_24BIT 0x00000001 +#define QSPI_MODE_32BIT 0x00000002 +#define SD_MODE 0x00000003 /* sd 0 */ +#define SD_MODE1 0x00000005 /* sd 1 */ +#define EMMC_MODE 0x00000006 +#define USB_MODE 0x00000007 +#define OSPI_MODE 0x00000008 +#define SELECTMAP_MODE 0x0000000A +#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ +#define JTAG_MODE 0x00000000 +#define BOOT_MODE_USE_ALT 0x100 +#define BOOT_MODE_ALT_SHIFT 12 + +enum versal2_platform { + VERSAL2_SILICON = 0, + VERSAL2_SPP = 1, + VERSAL2_EMU = 2, + VERSAL2_QEMU = 3, + VERSAL2_SPP_MMD = 5, + VERSAL2_EMU_MMD = 6, +}; + +#define VERSAL2_SLCR_BASEADDR 0xF1060000 +#define VERSAL_AXI_MUX_SEL (VERSAL2_SLCR_BASEADDR + 0x504) +#define VERSAL_OSPI_LINEAR_MODE BIT(1) + +#define FLASH_RESET_GPIO 0xc +#define WPROT_CRP 0xF126001C +#define RST_GPIO 0xF1260318 +#define WPROT_LPD_MIO 0xFF080728 +#define WPROT_PMC_MIO 0xF1060828 +#define BOOT_MODE_DIR 0xF1020204 +#define BOOT_MODE_OUT 0xF1020208 +#define MIO_PIN_12 0xF1060030 +#define BANK0_OUTPUT 0xF1020040 +#define BANK0_TRI 0xF1060200 diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h new file mode 100644 index 00000000000..7b1726a7ef4 --- /dev/null +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + */ + +#include + +void mem_map_fill(void); diff --git a/board/amd/common b/board/amd/common new file mode 120000 index 00000000000..cd4d172974b --- /dev/null +++ b/board/amd/common @@ -0,0 +1 @@ +../xilinx/common/ \ No newline at end of file diff --git a/board/amd/versal2/Kconfig b/board/amd/versal2/Kconfig new file mode 100644 index 00000000000..ab46af6935e --- /dev/null +++ b/board/amd/versal2/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020 - 2022, Xilinx, Inc. +# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. +# +if ARCH_VERSAL2 + +config CMD_VERSAL2 + bool "Enable Versal Gen 2 specific commands" + default y + depends on ZYNQMP_FIRMWARE + help + Select this to enable AMD Versal Gen 2 specific commands. + Commands like versal2 loadpdi are enabled by this. + +endif diff --git a/board/amd/versal2/MAINTAINERS b/board/amd/versal2/MAINTAINERS new file mode 100644 index 00000000000..af7913d8db3 --- /dev/null +++ b/board/amd/versal2/MAINTAINERS @@ -0,0 +1,7 @@ +XILINX_VERSAL2 BOARDS +M: Michal Simek +S: Maintained +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git +F: arch/arm/dts/versal2* +F: board/amd/ +F: configs/amd* diff --git a/board/amd/versal2/Makefile b/board/amd/versal2/Makefile new file mode 100644 index 00000000000..3a044517f0c --- /dev/null +++ b/board/amd/versal2/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2021 - 2022, Xilinx, Inc. +# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. +# +# Michal Simek +# + +obj-y := board.o + +obj-$(CONFIG_CMD_VERSAL2) += cmds.o diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c new file mode 100644 index 00000000000..5651d516a9e --- /dev/null +++ b/board/amd/versal2/board.c @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../xilinx/common/board.h" + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + printf("EL Level:\tEL%d\n", current_el()); + + return 0; +} + +static u32 platform_id, platform_version; + +char *soc_name_decode(void) +{ + char *name, *platform_name; + + switch (platform_id) { + case VERSAL2_SPP: + platform_name = "spp"; + break; + case VERSAL2_EMU: + platform_name = "emu"; + break; + case VERSAL2_SPP_MMD: + platform_name = "spp-mmd"; + break; + case VERSAL2_EMU_MMD: + platform_name = "emu-mmd"; + break; + case VERSAL2_QEMU: + platform_name = "qemu"; + break; + default: + return NULL; + } + + /* + * --rev. are 6 chars + * max platform name is qemu which is 4 chars + * platform version number are 1+1 + * Plus 1 char for \n + */ + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); + if (!name) + return NULL; + + sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD, + platform_name, platform_version / 10, + platform_version % 10, current_el()); + + return name; +} + +bool soc_detection(void) +{ + u32 version, ps_version; + + version = readl(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + ps_version = FIELD_GET(PS_VERSION_MASK, version); + + debug("idcode %x, version %x, usercode %x\n", + readl(PMC_TAP_IDCODE), version, + readl(PMC_TAP_USERCODE)); + + debug("pmc_ver %lx, ps version %x, rtl version %lx\n", + FIELD_GET(PMC_VERSION_MASK, version), + ps_version, + FIELD_GET(RTL_VERSION_MASK, version)); + + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + debug("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10, platform_version % 10); + + return true; +} + +int board_early_init_r(void) +{ + u32 val; + + if (current_el() != 3) + return 0; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); + + return 0; +} + +static u8 versal_net_get_bootmode(void) +{ + u8 bootmode; + u32 reg = 0; + + reg = readl(&crp_base->boot_mode_usr); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + return bootmode; +} + +static int boot_targets_setup(void) +{ + u8 bootmode; + struct udevice *dev; + int bootseq = -1; + int bootseq_len = 0; + int env_targets_len = 0; + const char *mode = NULL; + char *new_targets; + char *env_targets; + + bootmode = versal_net_get_bootmode(); + + puts("Bootmode: "); + switch (bootmode) { + case USB_MODE: + puts("USB_MODE\n"); + mode = "usb_dfu0 usb_dfu1"; + break; + case JTAG_MODE: + puts("JTAG_MODE\n"); + mode = "jtag pxe dhcp"; + break; + case QSPI_MODE_24BIT: + puts("QSPI_MODE_24\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } + mode = "xspi"; + bootseq = dev_seq(dev); + break; + case QSPI_MODE_32BIT: + puts("QSPI_MODE_32\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } + mode = "xspi"; + bootseq = dev_seq(dev); + break; + case OSPI_MODE: + puts("OSPI_MODE\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1010000", &dev)) { + debug("OSPI driver for OSPI device is not present\n"); + break; + } + mode = "xspi"; + bootseq = dev_seq(dev); + break; + case EMMC_MODE: + puts("EMMC_MODE\n"); + mode = "mmc"; + bootseq = dev_seq(dev); + break; + case SELECTMAP_MODE: + puts("SELECTMAP_MODE\n"); + break; + case SD_MODE: + puts("SD_MODE\n"); + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1040000", &dev)) { + debug("SD0 driver for SD0 device is not present\n"); + break; + } + debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev)); + + mode = "mmc"; + bootseq = dev_seq(dev); + break; + case SD1_LSHFT_MODE: + puts("LVL_SHFT_"); + fallthrough; + case SD_MODE1: + puts("SD_MODE1\n"); + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1050000", &dev)) { + debug("SD1 driver for SD1 device is not present\n"); + break; + } + debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev)); + + mode = "mmc"; + bootseq = dev_seq(dev); + break; + default: + printf("Invalid Boot Mode:0x%x\n", bootmode); + break; + } + + if (mode) { + if (bootseq >= 0) { + bootseq_len = snprintf(NULL, 0, "%i", bootseq); + debug("Bootseq len: %x\n", bootseq_len); + } + + /* + * One terminating char + one byte for space between mode + * and default boot_targets + */ + env_targets = env_get("boot_targets"); + if (env_targets) + env_targets_len = strlen(env_targets); + + new_targets = calloc(1, strlen(mode) + env_targets_len + 2 + + bootseq_len); + if (!new_targets) + return -ENOMEM; + + if (bootseq >= 0) + sprintf(new_targets, "%s%x %s", mode, bootseq, + env_targets ? env_targets : ""); + else + sprintf(new_targets, "%s %s", mode, + env_targets ? env_targets : ""); + + env_set("boot_targets", new_targets); + } + + return 0; +} + +int board_late_init(void) +{ + int ret; + + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { + debug("Saved variables - Skipping\n"); + return 0; + } + + if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) + return 0; + + if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) { + ret = boot_targets_setup(); + if (ret) + return ret; + } + + return board_late_init_xilinx(); +} + +int dram_init_banksize(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + mem_map_fill(); + + return 0; +} + +int dram_init(void) +{ + int ret; + + if (IS_ENABLED(CONFIG_SYS_MEM_RSVD_FOR_MMU)) + ret = fdtdec_setup_mem_size_base(); + else + ret = fdtdec_setup_mem_size_base_lowest(); + + if (ret) + return -EINVAL; + + return 0; +} + +void reset_cpu(void) +{ +} diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c new file mode 100644 index 00000000000..fbd99918a7f --- /dev/null +++ b/board/amd/versal2/cmds.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * do_versal2_load_pdi - Handle the "versal2 load pdi" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Processes the versal2 load pdi command + * + * Return: return 0 on success, Error value if command fails. + * CMD_RET_USAGE incase of incorrect/missing parameters. + */ +static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 buf_lo, buf_hi; + u32 ret_payload[PAYLOAD_ARG_CNT]; + ulong addr, *pdi_buf; + size_t len; + int ret; + + if (argc != cmdtp->maxargs) { + debug("pdi_load: incorrect parameters passed\n"); + return CMD_RET_USAGE; + } + + addr = simple_strtol(argv[1], NULL, 16); + if (!addr) { + debug("pdi_load: zero pdi_data address\n"); + return CMD_RET_USAGE; + } + + len = hextoul(argv[2], NULL); + if (!len) { + debug("pdi_load: zero size\n"); + return CMD_RET_USAGE; + } + + pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN); + if ((ulong)addr != (ulong)pdi_buf) { + memcpy((void *)pdi_buf, (void *)addr, len); + debug("Pdi addr:0x%lx aligned to 0x%lx\n", + addr, (ulong)pdi_buf); + } + + flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len); + + buf_lo = lower_32_bits((ulong)pdi_buf); + buf_hi = upper_32_bits((ulong)pdi_buf); + + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, + buf_hi, 0, ret_payload); + if (ret) + printf("PDI load failed with err: 0x%08x\n", ret); + + return cmd_process_error(cmdtp, ret); +} + +static char versal2_help_text[] = + "loadpdi addr len - Load pdi image\n" + "load pdi image at ddr address 'addr' with pdi image size 'len'\n" +; + +U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text, + U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, + do_versal2_load_pdi)); diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 5c4ad8f1df9..c7df4ab5781 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -42,7 +42,7 @@ endif config XILINX_OF_BOARD_DTB_ADDR hex "Default DTB pickup address" - default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET + default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0x8000 if MICROBLAZE default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP default 0x23000000 if TARGET_XILINX_MBV @@ -52,10 +52,10 @@ config XILINX_OF_BOARD_DTB_ADDR config BOOT_SCRIPT_OFFSET hex "Boot script offset" - depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE || TARGET_XILINX_MBV + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 || MICROBLAZE || TARGET_XILINX_MBV default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE default 0x3E80000 if ARCH_ZYNQMP - default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET + default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0 if TARGET_XILINX_MBV help Specifies distro boot script offset in NAND/QSPI/NOR flash. diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig new file mode 100644 index 00000000000..5eea07f03f5 --- /dev/null +++ b/configs/amd_versal2_virt_defconfig @@ -0,0 +1,145 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=375000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 +CONFIG_ARCH_VERSAL2=y +CONFIG_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x100000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-virt" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_BASE=0xf1920000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_CMD_FRU=y +CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_DEBUG_UART=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_BOOTM_LEN=0x6400000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=5 +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_SYS_PBSIZE=2073 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CLOCKS=y +CONFIG_SYS_PROMPT="versal2> " +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_UFS=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y +CONFIG_CMD_TPM=y +CONFIG_CMD_SCMI=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_BOARD=y +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_IP_DEFRAG=y +CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_DFU_RAM=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_DM_MAILBOX=y +CONFIG_ZYNQMP_IPI=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_XILINX_AXIEMAC=y +CONFIG_ZYNQ_GEM=y +CONFIG_POWER_DOMAIN=y +CONFIG_RESET_SCMI=y +CONFIG_SCSI=y +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_ARM_DCC=y +CONFIG_PL01X_SERIAL=y +CONFIG_XILINX_UARTLITE=y +CONFIG_SOC_DEVICE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQ_SPI=y +CONFIG_TPM2_TIS_SPI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_THOR=y +CONFIG_UFS=y +CONFIG_CADENCE_UFS=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y +CONFIG_TPM=y diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b050585389b..2c0e244b9e4 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -487,7 +487,7 @@ config MVEBU_GPIO config ZYNQ_GPIO bool "Zynq GPIO driver" depends on DM_GPIO - default y if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL + default y if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL2 help Supports GPIO access on Zynq SoC. diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 47f24e0a02e..67d5ac1a742 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -54,7 +54,7 @@ config K3_SEC_PROXY config ZYNQMP_IPI bool "Xilinx ZynqMP IPI controller support" - depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET) + depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) help This enables support for the Xilinx ZynqMP Inter Processor Interrupt communication controller. diff --git a/env/Kconfig b/env/Kconfig index 9641abe371a..451bab45ea7 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -570,7 +570,7 @@ config ENV_OFFSET default 0xF0000 if ARCH_SUNXI default 0xE0000 if ARCH_ZYNQ default 0x1E00000 if ARCH_ZYNQMP - default 0x7F40000 if ARCH_VERSAL || ARCH_VERSAL_NET + default 0x7F40000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0x0 if ARC default 0x140000 if ARCH_AT91 default 0x260000 if ARCH_OMAP2PLUS @@ -605,7 +605,7 @@ config ENV_SIZE default 0x10000 if ARCH_SUNXI default 0x8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x2000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH - default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET + default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0x4000 if ARC default 0x1f000 help @@ -615,7 +615,7 @@ config ENV_SECT_SIZE hex "Environment Sector-Size" depends on ENV_IS_IN_FLASH || ENV_IS_IN_SPI_FLASH default 0x2000 if ARCH_ROCKCHIP - default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET + default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 default 0x20000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH default 0x10000 if ARCH_SUNXI && ENV_IS_IN_SPI_FLASH diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h new file mode 100644 index 00000000000..6a40bbdf3a7 --- /dev/null +++ b/include/configs/amd_versal2.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for AMD Versal Gen 2 + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * + * Michal Simek + * + * Based on Configuration for Xilinx ZynqMP + */ + +#ifndef __AMD_VERSAL2_H +#define __AMD_VERSAL2_H + +/* FIXME this is causing issue at least on IPP */ +/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xF9000000 +#define GICR_BASE 0xF9060000 + +/* Serial setup */ +#define CFG_SYS_BAUDRATE_TABLE \ + { 4800, 9600, 19200, 38400, 57600, 115200 } + +#if defined(CONFIG_CMD_DFU) +#define DFU_DEFAULT_POLL_TIMEOUT 300 +#define DFU_ALT_INFO_RAM \ + "dfu_ram_info=" \ + "setenv dfu_alt_info " \ + "Image ram 80000 $kernel_size_r\\\\;" \ + "system.dtb ram $fdt_addr_r $fdt_size_r\0" \ + "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ + "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" + +#define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM +#endif + +#if !defined(DFU_ALT_INFO) +# define DFU_ALT_INFO +#endif + +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM) +# define PHY_ANEG_TIMEOUT 20000 +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_addr_r=0x40000000\0" \ + "fdt_size_r=0x400000\0" \ + "pxefile_addr_r=0x10000000\0" \ + "kernel_addr_r=0x18000000\0" \ + "kernel_size_r=0x10000000\0" \ + "kernel_comp_addr_r=0x30000000\0" \ + "kernel_comp_size=0x3C00000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + "script_size_f=0x80000\0" + +#if defined(CONFIG_DISTRO_DEFAULTS) + +#if defined(CONFIG_MMC_SDHCI_ZYNQ) +# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) +#else +# define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL) +# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) func(XSPI, xspi, 1) +# define BOOTENV_DEV_SHARED_XSPI \ + "xspi_boot=sf probe $devnum_xspi:0 0 0 && " \ + "sf read $scriptaddr $script_offset_f $script_size_f && " \ + "echo XSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" +#else +# define BOOT_TARGET_DEVICES_XSPI(func) +# define BOOTENV_DEV_SHARED_XSPI +#endif + +#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "devnum_xspi=" #instance "; run " #devtypel "_boot\0" \ + +#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ + "" + +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + +#define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0) + +#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \ + "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \ + "$script_size_f; dfu 0 ram 0 && " \ + "echo DFU: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo DFU: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \ + "" + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_XSPI(func) \ + BOOT_TARGET_DEVICES_DFU_USB(func) \ + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) + +#include + +#else /* CONFIG_DISTRO_DEFAULTS */ +# define BOOTENV +#endif /* CONFIG_DISTRO_DEFAULTS */ + +/* Initial environment variables */ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV \ + BOOTENV_DEV_SHARED_XSPI \ + DFU_ALT_INFO +#endif + +#endif /* __AMD_VERSAL2_H */ From 96cec1bbc9ed108de3fab582bd8ae26775c01e0b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 29 May 2024 16:47:59 +0200 Subject: [PATCH 12/21] soc: versal2: Add SoC driver for AMD Versal Gen 2 Communication is happening via firmware interface (SMC) or via direct register reading if firmware driver is not available. Also enable it via defconfig. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/22cf9c765e47ab03dbf2b8363e6626e809113432.1716994063.git.michal.simek@amd.com --- configs/amd_versal2_virt_defconfig | 1 + drivers/soc/Kconfig | 8 ++++ drivers/soc/Makefile | 1 + drivers/soc/soc_amd_versal2.c | 77 ++++++++++++++++++++++++++++++ 4 files changed, 87 insertions(+) create mode 100644 drivers/soc/soc_amd_versal2.c diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 5eea07f03f5..8ef86f1f383 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -119,6 +119,7 @@ CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y CONFIG_SOC_DEVICE=y +CONFIG_SOC_AMD_VERSAL2=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_ZYNQ_SPI=y diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 03433bc0e6d..cee506fe474 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,14 @@ config SOC_DEVICE need different parameters or quirks enabled depending on the specific device variant in use. +config SOC_AMD_VERSAL2 + bool "Enable SoC Device ID driver for AMD Versal Gen 2" + depends on SOC_DEVICE && ARCH_VERSAL2 + help + Enable this option to select SoC device id driver for AMD Versal Gen 2. + This allows other drivers to verify the SoC familiy & revision using + matching SoC attributes. + config SOC_DEVICE_TI_K3 depends on SOC_DEVICE && ARCH_K3 bool "Enable SoC Device ID driver for TI K3 SoCs" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 610bf816d40..5ec89a05316 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -2,6 +2,7 @@ # # Makefile for the U-Boot SOC specific device drivers. +obj-$(CONFIG_SOC_AMD_VERSAL2) += soc_amd_versal2.o obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o diff --git a/drivers/soc/soc_amd_versal2.c b/drivers/soc/soc_amd_versal2.c new file mode 100644 index 00000000000..66bcb22b4fa --- /dev/null +++ b/drivers/soc/soc_amd_versal2.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Versal Gen 2 SOC driver + * + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include + +#include + +/* + * v1 -> 0x10 - ES1 + * v2 -> 0x20 - Production + */ +static const char versal2_family[] = "Versal Gen 2"; + +struct soc_amd_versal2_priv { + const char *family; + char revision; +}; + +static int soc_amd_versal2_get_family(struct udevice *dev, char *buf, int size) +{ + struct soc_amd_versal2_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "%s", priv->family); +} + +static int soc_amd_versal2_get_revision(struct udevice *dev, char *buf, int size) +{ + struct soc_amd_versal2_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "v%d", priv->revision); +} + +static const struct soc_ops soc_amd_versal2_ops = { + .get_family = soc_amd_versal2_get_family, + .get_revision = soc_amd_versal2_get_revision, +}; + +static int soc_amd_versal2_probe(struct udevice *dev) +{ + struct soc_amd_versal2_priv *priv = dev_get_priv(dev); + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + priv->family = versal2_family; + + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, + ret_payload); + if (ret) + return ret; + } else { + ret_payload[2] = readl(PMC_TAP_VERSION); + if (!ret_payload[2]) + return -EINVAL; + } + + priv->revision = FIELD_GET(PS_VERSION_MASK, ret_payload[2]); + + return 0; +} + +U_BOOT_DRIVER(soc_amd_versal2) = { + .name = "soc_amd_versal2", + .id = UCLASS_SOC, + .ops = &soc_amd_versal2_ops, + .probe = soc_amd_versal2_probe, + .priv_auto = sizeof(struct soc_amd_versal2_priv), + .flags = DM_FLAG_PRE_RELOC, +}; From 4950a98d14da12335c960c81a62754b667c11300 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 29 May 2024 16:48:00 +0200 Subject: [PATCH 13/21] mmc: versal2: Update zynq_sdhci driver to support AMD Versal Gen 2 Enable tap delay programming for new SoC and also enable it via defconfig. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f07daded9704cbc393657b65a28933c34a8cec25.1716994063.git.michal.simek@amd.com --- configs/amd_versal2_virt_defconfig | 2 ++ drivers/mmc/zynq_sdhci.c | 22 ++++++++++++++-------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 8ef86f1f383..b74e69be28c 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -87,6 +87,8 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 8a83adef434..28d2b456fbf 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -122,7 +122,8 @@ __weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) return 1; } -#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) +#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || \ + defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2) /* Default settings for ZynqMP Clock Phases */ static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}; @@ -156,7 +157,7 @@ static const u8 mode2timing[] = { [MMC_HS_400] = MMC_TIMING_MMC_HS400, }; -#if defined(CONFIG_ARCH_VERSAL_NET) +#if defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2) /** * arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock * @@ -866,7 +867,8 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) if (ret) return ret; } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || - IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) && + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2)) && device_is_compatible(dev, "xlnx,versal-8.9a")) { ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase); if (ret) @@ -875,7 +877,8 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase); if (ret) return ret; - } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && + } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2)) && device_is_compatible(dev, "xlnx,versal-net-emmc")) { if (mmc->clock >= MIN_PHY_CLK_HZ) if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN) @@ -943,7 +946,8 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) } if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || - IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) && + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2)) && device_is_compatible(dev, "xlnx,versal-8.9a")) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_iclk_phases[i]; @@ -951,7 +955,8 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) } } - if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && + if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2)) && device_is_compatible(dev, "xlnx,versal-net-emmc")) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i]; @@ -987,7 +992,7 @@ static const struct sdhci_ops arasan_ops = { .platform_execute_tuning = &arasan_sdhci_execute_tuning, .set_delay = &arasan_sdhci_set_tapdelay, .set_control_reg = &sdhci_set_control_reg, -#if defined(CONFIG_ARCH_VERSAL_NET) +#if defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2) .config_dll = &arasan_sdhci_config_dll, #endif }; @@ -1195,7 +1200,8 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev) priv->host->name = dev->name; -#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) +#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) || \ + defined(CONFIG_ARCH_VERSAL2) priv->host->ops = &arasan_ops; arasan_dt_parse_clk_phases(dev); #endif From 9bf522cd5c521f9304e7d54f0cf97eb6c08a0696 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 29 May 2024 16:48:01 +0200 Subject: [PATCH 14/21] spi: versal2: Enable spi drivers for Versal Gen 2 Enable and update OSPI/QSPI/GQSPI drivers to support Versal Gen 2 SoCs. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/691782470f56f7d49a3204f6757296f2752d4156.1716994063.git.michal.simek@amd.com --- configs/amd_versal2_virt_defconfig | 4 +++- drivers/spi/Kconfig | 2 +- drivers/spi/cadence_qspi.c | 3 ++- drivers/spi/zynqmp_gqspi.c | 6 ++++-- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index b74e69be28c..6e4adddf2c0 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_VERSAL2=y CONFIG_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 -CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-virt" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -124,7 +123,10 @@ CONFIG_SOC_DEVICE=y CONFIG_SOC_AMD_VERSAL2=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 35030ab3556..cd785aefd56 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -156,7 +156,7 @@ config CQSPI_REF_CLK config CADENCE_OSPI_VERSAL bool "Configure Versal OSPI" - depends on (ARCH_VERSAL || ARCH_VERSAL_NET) && CADENCE_QSPI + depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) && CADENCE_QSPI imply DM_GPIO help This option is used to enable Versal OSPI DMA operations which diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 75e52232010..9c466f8695e 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -253,7 +253,8 @@ static int cadence_spi_probe(struct udevice *bus) /* Versal and Versal-NET use spi calibration to set read delay */ if (CONFIG_IS_ENABLED(ARCH_VERSAL) || - CONFIG_IS_ENABLED(ARCH_VERSAL_NET)) + CONFIG_IS_ENABLED(ARCH_VERSAL_NET) || + CONFIG_IS_ENABLED(ARCH_VERSAL2)) if (priv->read_delay >= 0) priv->read_delay = -1; diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 61349a4da53..ae795e50b0a 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -106,7 +106,8 @@ #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 #define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \ - IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \ + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || \ + IS_ENABLED(CONFIG_ARCH_VERSAL2)) ? \ 0xFF180390 : 0xF103003C #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020 #define GQSPI_FREQ_37_5MHZ 37500000 @@ -316,7 +317,8 @@ static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) __func__, clk_rate, baudrateval, reqhz); if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) || - IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) { + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2))) { if (reqhz <= GQSPI_FREQ_40MHZ) { tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << TAP_DLY_BYPASS_LQSPI_RX_SHIFT; From 8ef61c22cd4374e4fcef8278041ec4f69587e394 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 3 Jun 2024 15:09:01 +0200 Subject: [PATCH 15/21] arm64: zynqmp: Setup multiboot register to 0 On Kria when board starts from Image A or Image B partition multiboot register is already setup to that location. When reset command is called board is issuing soft reset which start SW at already used location (offset of multiboot * 32k). But board should continue to run from multiboot offset 0 (start of QSPI) and call early bootloader every reboot that's why clear multiboot register to 0 by default to go that route all the time. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/edaf714a778bdd7447533a77b3455e4fd623f9da.1717420131.git.michal.simek@amd.com --- board/xilinx/zynqmp/zynqmp_kria.env | 1 + 1 file changed, 1 insertion(+) diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index 846eceb0118..69e333c5388 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -65,6 +65,7 @@ kd240_setup=i2c dev 1 && run usb_hub_init;zynqmp pmufw node 33; zynqmp pmufw nod tpm_setup=tpm autostart; board_setup=\ +zynqmp mmio_write 0xFFCA0010 0xfff 0; \ if test ${card1_name} = SCK-KV-G; then run kv260_setup; fi;\ if test ${card1_name} = SCK-KR-G; then run kr260_setup; fi;\ if test ${card1_name} = SCK-KD-G; then run kd240_setup; fi;\ From d67558b358963be5e8e39a80b3d27ba9325df72f Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Tue, 4 Jun 2024 09:38:54 +0100 Subject: [PATCH 16/21] arm64: zynqmp: Enable usb3 for k24 som This patch corrects the mio and pll configuration registers for using usb3 on the kd240 starter kit. Without this patch, the usb3 to sd card bridge does not initialize correctly and u-boot is unable to find the OS located on the kd240 starter kit sd card. In addition, this patch correctly configures mio76 and mio77 as gpio pins which are used as reset gpio pins on the kd240 starter kit. Signed-off-by: Neal Frager Link: https://lore.kernel.org/r/20240604083854.2033917-1-neal.frager@amd.com Signed-off-by: Michal Simek --- .../zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c | 23 ++++++++----------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c index 166e61431ba..274203ffaa3 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c @@ -528,8 +528,8 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U); psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U); psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); @@ -569,21 +569,16 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U); psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000080U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); @@ -591,13 +586,15 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x01000000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x01000000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U); mask_delay(1); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0000U); mask_delay(5); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U); return 1; } From 081f3a19912174018f55c854c7b258cb2d511ce1 Mon Sep 17 00:00:00 2001 From: Lukas Funke Date: Fri, 7 Jun 2024 11:26:08 +0200 Subject: [PATCH 17/21] xilinx: zynqmp: Enable reset_cpu() in SPL This commit enables SPL to reset the CPU via PMU-firmware. The usual reset mechanism requires bl31 to be loaded which may not be the case in SPL. Signed-off-by: Lukas Funke Link: https://lore.kernel.org/r/20240607092608.712996-2-lukas.funke-oss@weidmueller.com Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 63cc6b862e9..b4c15b041cc 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -285,6 +285,18 @@ int dram_init(void) #if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { + if (!IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + log_warning("reset failed: ZYNQMP_FIRMWARE disabled"); + return; + } + + /* In case of !CONFIG_ZYNQMP_FIRMWARE the call to 'xilinx_pm_request()' + * will be removed by the compiler due to the early return. + * If CONFIG_ZYNQMP_FIRMWARE is defined in SPL 'xilinx_pm_request()' + * will send command over IPI and requires pmufw to be present. + */ + xilinx_pm_request(PM_RESET_ASSERT, ZYNQMP_PM_RESET_SOFT, + PM_RESET_ACTION_ASSERT, 0, 0, NULL); } #endif From ee3630f0bc43afddb8730acbfbdcc389dfb2edbc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 6 Jun 2024 16:35:50 +0200 Subject: [PATCH 18/21] arm64: zynqmp: Align #address/size-cells with node zynqmp-mini-nand wasn't aligned with dt binding that's why fix it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/3916fde2e896b8be8863505305118903e0644ab0.1717684544.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-mini-nand.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index 5889d436edb..e08a7840d8e 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -46,8 +46,8 @@ status = "okay"; reg = <0x0 0xff100000 0x1000>; clock-names = "clk_sys", "clk_flash"; - #address-cells = <2>; - #size-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; arasan,has-mdma; num-cs = <2>; nand@0 { From 62a3e4016ab1938b1c2a2639eb772b31e98c25b6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 6 Jun 2024 16:44:54 +0200 Subject: [PATCH 19/21] gpio: Add proper dependency on ZYNQMP_FIRMWARE ZYNQMP_FIRMWARE can be disabled and driver depends on it that's why record this dependency via Kconfig. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c3ca38fbb2f4e6948a5ef95b369015de96259709.1717685091.git.michal.simek@amd.com --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2c0e244b9e4..fcca6941ebf 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -639,7 +639,7 @@ config NOMADIK_GPIO config ZYNQMP_GPIO_MODEPIN bool "ZynqMP gpio modepin" - depends on DM_GPIO + depends on DM_GPIO && ZYNQMP_FIRMWARE help This config enables the ZynqMP gpio modepin driver. ZynqMP modepin driver will set and get the status of PS_MODE pins. These modepins From 37bd12551310e4c63a8d84bd05a98a83cf92105b Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 14 Jun 2024 18:21:10 +0530 Subject: [PATCH 20/21] xilinx: versal-net: Add env redund offset ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env variables is overwriting data at 0 offset, which is wrong. So add default redund env offset ENV_OFFSET_REDUND at 0x7F00000 for Versal NET platform. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20240614125110.23058-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- configs/xilinx_versal_net_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 73b2e7ad953..dd7c558d810 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-net-virt" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y +CONFIG_ENV_OFFSET_REDUND=0x7F00000 CONFIG_CMD_FRU=y CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SYS_MEMTEST_START=0x00000000 From e4a11e984d11cf4bbe55385cbae03c08f27ecd02 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 11 Jun 2024 13:06:58 +0200 Subject: [PATCH 21/21] xilinx: Enable FF-A for all our arm64 SoCs Enable FFA_TRANSPORT which also enable FFA command. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5a850b1558fad0f05c61de82110abe4c0e7fd2e4.1718104009.git.michal.simek@amd.com --- configs/amd_versal2_virt_defconfig | 1 + configs/xilinx_versal_net_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynqmp_kria_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 6e4adddf2c0..2d611f84cd9 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -73,6 +73,7 @@ CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_CLK_CCF=y CONFIG_CLK_SCMI=y CONFIG_DFU_RAM=y +CONFIG_ARM_FFA_TRANSPORT=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index dd7c558d810..377081c92e0 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -73,6 +73,7 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_CLK_VERSAL=y CONFIG_DFU_RAM=y +CONFIG_ARM_FFA_TRANSPORT=y CONFIG_ZYNQ_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index b986eda7370..59fdd30fd83 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -74,6 +74,7 @@ CONFIG_CLK_VERSAL=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_RAM=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 +CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_VERSALPL=y CONFIG_DM_I2C=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 8c6032532a2..3d1cfe850a9 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -134,6 +134,7 @@ CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_GPIO_HOG=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index a5cdb5ca244..a9e65039d3e 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -134,6 +134,7 @@ CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_GPIO_HOG=y