ARM: keystone2: K2G: power-off DSP during boot
The DSPs are powered on by default upon a Power ON reset, and they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E during the boot in u-boot. This is not functional on K2G though. Extend the existing DSP power-off support to the only DSP present on K2G. Do note that the PSC clock domain module id for DSP on K2G differs from that of previous Keystone2 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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@@ -10,7 +10,7 @@
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#ifndef __ASM_ARCH_HARDWARE_K2G_H
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#ifndef __ASM_ARCH_HARDWARE_K2G_H
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#define __ASM_ARCH_HARDWARE_K2G_H
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#define __ASM_ARCH_HARDWARE_K2G_H
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#define KS2_NUM_DSPS 0
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#define KS2_NUM_DSPS 1
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/* Power and Sleep Controller (PSC) Domains */
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/* Power and Sleep Controller (PSC) Domains */
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#define KS2_LPSC_ALWAYSON 0
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#define KS2_LPSC_ALWAYSON 0
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@@ -30,7 +30,10 @@
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#define KS2_LPSC_MCASP 15
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#define KS2_LPSC_MCASP 15
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#define KS2_LPSC_SR 16
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#define KS2_LPSC_SR 16
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#define KS2_LPSC_MSMC 17
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#define KS2_LPSC_MSMC 17
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#define KS2_LPSC_GEM 18
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#ifdef KS2_LPSC_GEM_0
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#undef KS2_LPSC_GEM_0
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#endif
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#define KS2_LPSC_GEM_0 18
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#define KS2_LPSC_ARM 19
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#define KS2_LPSC_ARM 19
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#define KS2_LPSC_ASRC 20
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#define KS2_LPSC_ASRC 20
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#define KS2_LPSC_ICSS 21
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#define KS2_LPSC_ICSS 21
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