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drivers: net: Remove duplicate newlines

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Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
2024-07-20 14:40:45 +02:00
committed by Tom Rini
parent a7dd2d1d6e
commit f3974bec32
32 changed files with 0 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/bcm-sf2-eth-gmac.h
View File

@@ -18,7 +18,6 @@
#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100) #define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188) #define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
#define GMAC_DMA_PTR_OFFSET 0x04 #define GMAC_DMA_PTR_OFFSET 0x04
#define GMAC_DMA_ADDR_LOW_OFFSET 0x08 #define GMAC_DMA_ADDR_LOW_OFFSET 0x08
#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c #define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c

1
drivers/net/bnxt/bnxt.c
View File

@@ -3,7 +3,6 @@
* Copyright 2019-2021 Broadcom. * Copyright 2019-2021 Broadcom.
*/ */
#include <asm/io.h> #include <asm/io.h>
#include <dm.h> #include <dm.h>
#include <linux/delay.h> #include <linux/delay.h>

1
drivers/net/designware.h
View File

@@ -64,7 +64,6 @@ struct eth_mac_regs {
#define MII_REGMSK (0x1F << 6) #define MII_REGMSK (0x1F << 6)
#define MII_ADDRMSK (0x1F << 11) #define MII_ADDRMSK (0x1F << 11)
struct eth_dma_regs { struct eth_dma_regs {
u32 busmode; /* 0x00 */ u32 busmode; /* 0x00 */
u32 txpolldemand; /* 0x04 */ u32 txpolldemand; /* 0x04 */

6
drivers/net/e1000.c
View File

@@ -7,10 +7,8 @@ tested on both gig copper and gig fiber boards
***************************************************************************/ ***************************************************************************/
/******************************************************************************* /*******************************************************************************
Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
Contact Information: Contact Information:
Linux NICS <linux.nics@intel.com> Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
@@ -1742,7 +1740,6 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
switch (hw->mac_type) { switch (hw->mac_type) {
case e1000_igb: /* IGB is cool */ case e1000_igb: /* IGB is cool */
return; return;
@@ -2594,7 +2591,6 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
return ret_val; return ret_val;
} }
} else { } else {
if (hw->mac_type == e1000_ich8lan) { if (hw->mac_type == e1000_ich8lan) {
@@ -5216,7 +5212,6 @@ e1000_configure_tx(struct e1000_hw *hw)
E1000_WRITE_REG(hw, TARC1, tarc); E1000_WRITE_REG(hw, TARC1, tarc);
} }
e1000_config_collision_dist(hw); e1000_config_collision_dist(hw);
/* Setup Transmit Descriptor Settings for eop descriptor */ /* Setup Transmit Descriptor Settings for eop descriptor */
hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
@@ -5227,7 +5222,6 @@ e1000_configure_tx(struct e1000_hw *hw)
else else
hw->txd_cmd |= E1000_TXD_CMD_RS; hw->txd_cmd |= E1000_TXD_CMD_RS;
if (hw->mac_type == e1000_igb) { if (hw->mac_type == e1000_igb) {
E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);

4
drivers/net/e1000.h
View File

@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-License-Identifier: GPL-2.0+ */
/******************************************************************************* /*******************************************************************************
Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
Copyright 2011 Freescale Semiconductor, Inc. Copyright 2011 Freescale Semiconductor, Inc.
@@ -402,7 +401,6 @@ struct e1000_phy_stats {
off */ off */
#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
#define NUM_DEV_IDS 16 #define NUM_DEV_IDS 16
#define NODE_ADDRESS_SIZE 6 #define NODE_ADDRESS_SIZE 6
@@ -1069,7 +1067,6 @@ typedef enum {
e1000_ffe_config_blocked e1000_ffe_config_blocked
} e1000_ffe_config; } e1000_ffe_config;
/* Structure containing variables used by the shared code (e1000_hw.c) */ /* Structure containing variables used by the shared code (e1000_hw.c) */
struct e1000_hw { struct e1000_hw {
const char *name; const char *name;
@@ -2128,7 +2125,6 @@ struct e1000_hw {
/* In-Band Control Register (Page 194, Register 18) */ /* In-Band Control Register (Page 194, Register 18) */
#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
/* Bits... /* Bits...
* 15-5: page * 15-5: page
* 4-0: register offset * 4-0: register offset

2
drivers/net/fsl-mc/dpio/qbman_portal.c
View File

@@ -218,7 +218,6 @@ void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash); qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash);
} }
void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid, void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid,
uint32_t qd_bin, uint32_t qd_prio) uint32_t qd_bin, uint32_t qd_prio)
{ {
@@ -365,7 +364,6 @@ static struct qb_attr_code code_dqrr_stat = QB_CODE(0, 8, 8);
#define QBMAN_DQRR_RESPONSE_BPSCN 0x29 #define QBMAN_DQRR_RESPONSE_BPSCN 0x29
#define QBMAN_DQRR_RESPONSE_CSCN_WQ 0x2a #define QBMAN_DQRR_RESPONSE_CSCN_WQ 0x2a
/* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry /* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry
* only once, so repeated calls can return a sequence of DQRR entries, without * only once, so repeated calls can return a sequence of DQRR entries, without
* requiring they be consumed immediately or in any particular order. */ * requiring they be consumed immediately or in any particular order. */

2
drivers/net/fsl-mc/dpio/qbman_portal.h
View File

@@ -16,7 +16,6 @@
#define QBMAN_VER_4_0_DQRR_SIZE 4 #define QBMAN_VER_4_0_DQRR_SIZE 4
#define QBMAN_VER_4_1_DQRR_SIZE 8 #define QBMAN_VER_4_1_DQRR_SIZE 8
/* --------------------- */ /* --------------------- */
/* portal data structure */ /* portal data structure */
/* --------------------- */ /* --------------------- */
@@ -130,7 +129,6 @@ static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code,
return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]);
} }
/* encode a field to a cacheline */ /* encode a field to a cacheline */
static inline void qb_attr_code_encode(const struct qb_attr_code *code, static inline void qb_attr_code_encode(const struct qb_attr_code *code,
uint32_t *cacheline, uint32_t val) uint32_t *cacheline, uint32_t val)

1
drivers/net/ftmac100.c
View File

@@ -101,7 +101,6 @@ static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6])
/* set the ethernet address */ /* set the ethernet address */
ftmac100_set_mac(priv, enetaddr); ftmac100_set_mac(priv, enetaddr);
/* disable all interrupts */ /* disable all interrupts */
writel (0, &ftmac100->imr); writel (0, &ftmac100->imr);

1
drivers/net/gmac_rockchip.c
View File

@@ -51,7 +51,6 @@ struct rk_gmac_ops {
void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata); void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata);
}; };
static int gmac_rockchip_of_to_plat(struct udevice *dev) static int gmac_rockchip_of_to_plat(struct udevice *dev)
{ {
struct gmac_rockchip_plat *pdata = dev_get_plat(dev); struct gmac_rockchip_plat *pdata = dev_get_plat(dev);

1
drivers/net/ks8851_mll.h
View File

@@ -114,7 +114,6 @@
#define TXSR_TXFID_SHIFT (0) #define TXSR_TXFID_SHIFT (0)
#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f) #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
#define KS_RXCR1 0x74 #define KS_RXCR1 0x74
#define RXCR1_FRXQ (1 << 15) #define RXCR1_FRXQ (1 << 15)
#define RXCR1_RXUDPFCC (1 << 14) #define RXCR1_RXUDPFCC (1 << 14)

1
drivers/net/ldpaa_eth/ldpaa_eth.h
View File

@@ -17,7 +17,6 @@
#include <fsl-mc/fsl_qbman_portal.h> #include <fsl-mc/fsl_qbman_portal.h>
#include <fsl-mc/fsl_mc_private.h> #include <fsl-mc/fsl_mc_private.h>
enum ldpaa_eth_type { enum ldpaa_eth_type {
LDPAA_ETH_1G_E, LDPAA_ETH_1G_E,
LDPAA_ETH_10G_E, LDPAA_ETH_10G_E,

2
drivers/net/ldpaa_eth/ldpaa_wriop.c
View File

@@ -52,7 +52,6 @@ void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)
} }
} }
/*TODO what it do */ /*TODO what it do */
static int wriop_dpmac_to_index(int dpmac_id) static int wriop_dpmac_to_index(int dpmac_id)
{ {
@@ -102,7 +101,6 @@ int wriop_is_enabled_dpmac(int dpmac_id)
return dpmac_info[i].enabled; return dpmac_info[i].enabled;
} }
int wriop_set_mdio(int dpmac_id, struct mii_dev *bus) int wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
{ {
int i = wriop_dpmac_to_index(dpmac_id); int i = wriop_dpmac_to_index(dpmac_id);

3
drivers/net/macb.h
View File

@@ -273,7 +273,6 @@
#define GEM_SGMIIEN_OFFSET 27 #define GEM_SGMIIEN_OFFSET 27
#define GEM_SGMIIEN_SIZE 1 #define GEM_SGMIIEN_SIZE 1
/* Constants for data bus width. */ /* Constants for data bus width. */
#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
@@ -303,7 +302,6 @@
#define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
#define GEM_ADDR64_SIZE 1 #define GEM_ADDR64_SIZE 1
/* Bitfields in NSR */ /* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
#define MACB_NSR_LINK_SIZE 1 #define MACB_NSR_LINK_SIZE 1
@@ -456,7 +454,6 @@
#define GEM_TX_PKT_BUFF_OFFSET 21 #define GEM_TX_PKT_BUFF_OFFSET 21
#define GEM_TX_PKT_BUFF_SIZE 1 #define GEM_TX_PKT_BUFF_SIZE 1
/* Bitfields in DCFG5. */ /* Bitfields in DCFG5. */
#define GEM_TSU_OFFSET 8 #define GEM_TSU_OFFSET 8
#define GEM_TSU_SIZE 1 #define GEM_TSU_SIZE 1

1
drivers/net/mpc8xx_fec.c
View File

@@ -636,7 +636,6 @@ static int fec_start(struct udevice *dev)
return 0; return 0;
} }
static void fec_stop(struct udevice *dev) static void fec_stop(struct udevice *dev)
{ {
struct ether_fcc_info_s *efis = dev_get_priv(dev); struct ether_fcc_info_s *efis = dev_get_priv(dev);

1
drivers/net/mscc_eswitch/luton_switch.c
View File

@@ -627,7 +627,6 @@ static int luton_probe(struct udevice *dev)
GCB_MISC_STAT_PHY_READY, true, 500, false)) GCB_MISC_STAT_PHY_READY, true, 500, false))
return -EACCES; return -EACCES;
/* Initialize miim buses */ /* Initialize miim buses */
memset(&miim, 0x0, sizeof(miim) * LUTON_MIIM_BUS_COUNT); memset(&miim, 0x0, sizeof(miim) * LUTON_MIIM_BUS_COUNT);

1
drivers/net/mscc_eswitch/mscc_miim.h
View File

@@ -20,5 +20,4 @@ struct mii_dev *mscc_mdiobus_init(struct mscc_miim_dev *miim, int *miim_count,
phys_addr_t miim_base, phys_addr_t miim_base,
unsigned long miim_size); unsigned long miim_size);
#endif /* _MSCC_MIIM_H_ */ #endif /* _MSCC_MIIM_H_ */

2
drivers/net/mvneta.c
View File

@@ -970,7 +970,6 @@ static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
return &pp->rxqs[rxq]; return &pp->rxqs[rxq];
} }
/* Drop packets received by the RXQ and free buffers */ /* Drop packets received by the RXQ and free buffers */
static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
struct mvneta_rx_queue *rxq) struct mvneta_rx_queue *rxq)
@@ -1107,7 +1106,6 @@ static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
mvneta_rxq_deinit(pp, &pp->rxqs[queue]); mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
} }
/* Init all Rx queues */ /* Init all Rx queues */
static int mvneta_setup_rxqs(struct mvneta_port *pp) static int mvneta_setup_rxqs(struct mvneta_port *pp)
{ {

1
drivers/net/mvpp2.c
View File

@@ -4702,7 +4702,6 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
port->rxqs[queue] = rxq; port->rxqs[queue] = rxq;
} }
/* Create Rx descriptor rings */ /* Create Rx descriptor rings */
for (queue = 0; queue < rxq_number; queue++) { for (queue = 0; queue < rxq_number; queue++) {
struct mvpp2_rx_queue *rxq = port->rxqs[queue]; struct mvpp2_rx_queue *rxq = port->rxqs[queue];

1
drivers/net/pfe_eth/pfe_mdio.c
View File

@@ -164,7 +164,6 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv)
if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX)
sgmii_2500 = 1; sgmii_2500 = 1;
/* PCS configuration done with corresponding GEMAC */ /* PCS configuration done with corresponding GEMAC */
bus.priv = gem_info[priv->gemac_port].gemac_base; bus.priv = gem_info[priv->gemac_port].gemac_base;

1
drivers/net/phy/davicom.c
View File

@@ -21,7 +21,6 @@
#define MIIM_DM9161_10BTCSR 0x12 #define MIIM_DM9161_10BTCSR 0x12
#define MIIM_DM9161_10BTCSR_INIT 0x7800 #define MIIM_DM9161_10BTCSR_INIT 0x7800
/* Davicom DM9161E */ /* Davicom DM9161E */
static int dm9161_config(struct phy_device *phydev) static int dm9161_config(struct phy_device *phydev)
{ {

1
drivers/net/phy/lxt.c
View File

@@ -15,7 +15,6 @@
#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
/* LXT971 */ /* LXT971 */
static int lxt971_parse_status(struct phy_device *phydev) static int lxt971_parse_status(struct phy_device *phydev)
{ {

1
drivers/net/phy/micrel_ksz90x1.c
View File

@@ -228,7 +228,6 @@ int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
} }
static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr, static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
int regnum) int regnum)
{ {

1
drivers/net/phy/miiphybb.c
View File

@@ -279,7 +279,6 @@ int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
return rdreg; return rdreg;
} }
/***************************************************************************** /*****************************************************************************
* *
* Write a MII PHY register. * Write a MII PHY register.

1
drivers/net/phy/mv88e6352.c
View File

@@ -262,7 +262,6 @@ int do_mvsw_reg_write(const char *name, int argc, char *const argv[])
return ret; return ret;
} }
int do_mvsw_reg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) int do_mvsw_reg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{ {
int ret; int ret;

3
drivers/net/phy/natsemi.c
View File

@@ -42,7 +42,6 @@ U_BOOT_PHY_DRIVER(dp83630) = {
.shutdown = &genphy_shutdown, .shutdown = &genphy_shutdown,
}; };
/* DP83865 Link and Auto-Neg Status Register */ /* DP83865 Link and Auto-Neg Status Register */
#define MIIM_DP83865_LANR 0x11 #define MIIM_DP83865_LANR 0x11
#define MIIM_DP83865_SPD_MASK 0x0018 #define MIIM_DP83865_SPD_MASK 0x0018
@@ -50,7 +49,6 @@ U_BOOT_PHY_DRIVER(dp83630) = {
#define MIIM_DP83865_SPD_100 0x0008 #define MIIM_DP83865_SPD_100 0x0008
#define MIIM_DP83865_DPX_FULL 0x0002 #define MIIM_DP83865_DPX_FULL 0x0002
/* NatSemi DP83865 */ /* NatSemi DP83865 */
static int dp838xx_config(struct phy_device *phydev) static int dp838xx_config(struct phy_device *phydev)
{ {
@@ -101,7 +99,6 @@ static int dp83865_startup(struct phy_device *phydev)
return dp83865_parse_status(phydev); return dp83865_parse_status(phydev);
} }
U_BOOT_PHY_DRIVER(dp83865) = { U_BOOT_PHY_DRIVER(dp83865) = {
.name = "NatSemi DP83865", .name = "NatSemi DP83865",
.uid = 0x20005c70, .uid = 0x20005c70,

2
drivers/net/rtl8169.c
View File

@@ -736,7 +736,6 @@ static void rtl8169_hw_start(struct udevice *dev)
RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
(InterFrameGap << TxInterFrameGapShift)); (InterFrameGap << TxInterFrameGapShift));
tpc->cur_rx = 0; tpc->cur_rx = 0;
RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev, RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
@@ -1031,7 +1030,6 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name,
#endif #endif
} }
tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
if (!tpc->RxDescArray) if (!tpc->RxDescArray)
return -ENOMEM; return -ENOMEM;

1
drivers/net/sh_eth.h
View File

@@ -474,7 +474,6 @@ enum EESR_BIT {
EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
}; };
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define TX_CHECK (EESR_TC1 | EESR_FTC) # define TX_CHECK (EESR_TC1 | EESR_FTC)
# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \

2
drivers/net/sun8i_emac.c
View File

@@ -171,7 +171,6 @@ struct emac_eth_dev {
struct udevice *phy_reg; struct udevice *phy_reg;
}; };
struct sun8i_eth_pdata { struct sun8i_eth_pdata {
struct eth_pdata eth_pdata; struct eth_pdata eth_pdata;
u32 reset_delays[3]; u32 reset_delays[3];
@@ -179,7 +178,6 @@ struct sun8i_eth_pdata {
int rx_delay_ps; int rx_delay_ps;
}; };
static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{ {
struct udevice *dev = bus->priv; struct udevice *dev = bus->priv;

3
drivers/net/ti/davinci_emac.c
View File

@@ -144,7 +144,6 @@ static int davinci_emac_write_hwaddr(struct udevice *dev)
writel(mac_hi, &adap_emac->MACSRCADDRHI); writel(mac_hi, &adap_emac->MACSRCADDRHI);
writel(mac_lo, &adap_emac->MACSRCADDRLO); writel(mac_lo, &adap_emac->MACSRCADDRLO);
return 0; return 0;
} }
@@ -205,7 +204,6 @@ static int davinci_eth_phy_detect(void)
return count; return count;
} }
/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
{ {
@@ -378,7 +376,6 @@ static int gen_auto_negotiate(int phy_addr)
} }
/* End of generic PHY functions */ /* End of generic PHY functions */
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad, static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
int reg) int reg)

3
drivers/net/ti/davinci_emac.h
View File

@@ -20,7 +20,6 @@
*/ */
#define EMAC_MAX_RX_BUFFERS 10 #define EMAC_MAX_RX_BUFFERS 10
/*********************************************** /***********************************************
******** Internally used macros *************** ******** Internally used macros ***************
***********************************************/ ***********************************************/
@@ -45,7 +44,6 @@
/* Number of statistics registers */ /* Number of statistics registers */
#define EMAC_NUM_STATS 36 #define EMAC_NUM_STATS 36
/* EMAC Descriptor */ /* EMAC Descriptor */
typedef volatile struct _emac_desc typedef volatile struct _emac_desc
{ {
@@ -78,7 +76,6 @@ typedef volatile struct _emac_desc
#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) #define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
#define MDIO_CONTROL_IDLE (0x80000000) #define MDIO_CONTROL_IDLE (0x80000000)
#define MDIO_CONTROL_ENABLE (0x40000000) #define MDIO_CONTROL_ENABLE (0x40000000)
#define MDIO_CONTROL_FAULT_ENABLE (0x40000) #define MDIO_CONTROL_FAULT_ENABLE (0x40000)

2
drivers/net/ti/keystone_net.c
View File

@@ -83,7 +83,6 @@ enum link_type {
#endif #endif
struct ks2_eth_priv { struct ks2_eth_priv {
struct udevice *dev; struct udevice *dev;
struct phy_device *phydev; struct phy_device *phydev;
@@ -208,7 +207,6 @@ int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
__raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
__raw_writel(control, SGMII_CTL_REG(port)); __raw_writel(control, SGMII_CTL_REG(port));
mask = SGMII_REG_STATUS_LINK; mask = SGMII_REG_STATUS_LINK;
if (control & SGMII_REG_CONTROL_AUTONEG) if (control & SGMII_REG_CONTROL_AUTONEG)

1
drivers/net/zynq_gem.c
View File

@@ -390,7 +390,6 @@ static int zynq_phy_init(struct udevice *dev)
return phy_config(priv->phydev); return phy_config(priv->phydev);
} }
static int zynq_gem_init(struct udevice *dev) static int zynq_gem_init(struct udevice *dev)
{ {
u32 i, nwconfig, nwcfg; u32 i, nwconfig, nwcfg;