ARM: stm32mp: enable data cache after LMB configuration for STM32MP1
Move the stm32mp1 data cache reconfiguration after the lmb init call
board_r::initr_lmb to allow parsing of the reserved region with
no-map tag.
After this patch the DDR is not fully mapped up to arch_early_init_r()
call, only the relocation region is mapped, but it is enough for
the first board_r initialization phases; later, when arch_early_init_r()
is called, the LMB is already initialized and the function
lmb_is_reserved_flags() function is functional, this LMB function
is called in the weak function dram_bank_mmu_setup() when
dcache_enable() is executed.
Without this change, as LMB is not initialized when it is used in
dram_bank_mmu_setup, the OP-TEE region is mapped cache-able by U-Boot
and we have some firewall violation since "LMB memory map global and
persistent" series.
Fixes: ed17a33fed
("lmb: make LMB memory map persistent and global")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This commit is contained in:
@@ -39,6 +39,7 @@ choice
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config STM32MP13X
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bool "Support STMicroelectronics STM32MP13x Soc"
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select ARCH_EARLY_INIT_R
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select ARM_SMCCC
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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@@ -57,6 +58,7 @@ config STM32MP13X
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config STM32MP15X
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bool "Support STMicroelectronics STM32MP15x Soc"
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select ARCH_EARLY_INIT_R
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select ARCH_SUPPORT_PSCI
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select BINMAN
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select CPU_V7A
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@@ -143,6 +143,11 @@ void enable_caches(void)
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{
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/* I-cache is already enabled in start.S: icache_enable() not needed */
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/* keep D-cache configuration done before relocation, wait arch_early_init_r*/
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}
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int arch_early_init_r(void)
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{
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/* deactivate the data cache, early enabled in arch_cpu_init() */
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dcache_disable();
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/*
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@@ -150,6 +155,8 @@ void enable_caches(void)
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* warning: the TLB location udpated in board_f.c::reserve_mmu
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*/
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dcache_enable();
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return 0;
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}
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static void setup_boot_mode(void)
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