arm: socfpga: Enable SPL_DM_SEQ_ALIAS for all SOCFPGA configs
This feature is required in SPL to enable support for loading from SPI flash. Also clean up the #define in socfpga_common.h. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin-Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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committed by
Michal Simek

parent
47c0d79edc
commit
fc82edd844
@@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
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CONFIG_SPL=y
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CONFIG_SPL=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FLASH is not set
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@@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
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CONFIG_SPL=y
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CONFIG_SPL=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FLASH is not set
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@@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
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CONFIG_SPL=y
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CONFIG_SPL=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FLASH is not set
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@@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
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CONFIG_SPL=y
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CONFIG_SPL=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FLASH is not set
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@@ -6,6 +6,7 @@ CONFIG_DM_GPIO=y
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CONFIG_TARGET_SOCFPGA_SR1500=y
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CONFIG_TARGET_SOCFPGA_SR1500=y
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
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CONFIG_SPL=y
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CONFIG_SPL=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_IMLS is not set
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@@ -370,7 +370,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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/* SPL QSPI boot support */
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/* SPL QSPI boot support */
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#ifdef CONFIG_SPL_SPI_SUPPORT
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#ifdef CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_DM_SEQ_ALIAS 1
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
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