firmware: ti_sci: Add support for NAVSS resource management
Texas Instruments' System Control Interface (TI-SCI) Message Protocol abstracts management of NAVSS resources, like PSI-L pairing and unpairing, UDMAP tx/rx/flow configuration and Rings. This patch adds support for requesting and configuring such resources from TI-SCI firmware. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
This commit is contained in:
Grygorii Strashko
committed by
Tom Rini
Tom Rini
parent
02f173ca15
commit
fd6b40b1ba
@@ -212,6 +212,31 @@ struct ti_sci_clk_ops {
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u64 *current_freq);
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};
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/**
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* struct ti_sci_rm_core_ops - Resource management core operations
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* @get_range: Get a range of resources belonging to ti sci host.
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* @get_rage_from_shost: Get a range of resources belonging to
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* specified host id.
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* - s_host: Host processing entity to which the
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* resources are allocated
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*
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* NOTE: for these functions, all the parameters are consolidated and defined
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* as below:
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* - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
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* - dev_id: TISCI device ID.
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* - subtype: Resource assignment subtype that is being requested
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* from the given device.
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* - range_start: Start index of the resource range
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* - range_end: Number of resources in the range
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*/
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struct ti_sci_rm_core_ops {
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int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
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u8 subtype, u16 *range_start, u16 *range_num);
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int (*get_range_from_shost)(const struct ti_sci_handle *handle,
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u32 dev_id, u8 subtype, u8 s_host,
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u16 *range_start, u16 *range_num);
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};
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/**
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* struct ti_sci_core_ops - SoC Core Operations
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* @reboot_device: Reboot the SoC
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@@ -257,6 +282,230 @@ struct ti_sci_proc_ops {
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u32 *sts_flags);
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};
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#define TI_SCI_RING_MODE_RING (0)
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#define TI_SCI_RING_MODE_MESSAGE (1)
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#define TI_SCI_RING_MODE_CREDENTIALS (2)
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#define TI_SCI_RING_MODE_QM (3)
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#define TI_SCI_MSG_UNUSED_SECONDARY_HOST TI_SCI_RM_NULL_U8
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/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
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#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
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/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
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#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
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/* RA config.count parameter is valid for RM ring configure TI_SCI message */
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#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
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/* RA config.mode parameter is valid for RM ring configure TI_SCI message */
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#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
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/* RA config.size parameter is valid for RM ring configure TI_SCI message */
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#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
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/* RA config.order_id parameter is valid for RM ring configure TISCI message */
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#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
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#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
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(TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
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TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
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TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
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TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
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TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
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/**
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* struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
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* @config: configure the SoC Navigator Subsystem Ring Accelerator ring
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* @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
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* configuration
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*/
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struct ti_sci_rm_ringacc_ops {
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int (*config)(const struct ti_sci_handle *handle,
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u32 valid_params, u16 nav_id, u16 index,
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u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
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u8 size, u8 order_id
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);
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int (*get_config)(const struct ti_sci_handle *handle,
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u32 nav_id, u32 index, u8 *mode,
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u32 *addr_lo, u32 *addr_hi, u32 *count,
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u8 *size, u8 *order_id);
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};
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/**
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* struct ti_sci_rm_psil_ops - PSI-L thread operations
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* @pair: pair PSI-L source thread to a destination thread.
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* If the src_thread is mapped to UDMA tchan, the corresponding channel's
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* TCHAN_THRD_ID register is updated.
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* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
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* RCHAN_THRD_ID register is updated.
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* @unpair: unpair PSI-L source thread from a destination thread.
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* If the src_thread is mapped to UDMA tchan, the corresponding channel's
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* TCHAN_THRD_ID register is cleared.
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* If the dst_thread is mapped to UDMA rchan, the corresponding channel's
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* RCHAN_THRD_ID register is cleared.
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*/
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struct ti_sci_rm_psil_ops {
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int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
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u32 src_thread, u32 dst_thread);
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int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
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u32 src_thread, u32 dst_thread);
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};
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/* UDMAP channel types */
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#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
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#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
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#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
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#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
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#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
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#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
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/* UDMAP channel atypes */
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#define TI_SCI_RM_UDMAP_ATYPE_PHYS 0
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#define TI_SCI_RM_UDMAP_ATYPE_INTERMEDIATE 1
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#define TI_SCI_RM_UDMAP_ATYPE_VIRTUAL 2
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/* UDMAP channel scheduling priorities */
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#define TI_SCI_RM_UDMAP_SCHED_PRIOR_HIGH 0
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#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDHIGH 1
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#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDLOW 2
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#define TI_SCI_RM_UDMAP_SCHED_PRIOR_LOW 3
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#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
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#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
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/* UDMAP TX/RX channel valid_params common declarations */
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
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/**
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* Configures a Navigator Subsystem UDMAP transmit channel
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*
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* Configures a Navigator Subsystem UDMAP transmit channel registers.
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* See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
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*/
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struct ti_sci_msg_rm_udmap_tx_ch_cfg {
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u32 valid_params;
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
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u16 nav_id;
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u16 index;
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u8 tx_pause_on_err;
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u8 tx_filt_einfo;
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u8 tx_filt_pswords;
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u8 tx_atype;
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u8 tx_chan_type;
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u8 tx_supr_tdpkt;
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u16 tx_fetch_size;
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u8 tx_credit_count;
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u16 txcq_qnum;
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u8 tx_priority;
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u8 tx_qos;
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u8 tx_orderid;
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u16 fdepth;
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u8 tx_sched_priority;
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};
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/**
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* Configures a Navigator Subsystem UDMAP receive channel
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*
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* Configures a Navigator Subsystem UDMAP receive channel registers.
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* See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
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*/
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struct ti_sci_msg_rm_udmap_rx_ch_cfg {
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u32 valid_params;
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
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u16 nav_id;
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u16 index;
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u16 rx_fetch_size;
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u16 rxcq_qnum;
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u8 rx_priority;
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u8 rx_qos;
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u8 rx_orderid;
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u8 rx_sched_priority;
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u16 flowid_start;
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u16 flowid_cnt;
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u8 rx_pause_on_err;
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u8 rx_atype;
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u8 rx_chan_type;
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u8 rx_ignore_short;
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u8 rx_ignore_long;
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};
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/**
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* Configures a Navigator Subsystem UDMAP receive flow
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*
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* Configures a Navigator Subsystem UDMAP receive flow's registers.
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* See @tis_ci_msg_rm_udmap_flow_cfg_req
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*/
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struct ti_sci_msg_rm_udmap_flow_cfg {
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u32 valid_params;
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
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#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
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u16 nav_id;
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u16 flow_index;
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u8 rx_einfo_present;
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u8 rx_psinfo_present;
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u8 rx_error_handling;
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u8 rx_desc_type;
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u16 rx_sop_offset;
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u16 rx_dest_qnum;
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u8 rx_src_tag_hi;
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u8 rx_src_tag_lo;
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u8 rx_dest_tag_hi;
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u8 rx_dest_tag_lo;
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u8 rx_src_tag_hi_sel;
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u8 rx_src_tag_lo_sel;
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u8 rx_dest_tag_hi_sel;
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u8 rx_dest_tag_lo_sel;
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u16 rx_fdq0_sz0_qnum;
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u16 rx_fdq1_qnum;
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u16 rx_fdq2_qnum;
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u16 rx_fdq3_qnum;
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u8 rx_ps_location;
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};
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/**
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* struct ti_sci_rm_udmap_ops - UDMA Management operations
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* @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
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* @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
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* @rx_flow_cfg: configure SoC Navigator Subsystem UDMA receive flow.
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*/
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struct ti_sci_rm_udmap_ops {
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int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
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const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
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int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
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const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
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int (*rx_flow_cfg)(
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const struct ti_sci_handle *handle,
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const struct ti_sci_msg_rm_udmap_flow_cfg *params);
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};
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/**
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* struct ti_sci_ops - Function support for TI SCI
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* @board_ops: Miscellaneous operations
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@@ -264,6 +513,7 @@ struct ti_sci_proc_ops {
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* @clk_ops: Clock specific operations
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* @core_ops: Core specific operations
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* @proc_ops: Processor specific operations
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* @ring_ops: Ring Accelerator Management operations
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*/
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struct ti_sci_ops {
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struct ti_sci_board_ops board_ops;
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@@ -271,6 +521,10 @@ struct ti_sci_ops {
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struct ti_sci_clk_ops clk_ops;
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struct ti_sci_core_ops core_ops;
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struct ti_sci_proc_ops proc_ops;
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struct ti_sci_rm_core_ops rm_core_ops;
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struct ti_sci_rm_ringacc_ops rm_ring_ops;
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struct ti_sci_rm_psil_ops rm_psil_ops;
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struct ti_sci_rm_udmap_ops rm_udmap_ops;
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};
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/**
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@@ -283,12 +537,42 @@ struct ti_sci_handle {
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struct ti_sci_version_info version;
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};
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#define TI_SCI_RESOURCE_NULL 0xffff
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/**
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* struct ti_sci_resource_desc - Description of TI SCI resource instance range.
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* @start: Start index of the resource.
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* @num: Number of resources.
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* @res_map: Bitmap to manage the allocation of these resources.
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*/
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struct ti_sci_resource_desc {
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u16 start;
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u16 num;
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unsigned long *res_map;
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};
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/**
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* struct ti_sci_resource - Structure representing a resource assigned
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* to a device.
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* @sets: Number of sets available from this resource type
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* @desc: Array of resource descriptors.
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*/
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struct ti_sci_resource {
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u16 sets;
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struct ti_sci_resource_desc *desc;
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};
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#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
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const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev);
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const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev);
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const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
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const char *property);
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u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
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void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
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struct ti_sci_resource *
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devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
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struct udevice *dev, u32 dev_id, char *of_prop);
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#else /* CONFIG_TI_SCI_PROTOCOL */
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@@ -309,6 +593,22 @@ const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
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{
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return ERR_PTR(-EINVAL);
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}
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static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
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{
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return TI_SCI_RESOURCE_NULL;
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}
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static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
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{
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}
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static inline struct ti_sci_resource *
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devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
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struct udevice *dev, u32 dev_id, char *of_prop)
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{
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return ERR_PTR(-EINVAL);
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}
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#endif /* CONFIG_TI_SCI_PROTOCOL */
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#endif /* __TISCI_PROTOCOL_H */
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