Commit Graph

190 Commits

Author SHA1 Message Date
Kongyang Liu
1cd239f444 riscv: spacemit: bananapi_f3: initial support added
Add basic support for SpacemiT's Banana Pi F3 board.
Update the k1.dtsi align with mainline.
Note that the device tree files follow the mainline Linux source[1].

Links: https://patches.linaro.org/project/linux-serial/patch/20240730-k1-01-basic-dt-v5-8-98263aae83be@gentoo.org/ [1]

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Signed-off-by: Huan Zhou <pericycle.cc@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
2024-12-18 13:19:16 +08:00
Hal Feng
2c1cb8837b riscv: cpu: jh7110: Sort the list of imply statements
The imply statements should be sorted in the sequence
of appearance in .config.

Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18 13:19:16 +08:00
Hal Feng
84d3911a01 dts: starfive: Switch to using upstream DT
Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to
the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi
to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b
device tree as the default device tree.

Drop redundant DT files from arch/riscv/dts/ and redundant clock and
reset definitions from include/dt-bindings/.

Since the old clock definitions is a little different from those in
upstream Linux, update the clock definitions in clock drivers
accordingly.

Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18 13:19:15 +08:00
Simon Glass
bef9fdbed2 arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:47 -06:00
Chia-Wei Wang
9efcb10a09 riscv: Add AST2700 SoC initial platform support
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.

This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:03 +08:00
Chia-Wei Wang
717002f8ff riscv: u-boot-spl.lds: Remove _image_binary_end alignment
The _image_binary_end symbol was aligned to the 8-bytes boundary.
However, the SPL device tree (u-boot-spl.dtb) is concatenated right
after the binary (u-boot-spl-nodtb.bin) wihtout the consideration of
the 8-bytes alignment restriction.

After then, for the SPL_SEPARATE_BSS case, fdtdec_setup() searching
for the DTB by _image_binary_end will return the "Missing DTB" error.
As the real DTB starting point does not align to a 8-bytes address
like _image_binary_end does.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-09-11 20:35:03 +08:00
Leo Yu-Chi Liang
1d29c718b7 andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND
Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND
to do cache flush operation in M-mode and S-mode.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-05-30 16:01:13 +08:00
Leo Yu-Chi Liang
cea0ed2e3f riscv: remove cache enablement in start.S
Cache could be enabled in harts_early_init board-specific hook,
so remove cache enablement in start.S

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-05-30 16:01:09 +08:00
Leo Yu-Chi Liang
2b8dc36b4c andes: Unify naming policy for Andes related source
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-05-14 18:50:47 +08:00
Lukas Funke
19b762cf83 board: starfive: Rename spl_soc_init() to spl_dram_init()
Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().

Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-05-02 00:01:18 +08:00
Lukas Funke
d6c81b87e6 board: sifive: Rename spl_soc_init() to spl_dram_init()
Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().

Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-05-02 00:01:18 +08:00
Yu Chien Peter Lin
fd55792e14 riscv: andesv5: Set default cache line size to 64-bytes
The instruction and data cache line sizes of Andes core
are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
the SYS_CACHELINE_SIZE is enabled with a default value.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-05-01 22:40:00 +08:00
Conor Dooley
f39b1b77d8 riscv: support extension probing using riscv, isa-extensions
A new property has been added, with an extensive rationale at [1], that
can be used in place of "riscv,isa" to indicate what extensions are
supported by a given platform that is a list of strings rather than a
single string. There are some differences between the new property,
"riscv,isa-extensions" and the incumbent "riscv,isa" - chief among them
for the sake of parsing being the list of strings, as opposed to a
string. Another advantage is strictly defined meanings for each string
in a dt-binding, rather than deriving meaning from RVI standards. This
will likely to some divergence over time, but U-Boot's current use of
extension detection is very limited - there are just four callsites of
supports_extension() in mainline U-Boot.

These checks are limited to two checks for FPU support and two checks
for "s" and "u". "s" and "u" are not supported by the new property, but
they were also not permitted in "riscv,isa". These checks are only
meaningful (or run) in M-Mode, in which case supports_extension() does
not parse the devicetree anyway.

Add support for the new property in U-Boot, prioritising it, before
falling back to the, now deprecated, "riscv,isa" property if it is not
present.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-04-09 11:30:17 +08:00
Conor Dooley
b90edde701 riscv: don't read riscv, isa in the riscv cpu's get_desc()
cpu_get_desc() for the RISC-V CPU currently reads "riscv,isa" to get
the description, but it is no longer a required property and cannot be
assummed to always be present, as the new "riscv,isa-extensions" and
"riscv,isa-base" properties may be present instead.

On RISC-V, cpu_get_desc() has two main uses - firstly providing an
informational name for the CPU for smbios or at boot with
DISPLAY_CPUINFO etc and secondly it forms the basis of ISA extension
detection in supports_extension() as it returns (a portion of) an ISA
string.

cpu_get_desc() returns a string, which aligned with "riscv,isa" but
the new property is a list of strings. Rather than add support for
the list of strings property, which would require creating an isa
string from "riscv,isa-extensions", modify the RISC-V CPU's
implementaion of cpu_get_desc() return the first compatible as the
cpu description instead. This may be fine for the informational cases,
but it would break extension dtection, given supports_extension()
expects cpu_get_desc() to return an ISA string.

Call dev_read_string() directly in supports_extension() to get the
contents of "riscv,isa" so that extension detection remains functional.
As a knock-on affect of this change, extension detection is no longer
broken for long ISA strings. Previously if the ISA string exceeded the
32 element array that supports_extension() passed to cpu_get_desc(),
it would return ENOSPC and no extensions would be detected.
This bug probably had no impact as U-Boot does not currently do anything
meaningful with the results of supports_extension() and most SoCs
supported by U-Boot don't have anywhere near that complex of an ISA
string. The QEMU virt machine's CPUs do however, so extension detection
doesn't work there.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-04-09 11:30:17 +08:00
Kongyang Liu
c21dfcb556 riscv: cache: Implement dcache for cv1800b
Add dcache operations invalidate_dcache_range and flush_dcache_range for
cv1800b.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-04-09 11:30:02 +08:00
Kongyang Liu
ae800aa79a riscv: cpu: cv1800b: Add support for cv1800b SoC
Add Sophgo cv1800b SoC to support RISC-V arch.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-04-09 11:30:02 +08:00
Ben Dooks
e4f69492ad riscv: add backtrace support
When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-04-09 11:29:38 +08:00
Conor Dooley
0d95add3b1 riscv: cpu: improve multi-letter extension detection in supports_extension()
The first multi-letter extension after the single-letter extensions does
not have to be preceded by an underscore, which could cause the parser
to mistakenly find a single-letter extension after the start of the
multi-letter portion of the string.
Three letters precede multi-letter extensions (s, x & z), none of which
are valid single-letter extensions. The dt-binding also allows
multi-letter extensions starting with h, but no such extension have been
frozen or ratified, and the unprivileged spec no longer uses "h" as a
prefix for multi-letter hypervisor extensions, having moved to "sh"
instead. For that reason, modify the parser to stop at s, x & z to prevent
this overrun, ignoring h.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-12 14:36:13 +08:00
Leo Yu-Chi Liang
61d5c543f3 andes: cpu: Enable cache and TLB ECC support
Andes CPU supports cache and TLB ECC.
Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
Leo Yu-Chi Liang
bf12bb99d8 andes: cpu: Enable memboost feature
Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
Leo Yu-Chi Liang
b0469041c0 andes: ae350: Implement cache switch via Kconfig
Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
Provide the corresponding implementation to the options.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
Simon Glass
c35bfd07ec riscv: Add a reset_cpu() function
The current do_reset() is called from a command context. Add a function
which can be used from anywhere, as is done on ARM. Adjust do_reset()
to call it.

Note that reset_cpu() is normally provided by SYSRESET so make this
declaration conditional on that being disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Tested-by: Chanho Park <chanho61.park@samsung.com>
2023-12-21 16:07:52 -05:00
Samuel Holland
3b00fab616 riscv: Align the trap handler to 64 bytes
This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."

Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02 15:15:46 +08:00
Tom Rini
0b9441ae76 riscv: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-10-24 16:34:45 -04:00
Heinrich Schuchardt
9385c9b0cd riscv: remove dram_init_banksize()
Remove dram_init_banksize() on the architecture level.

Limiting used RAM to under 4 GiB is only necessary for CPUs which have a
DMA issue. SoC specific code already exists for FU540, FU740, JH7110.

Not all RISC-V boards will have memory below 4 GiB.

A weak implementation of dram_init_banksize() exists in common/board_f.c.

See the discussion in
https://lore.kernel.org/u-boot/545fe813-cb1e-469c-a131-0025c77aeaa2@canonical.com/T/

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2023-10-19 17:29:32 +08:00
Yu Chien Peter Lin
8a0d5f2f51 riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode
The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.

Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-04 18:23:54 +08:00
Tom Rini
ac897385bb Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-02 10:55:44 -04:00
Tom Rini
59d2a7d731 riscv: Correct event usage for riscv_cpu_probe/setup
With having both an EVENT_SPY_SIMPLE setup for both riscv_cpu_probe and
riscv_cpu_setup we do not need the latter function to call the former
function as it will already have been done in time.

Fixes: 1c55d62fb9 ("riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback")
Tested-by: Milan P. Stanić <mps@arvanta.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-06 13:47:24 -04:00
Tom Rini
68f446fb9b riscv: Rework riscv_cpu_probe for current event macros
This function should now be a EVENT_SPY_SIMPLE call, update it.

Tested-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-06 13:47:20 -04:00
Shengyu Qu
64339bc1f2 riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT
Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error
would be triggered. Currently, we use DDR ram for SPL malloc arena on
Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as
SPL malloc arena. To avoid triggering ECC error in this scenario, we
imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:46 +08:00
Tom Rini
ddec4cae62 Merge tag 'v2023.10-rc4' into next
Prepare v2023.10-rc4
2023-09-04 10:51:58 -04:00
Simon Glass
f72d0d4a2f event: Convert existing spy records to simple
Very few of the existing event-spy records use the arguments they are
passed. Update them to use a simple spy instead, to simplify the code.

Where an adaptor function is currently used, remove it where possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-31 13:16:54 -04:00
Chanho Park
1c55d62fb9 riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback
Since the Patch 55171aedda, VisionFive2 booting has been broken [1].
VisionFive2 board requires to enable CONFIG_TIMER_EARLY but booting went
to panic from initr_dm_devices due to lack of a timer device.

- Error logs
initcall sequence 00000000fffd8d38 failed at call 00000000402185e4
(err=-19)

Thus, we need to move riscv_cpu_probe function in order to register
the timer earlier than initr_dm_devices.

Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
2023-08-22 08:07:54 -06:00
Heinrich Schuchardt
d768dd8855 common: return type board_get_usable_ram_top
board_get_usable_ram_top() returns a physical address that is stored in
gd->ram_top. The return type of the function should be phys_addr_t like the
current type of gd->ram_top.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Shengyu Qu
47ed15125c riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:55 +08:00
Shengyu Qu
6419f8e9fd riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing code has
following issues:
 1. Each hart (in the middle of a function call) overwriting its own
    stack and other harts' stacks.
    (data-race and data-corruption)
 2. Lottery winner hart can be doing "board_init_f_init_reserve",
    while other harts are in the middle of zeroing L2 LIM.
    (data-race)

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:12 +08:00
Minda Chen
eca2d41c68 riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
Heinrich Schuchardt
6aabe229f8 riscv: define a cache line size for the generic CPU
The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.

Define the cache line size for QEMU on RISC-V to be 64 bytes.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
2023-07-24 13:22:24 +08:00
Bo Gan
28ff3f16c4 riscv: setup per-hart stack earlier
Harts need to use per-hart stack before any function call, even if that
function is a simple one. When the callee uses stack for register save/
restore, especially RA, if nested call, concurrent access by multiple
harts on the same stack will cause data-race.

This patch sets up SP before `board_init_f_alloc_reserve`. A side effect
of this is that the memory layout has changed as the following:

+----------------+        +----------------+ <----- SPL_STACK/
|  ......        |        |  hart 0 stack  |        SYS_INIT_SP_ADDR
|  malloc_base   |        +----------------+
+----------------+        |  hart 1 stack  |
|  GD            |        +----------------+ If not SMP, N=1
+----------------+        |  ......        |
|  hart 0 stack  |        +----------------+
+----------------+   ==>  |  hart N-1 stack|
|  hart 1 stack  |        +----------------+
+----------------+        |  ......        |
|  ......        |        |  malloc_base   |
+----------------+        +----------------+
|  hart N-1 stack|        |  GD            |
+----------------+        +----------------+
|                |        |                |

Signed-off-by: Bo Gan <ganboing@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Leo <ycliang@andestech.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-24 13:17:26 +08:00
Bin Meng
9675d92027 riscv: Rename SiFive CLINT to RISC-V ALINT
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-07-12 13:21:40 +08:00
Yanhong Wang
38d900b409 ram: starfive: Read memory size information from EEPROM
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.

If there is no information in EEPROM, it is initialized with the default
size defined in DT.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-12 13:21:40 +08:00
Bin Meng
4a3efd71cd riscv: Fix alignment of RELA sections in the linker scripts
In current linker script both .efi_runtime_rel and .rela.dyn sections
are of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
These two are arranged as a continuous region on purpose so that the
prelink-riscv executable can fix up the PIE addresses in one loop.

However there is an 'ALIGN(8)' between these 2 sections which might
cause a gap to be inserted between these 2 sections to satisfy the
alignment requirement on RV32. This would break the assumption of
the prelink process and generate an unbootable image.

Fixes: 9a6569a043 ("riscv: Update alignment for some sections in linker scripts")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-06-27 10:09:51 +08:00
Simon Glass
55171aedda dm: Emit the arch_cpu_init_dm() even only before relocation
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.

With this, chromebook_link64 makes it through SPL.

Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Bin Meng
9a6569a043 riscv: Update alignment for some sections in linker scripts
Some sections in the linker scripts are aligned to 4 bytes, which
may cause misaligned exception on some platforms, e.g.: clearing
the bss section on 64-bit hardware if __bss_start does not start
from a naturally 8 bytes aligned address.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20 20:45:08 +08:00
Bin Meng
3f37baae83 riscv: spl: Remove relocation sections
U-Boot SPL is not relocable. Drop these relocation sections.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20 20:45:08 +08:00
Bin Meng
3c09ac2c58 riscv: Avoid updating the link register
board_init_r does not return for U-Boot SPL hence there is no need
to update the link register when jumping to board_init_r.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20 20:45:08 +08:00
Bin Meng
485f593079 riscv: Change to use positive offset to access relocation entries
The codes currently skip the very first relocation entry, and have
an inaccurate comment "skip first reserved entry" indicating that
the first entry is reserved, but later it references the elements
in the first relocation entry using a minus offset.

Change to use a positive offset so that there is no need to skip
the first relocation entry.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20 20:45:08 +08:00
Bin Meng
0b1a3a22de riscv: Optimize loading relocation type
't5' already contains relocation type so don't bother reloading it.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20 20:45:08 +08:00
Bin Meng
883f553e6b riscv: Optimize source end address calculation in start.S
The __bss_start is the source end address hence load its address
directly into register 't2' for optimization.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20 20:45:08 +08:00
Yanhong Wang
2f5fad0b0d riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC
Add Kconfig to select the basic functions for StarFive JH7110 SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20 16:08:44 +08:00