In commit 399f739be6 ("CI: allow jobs to be run in merge requests") we
added "rules:when: always" to many stages of the pipeline to allow for merge
requests to trigger a run. However based on current Gitlab
documentation, we should still be triggered on merge requests without
this. Furthermore the way we have things written today we always run all
stages of the CI rather than failing out early on problems, which is not
always useful. Remove these as we should still be fine with merge
requests triggering a run.
Link: https://docs.gitlab.com/ee/ci/yaml/#rules
Signed-off-by: Tom Rini <trini@konsulko.com>
Our Gitlab pipeline is currently broken up in to several stages. This
was done with the thought process of "we should test tools and if
they're good test emulated targets and if they're good test real
hardware and if they're good test the world". However, in terms of that
first stage it only really matters that binman, et al are still
functional. And for a few years now Gitlab has had a "needs" keyword
that lets you refine pipeline dependencies. Use this to perform the
minor optimization of having test.py only require that tool testing job.
This will become more useful later when we add long running testsuites
that we do not want to block later jobs.
Signed-off-by: Tom Rini <trini@konsulko.com>
It is annoying to have sandbox enter a boot loop when an assertion
fails. Hang instead, since then the error message is only printed once
and Ctrl-C can be used to quit, as per normal.
Signed-off-by: Simon Glass <sjg@chromium.org>
The mpc8xxx_gpio driver contains a workaround for certain chips
where the previously written state of outputs cannot be read back
from the GPIO data (GPDAT) register (MPC8572/MPC8536). This workaround
consists of tracking the state of GPDAT in a "shadow register" (i.e. a
software variable). The shadow register is initialized to zero.
This results in a problem w.r.t. outputs that are configured to a
high (1) state before U-Boot runs, but not touched by U-Boot itself:
Due to the zero-initialization, these GPIOs end up being set to zero,
the first time that any other output is set.
To avoid such issues initialize the GPDAT shadow register to the value
previously held by any outputs, if possible. On MPC8572/MPC8536 this
should make no difference, i.e. the shadow register should be
initialized to zero on these chips.
This patch has been tested on a MPC8314E-based board.
Reviewed-by: Sinan Akman <sinan@writeme.com>
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
To increase readability, use the defined constant instead of specifying
SPCR[TBEN] as a number.
Reviewed-by: Sinan Akman <sinan@writeme.com>
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Globals defined in headers can result in multiple-definition errors
while linking, if they are visible beyond the current translation unit.
This hasn't been a problem for initreg.h so far, but would become a
problem in the next patch, where I use a constant from initreg.h in a
second C file.
Reviewed-by: Sinan Akman <sinan@writeme.com>
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
TBU and TBL are specified as two 32-bit registers that form a 64-bit
value, but the calculation only shifted TBU by 16 bits.
Fix this by actually shifting 32 bits.
Reviewed-by: Sinan Akman <sinan@writeme.com>
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
PowerPC general-purpose registers are historically specified as plain
numbers (0-31), which makes them hard to distinguish from immediates.
For this reason, include/ppc_asm.tmpl defines aliases named r0-r31.
This can still lead to uncaught mistakes if a register is used in place
of a number.
Instead of (e.g.) 5 use %r5, which will result in an assembler warning
if used as a number. Turn these warnings into errors by passing
`--fatal-warnings` to the assembler.
I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig
(MPC85xx) that this patch results in the same machine code.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Instructions such as dcbi are in the X-form; they have RA and RB fields
and the effective address (EA) is computed as (RA|0)+(RB). In words,
this means that if RA is zero, the left-hand side of the addition is
zero, otherwise the corresponding GPR is used. r0 can never be used on
the left-hand side of a X-form instruction.
For D-form instructions such as addis, the Power ISA illustrates this in
the instruction pseudo-code:
if RA = 0 then RT <- EXTS(SI || 0x0000)
else RT <- (RA) + EXIS(SI || 0x0000)
In all of these cases, RA=0 indicates the value zero, not register r0.
I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig
(MPC85xx) that this patch results in the same machine code.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Ilias Apalodimas <ilias.apalodimas@linaro.org> says:
The LMB subsystem was used opportunistically for a number of years.
A while back Sughosh merged it with the EFI subsystem in order to have a
common allocator and avoid subsystems overwriting memory they shouldn't.
This is an initial cleanup of all the crud we gathered over the years.
There's no functional change expected from the patches as they just cleanup
some abstraction functions and rename a few variables to make more
sense.
I plan to make even bigger changes -- e.g I don't see the point of
having *_alloc() and *_reserve() versions of the functions since they
do the same thing and just cause confusion. lmb_alloc_addr_flags()
returning the base address on success makes little sense since we
already *request* the address on the function arguments, etc.
Since this patchset grew enough already, I'd like to get it in
before more refactoring happens.
It's worth noting that although some patches slightly increase the code
size due to an extra flags argument being carried around, the final
result is eventually smaller.
# qemu_arm64_lwip_defconfig (version string adds another 20b)
add/remove: 0/5 grow/shrink: 15/1 up/down: 568/-628 (-60)
Function old new delta
lmb_alloc_base 80 324 +244
lmb_alloc_addr 8 144 +136
lmb_reserve 8 96 +88
version_string 50 70 +20
boot_relocate_fdt 488 508 +20
boot_ramdisk_high 268 284 +16
lmb_add_region_flags 696 704 +8
boot_fdt_reserve_region 100 108 +8
load_serial 548 552 +4
lmb_alloc 8 12 +4
image_setup_libfdt 368 372 +4
do_load 728 732 +4
do_bootz 332 336 +4
do_booti 520 524 +4
bootm_run_states 2176 2180 +4
lmb_alloc_addr_flags 4 - -4
boot_fdt_add_mem_rsv_regions 284 280 -4
lmb_alloc_base_flags 76 - -76
lmb_reserve_flags 96 - -96
_lmb_alloc_addr 144 - -144
_lmb_alloc_base 304 - -304
Total: Before=1020102, After=1020042, chg -0.01%
# sandbox_defconfig (version string adds another 20b)
add/remove: 0/3 grow/shrink: 24/3 up/down: 523/-501 (22)
Function old new delta
lmb_alloc_base 48 299 +251
lmb_alloc_addr 4 92 +88
lmb_reserve 4 58 +54
test_alloc_addr 2933 2963 +30
version_string 50 70 +20
lib_test_lmb_overlapping_reserve 1018 1030 +12
lmb_add_region_flags 600 610 +10
test_multi_alloc.constprop 3034 3042 +8
test_get_unreserved_size 1032 1038 +6
boot_relocate_fdt 599 605 +6
boot_fdt_reserve_region 67 73 +6
lmb_alloc 4 9 +5
lmb_free_flags 190 194 +4
wget_handler 1530 1533 +3
tftp_handler 1190 1192 +2
test_noreserved 1207 1209 +2
test_bigblock 911 913 +2
load_serial 946 948 +2
lib_test_lmb_flags 2101 2103 +2
do_spi_flash 3150 3152 +2
do_bootz 526 528 +2
do_bootm_linux 2067 2069 +2
bootm_run_states 5275 5277 +2
_fs_read.lto_priv 331 333 +2
lmb_dump_region.lto_priv 356 353 -3
lmb_add 59 52 -7
efi_allocate_pages.part 303 249 -54
lmb_reserve_flags 65 - -65
_lmb_alloc_addr.lto_priv 92 - -92
_lmb_alloc_base.lto_priv 280 - -280
Total: Before=2492722, After=2492744, chg +0.00%
Link: https://lore.kernel.org/r/20241218070251.686383-1-ilias.apalodimas@linaro.org
lmb_alloc_addr_flags() is a wrapper for _lmb_alloc_addr() and it's the
only function using it. Rename _lmb_alloc_addr() to lmb_alloc_addr_flags()
and remove the wrapper.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
lmb_alloc_base() is just calling lmb_alloc_base_flags() with LMB_NONE.
There's not much we gain from this abstraction, so let's remove the
former add the flags argument to lmb_alloc_base() and make the code
a bit easier to follow.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
lmb_alloc_addr() is just calling lmb_alloc_addr_flags() with LMB_NONE
There's not much we gain from this abstraction, so let's remove the
latter, add a flags argument to lmb_alloc_addr() and make the code a
bit easier to follow.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
free_mem is a misnomer. We never update it with the free memory for
LMB. Instead, it describes all available memory and is checked against
used_mem to decide whether an area is free or not.
So let's rename this field to better match its usage.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
lmb_reserve() is just calling lmb_reserve_flags() with LMB_NONE.
There's not much we gain from this abstraction.
So let's remove the latter, add the flags argument to lmb_reserve()
and make the code a bit easier to follow.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
LMB flags is not an enum anymore. It's currently used as a bitmask
in various places of our code. So make it a u32 which is more
appropriate when dealing with masks.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Fix warnings from kernel-doc script. Improve and unify overall style of
kernel-doc comments in lmb source files. Move all kernel-doc comments
for public functions into the header, as recommended in U-Boot
documentation [1]:
Non-trivial functions should have a comment which describes what
they do. If it is an exported function, put the comment in the
header file so the API is in one place. If it is a static function,
put it in the C file.
This also takes care of existing duplication. While at it, do a bit of
cosmetic cleanups as well.
No functional change.
[1] doc/develop/codingstyle.rst
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
flag_str[] is a pointer to const. Make it also a const pointer. Improve
a style a bit while a it, to make this line fit 80 characters limit.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
rgnflags variable in lmb_add_region_flags() has incorrect type: it's
declared as phys_size_t when it should be enum lmb_flags. That
copy-paste mistake was firstly introduced in commit 59c0ea5df3 ("lmb:
Add support of flags for no-map properties"), and then copied further
into commit ed17a33fed ("lmb: make LMB memory map persistent and
global"). Fix it by using the correct type to match struct lmb_region
field.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Update the spi_nor_read() function based on the config SPI_FLASH_BAR
and update the length and bank calculation by spliting the memory of
16MB size banks only when the address width is 3byte.
Fix the read issue for 4byte address width by passing the entire
length to the read function.
Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Add support for mapping C22 register access to C45-only PHYs.
This is mainly useful for 'mii info' command, which performs
C22 only access to determine PHY ID and link state and does
not work well with this driver so far.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Implement C22 PHY access support in addition to C45 PHY access
support which is already present. This is used for PHYs which
do not support C45 access or which are C22 only.
The C22 access can be recognized when devad is set to -1 or
0xffffffff hex, which also matches MDIO_DEVAD_NONE macro. Test
for this special devad value and if it is set this way, perform
C22 access, otherwise perform C45 access.
Based on work by LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The Set Station Management Mode : Clause 45 setting of MFF bit in MPSM
register can be done in rswitch_mii_access_c45() once, instead of this
being done before each rswitch_mii_access_c45() call. Deduplicate the
bit setting into rswitch_mii_access_c45(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Replace enum rswitch_reg with plain #define REGISTER OFFSET macros.
The enum rswitch_reg was not referenced anywhere, so there was no
benefit of keeping it around. Include register block labels. Turn
all register offsets into lowercase hex values. No functional change.
Rename EATDQDC to EATDQDCR, GWTRC to GWTRCR, GWDCC to GWDCCR, FWPC0
to FWPC, FWPBFC to FWPBFCR, FWPBFCSDC to FWPBFCSDCR because there
are both register names which used to be part of this enum and also
macros with the same name, each used for slightly different purpose.
Make sure there is no collission.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Enable remoteproc command and APMU remoteproc driver to start Cortex-R52
cores from U-Boot command line. Code on the Cortex-R52 #0 can be started
as follows, code on other cores can be started by passing the correct ID
to 'rproc load' and 'rproc start' to select the core:
"
=> rproc init
=> rproc list
0 - Name:'rcar-apmu-cr52.0-apmu@e6170000' type:'internal memory mapped' supports: load start stop reset is_running
1 - Name:'rcar-apmu-cr52.1-apmu@e6170000' type:'internal memory mapped' supports: load start stop reset is_running
2 - Name:'rcar-apmu-cr52.2-apmu@e6170000' type:'internal memory mapped' supports: load start stop reset is_running
=> rproc load 0 0xeb200000 0x10000
Load Remote Processor 0 with data@addr=0xeb200000 65536 bytes: Success!
=> rproc start 0
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Describe APMU controller as a remoteproc device capable of starting
the Cortex-R52 cores in Renesas R8A779G0 V4H SoC DT. The APMU IP is
in fact a power management unit capable of additional operations, but
those are not used by U-Boot so far.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add R-Car Gen4 APMU controller remoteproc driver capable of starting
the Cortex-R52 cores in Renesas R8A779G0 V4H/V4M SoC. The APMU IP is
in fact a power management unit capable of additional operations, but
those are not used by U-Boot so far.
This requires slight adjustment to the SPL entry point code, as that
is being executed on the Cortex-R52 #0 and the Cortex-R52 #0 enters an
endless loop once it starts the rest of the SPL on Cortex-A76 core.
The endless loop now checks for content of APMU CRBARP registers and
tests whether valid VLD_BARP and BAREN_VALID bits are set, if so, the
Cortex-R52 core exits the endless loop and jumps to address started
in CRBARP[31:18] register in ARM mode, which is a trampoline code to
jump to the final entry point.
The trampoline code is in place to avoid limitation of CRBARP[31:18]
address field, which limits the core start address to memory addresses
aligned to 0x40000 or 256 kiB . The trampoline is placed at 0x40000
aligned address and jumps to the final entry point, which can be at
an address with arbitrary alignment at instruction granularity.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This DTC_FLAGS assignment is no longer necessary as all R-Car Gen2/Gen3/Gen4
platforms have been converted to OF_UPSTREAM and matching DTC_FLAGS assignment
is present in dts/upstream/src/arm64/Makefile . Drop the remnant.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Align R-Car Gen2/Gen3/Gen4 configuration header file to look
basically the same way across these three SoC generations.
There are subtle difference between the remaining bits in
those files across SoC generations, but the common bits are
now aligned. There is not much left in those headers either,
most of the configuration is now converted to Kconfig.
Specifically for R-Car Gen3, GIC registers have been moved
to architecture specific header file rcar-gen3-base.h , the
rest of the changes here are comment changes and indentation
changes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC.
The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts
U-Boot proper on the Cortex-A76 core.
The SoC BootROM can not boot the CA76 core directly, instead the SPL starts
on the CR52 core which immediately brings up the CA76 core, which in turn
starts executing the actual SPL. This is achieved by placing a tiny bit of
precompiled Aarch32 code at the very beginning of the SPL. The code consists
of some 32 instructions, uses APMU to configure CA76 start address to offset
0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The
code parts the CR52 core in an endless loop once the CA76 core got started.
The 32 instructions are completely arbitrary number, so is the offset 0x80
Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per
instruction is 32 instructions. The 32 instructions turned out to be enough
to started the CA76 and 0x80 is nicely aligned.
Once the SPL completes hardware initialization, the SPL loads U-Boot proper.
The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and
a DT for R8A779G0 V4H White Hawk board and is generated by binman. The
u-boot.itb is loaded from SPI NOR offset 0x80000.
In order to install this setup on an existing R8A779G0 V4H White Hawk board,
build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin
and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin
switches according to the R8A779G0 V4H White Hawk board documentation for
40 MHz SPI NOR boot using DMA and restart the board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
In case U-Boot runs in EL3, which is the highest privilege level on ARM64,
there can be no firmware running that would restrict access to the bottom
128 MiB of DRAM. In fact, it is likely that U-Boot would have to load that
firmware into those bottom 128 MiB of DRAM and start that firmware.
Make those bottom 128 MiB of DRAM available in case U-Boot runs in EL3 to
allow loading the firmware to that area.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Split common board code for R-Car Gen3 and Gen4 into separate files.
The R-Car Gen3 board code contains fixups specific to TFA which are
no longer required on R-Car Gen4, keep those fixups in its own file
so they would not interfere with Gen4.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
All R-Car Gen4 board files are copies of one another at this point.
Deduplicate them into single board/renesas/rcar-common/gen4-common.c
and remove all the duplicates. The one exception is R-Car V3U Falcon
board, which enables RWDT reset in board_init(), conditionally build
RWDT enablement in board_init() in the new common code for V3U.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Make the R-Car V3U stub PSCI implementation available on 64bit R-Car SoCs.
This implementation is useful during early board bring up, where it can
supplant missing fully-featured PSCI implementation. Note that this PSCI
implementation is very basic and offers only SoC reset functionality. It
is unable to enable or disable secondary CPU cores nor does it offer any
suspend/resume functionality.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Describe DBSC5 DRAM controller and RT-VRAM configuration interface
as two new DT nodes in R-Car Gen4 R8A779G0 U-Boot DT extras file.
This node is used by the U-Boot SPL for R8A779G0 SoC, where the
DBSC5 and RT-VRAM drivers bind to these nodes and bring up the
DRAM controller and RT-VRAM settings respectively, so U-Boot
proper can be loaded into DRAM and started on Cortex A76 core.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add Renesas R-Car Gen4 DBSC5 DRAM controller driver. This driver is currently
capable of bringing LPDDR5 DRAM on Renesas R-Car V4H Whitehawk board. Further
boards can be supported by supplying board specific DRAM configuration data
via dbsc5_get_board_data(). Support for R-Car V4M is not implemented, however
the driver is already mostly prepared to support this SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Use the IS_ENABLED() macro to reduce amount of #ifdef use in the driver
and improve code coverage. With IS_ENABLED() macro, the code is compiled
and then optimized out, which prevents bitrot.
In case no PFC table matches the SoC in use, do not probe the driver
and instead exit with -ENODEV. This should never happen under normal
conditions, because this would mean the driver DT compatible string
match happened, but the list in probe() cannot match the model listed
in match data associated with the compatible string on which the match
did happen.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:
Legacy TCP stack is bad. Here are some of the known issues:
* tcp packet from other connection can break a current one
* tcp send sequence always starts from zero
* bad tcp options processing
* strange assumptions on packet size for selective acknowledge
* tcp interface assumes one of the two scenarios:
- data downloading from remote host to a board
- request-response exchange with a small packets
so it's not possible to upload large amount of data from the
board to remote host.
* wget test generate bad tcp stream, test should fail but it passes instead
This series of patches fixes all of the above issues.
The benefits:
* A lot of bug was fixed
* Better and more reliable TCP state machine
* Tcp clients becomes smaller/simpler
* Data uploading was fixed (now it's possible to transmit a huge amount of
data from the board to remote host)
Modification was verified with
* firmware downloading via u-boot wget command
* fastboot over tcp
* netcat linux client using test netcat implementation (not included
to this patch series)
* Firefox/Chrome/Edge using test web-server implementation (not included
to this patch series)
[trini: snip]
WARNING: The v16 patch series does NOT fix lib/efi_selftest/efi_selftest_http.c
issue. It looks like the efi_selftest_http test is wrong by itself. The
following issues were detected during efi_selftest_http test study:
* The test should fail with HTTP status code 404 because:
* nowday most web-servers requires the presence of "HOST:" request header
* wget does not support sending "HOST:" request header
* web-server of "http://example.com/" site does NOT provide "default server"
configuration, so it answer 404 on any request without "HOST:" header.
* The test states that:
* test send HTTP HEAD request to a server,
* then test send HTTP GET request to a server,
* reads the actual bytes sent by the server and compare it with
the value from "Contents-Length:" responce header of the HEAD request
But actually it
* does not send HTTP HEAD request, only a single HTTP GET request
is performed
* the test reads the responce twice from the same request. It looks
very suspictiuos
Link: https://lore.kernel.org/r/20241228104637.4173913-1-mikhail.kshevetskiy@iopsys.eu
