Commit Graph

98985 Commits

Author SHA1 Message Date
Simon Glass
4c6774c606 test/py: Add a helper to send characters
The existing run_command() method is not great for sending things other
than U-Boot commands. Add a helper for sending arbitrary strings as well
as control characters.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-04-03 11:41:55 -06:00
Simon Glass
0b9e517aaf test/py: Correct sizing of created disks
At present the disks end up being 1MB shorter than they should be,
since dd truncates by default.

Move the code into a function and update it to avoid truncation.

This resolves various warnings when running sandbox tests, of the form:

   mmc_bread() MMC: block number 0x9801 exceeds max(0x9800)

caused by the FAT partition being scanning.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
b23f0a42c3 x86: qemu: Support environment and cat command
Add support for an environment stored in the first partition of the
disk, which is assumed to hold a FAT filesystem.

Support the 'cat' command as it is useful for looking at extlinux.conf
files.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
790baef3b9 x86: emulation: Set an MTRR for the RAM
QEMU likes to have an MTRR set up, just like real machines. Add an MTRR
which covers the total RAM size.

This does nothing on machines without MTRRs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
66c9ade35b x86: Allow adding non-aligned size for MTRR
At present mtrr_add_request() requires that the size is a power of two.
This is too limiting for machines with 4GB (or more) of RAM, since they
often must take account of a memory hole at 3GB.

Update the function to automatically deal with an unaligned size, using
more MTRRs as required.

The algorithm is taken from coreboot commit 60bce10750

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
a9d106421d x86: Correct msr operation on amd64
The CONFIG option is no-longer correct since we can have SPL and PPL
with different bitness.

Fix this and sync up with Linux 6.13 in this area, since this is where
the code came from many years ago.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
21feb3404e x86: Update cpuid_eax et al to work on amd64
The existing functions work but the register clobbers are wrong, so
strange bugs results.

The original functions were taken from a very old version of Linux.
Update them from Linux 6.13

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
5450836115 x86: Update mtrr command to support 64-bit values
The MTRR registers have 64-bit values. Update the command to use 64-bit
values so that memory larger than 4GB can be handled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
8bd563707d x86: Add functions to convert between mtrr size and mask
Rather than repeating the same code in several places, add some
functions which can do the conversion.

Use the cpu_phys_address_size() function to obtain the physical-address
size, since it is more reliable with kvm, where the host CPU may have a
different value from the emulation CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
5ee60f3afa x86: Support CPU functions in long mode
At present it is not possible to find out the physical-address size in
long mode, so a predefined value is used.

Update the macros to support this properly, since it is important when
programming MTRRs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
b4a3ebe304 x86: Rename the _D dirty flag
This value happens to be used by ctype.h so chose a different name.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
ffd92a25be x86: Use a simple jump into long mode
With the 64-bit descriptor we can use a jump instruction, rather than
pushing things on the stack.

Since the processor is in 64-bit mode by this point, pop a 64-bit value
from the stack, containing the target address.

This simplifies the code slightly, in particular its use of the stack.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
f5b1c643b4 x86: Use the same GDT when jumping to long mode
Make use the existing GDT which now includes entries for 64-bit code.
Leave the interrupt descriptors alone. They can be tidied up once U-Boot
starts up.

With this, kvm mode works with QEMU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/31
2025-04-03 11:41:55 -06:00
Simon Glass
f5f1ed8ae7 x86: Disable paging before changing to long mode
This is required as part of the procedure. The existing code works
because it changes the GDT at the same time, but this makes kvm
unhappy.

Update the algorithm to disable and then re-enable paging.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
3c7ab12249 x86: Tidy up the GDT size in start/16.S
Use a symbol to select the size of the GDT, rather than hard-coding a
value. This matches how it is done in start64

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
aae07e3df8 x86: Include stdbool.h in interrupt header
This makes use of a 'bool' type, so include the required header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
1111d92360 x86: Drop the message about features missing in 64-bit
This functions normally and has done for a while, so drop this scary
message.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
e93da0399c x86: spl: Drop duplicate CPU init
x86_cpu_init_f() is called by arch_cpu_init() a few lines below this
code. Drop the duplicate call.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
912e32d34f x86: Use defines for the cache flags
Use some named flags when setting up the cache, so it is easier to see
what is going on.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
66f0dcb07f x86: Add 64-bit entries to the GDT
At present it is not possible to execution 64-bit code without
installing an entire new Global Descriptor Table. This is inconvenient
since kvm does not seem to like switching into long mode with a new
table.

It isn't actually necessary, since we can just extend the existing
table. Add some new entries to this effect.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
899ab6cd52 x86: Avoid clearing the VESA display
U-Boot clears the display when it starts up, so there is no need to ask
the VESA driver to do this. Fix this and add a comment explaining the
flags.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
a9ba0080db x86: Drop use of CONFIG_REALMODE_DEBUG
This option is not actually defined in Kconfig anymore. Use a normal
debug print instead, which has a similar effect.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-04-03 11:41:55 -06:00
Simon Glass
22c434b0fb x86: Add some log categories
Add categories for i8259 and bios files, so that log statements have the
right category.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
05b8f8a95d x86: Drop mpspec from the SPL build
This is not needed in SPL, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
6f18c59315 x86: qemu: Avoid accessing BSS too early
BSS is placed in DRAM which is actually available early with QEMU. But
it is cleared by the init sequence, so values stored there are lost.

Move the system-type flag into a function, instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
6f30ae6cd6 x86: qemu: Enable dhrystone
Provide the 'dhry' command, which helps to check that kvm is being used
properly with QEMU.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:55 -06:00
Simon Glass
515d4ee339 x86: qemu: Switch to bochs display
The vesa display is widely used on hardware, but it is a bit of a pain
with QEMU. It requires executing option ROMs, which either doesn't work
with kvm, or is difficult to do in a kvm/QEMU-friendly way.

THe bochs display is probably better anyway, so switch to that. It works
fine with kvm as it doesn't need an option ROM.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/31
2025-04-03 11:41:55 -06:00
Simon Glass
e95bc5e929 x86: Expand x86_64 early memory
The SPL and pre-reloc malloc()-space is not large enough to start up
with a display. Expand it.

Switch the order of SPL_SYS_MALLOC_F_LEN and SPL_TEXT_BASE since this
matches what 'savedefconfig' gives us.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:54 -06:00
Simon Glass
96aa0719b7 sandbox: Correct a typo in mapmem
This should say 'cast', not 'case', so fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-04-03 11:41:54 -06:00
Tom Rini
39ff722b3e Merge patch series "acpi_table: Fix IORT RC node"
This series from Patrick Rudolph <patrick.rudolph@9elements.com> brings
in an assortment of ACPI related fixes.

Link: https://lore.kernel.org/r/20250316083300.2692377-1-patrick.rudolph@9elements.com
2025-04-03 11:38:22 -06:00
Patrick Rudolph
636b62c265 test: acpi: Add IORT tests
Add tests for IORT table generation:
- SMMU_V3 node
- RC node

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2025-04-03 11:38:14 -06:00
Patrick Rudolph
9c74857640 acpi: Conditionally set mapping_offset in IORT
The spec recommends to set the mapping_offset only when there are
ID mappings as indicated by the mapping_count field.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2025-04-03 11:38:14 -06:00
Patrick Rudolph
fe8844f4ad acpi: Clear reserved bits in IORT
The IORT spec says that reserved bits must be set to zero, thus clear
all fields of the struct before starting to fill out non-reserved
fields.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2025-04-03 11:38:14 -06:00
Patrick Rudolph
0ae343239b acpi_table: Add asserts in IORT
Check that the provided offsets are really pointing to a node
that have been previously written and are of the correct type.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2025-04-03 11:38:14 -06:00
Patrick Rudolph
92d448f4f1 acpi_table: Fix IORT RC node
Even though the RC node has the correct size and the ID mappings
are written to the end of the node, the ID 'mapping offset' and
'mapping count' are not written in the IORT RC node header, thus it
looks like that the RC node has no ID mappings.
The Linux kernel doesn't complain about the invalid IORT RC node,
even though the spec says that each RC node must have an ID mapping.
The kernel will fail to use MSI IRQs and fall back to a legacy IRQ
mechanism that's not working either.
Finally it will show strange behaviour around PCI interrupts, making it
hard to trace back to an invalid IORT RC nodes.

Add the missing ID mapping count and mapping offset.

TEST: Fixes IRQ usage of PCI devices on qemu/sbsa-ref.
Fixes: bf5d37662d "acpi: acpi_table: Add IORT support"

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2025-04-03 11:38:14 -06:00
Tom Rini
ccb3826054 Merge patch series "Introduce J742S2 SoC and EVM"
Manorit Chawdhry <m-chawdhry@ti.com> says:

The series adds support for J742S2 family of SoCs. Also adds J742S2 EVM
Support and re-uses most of the stuff from the superset device J784s4.

This device is a subset of J784S4 and shares the same memory map and
thus the code is being reused from J784S4 to avoid duplication.

It initially cleans up the J784s4 and AM69 files so that they can be
re-usable for j742s2 and then it introduces J742S2.

The DT for the following SoC will be coming to U-boot during 6.13 Sync
so the series is kept as RFC till then.

Here are some of the salient features of the J742S2 automotive grade
application processor:

The J742S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive, ADAS and industrial
applications requiring AI at the network edge. This SoC extends the K3
Jacinto 7 family of SoCs with focus on raising performance and
integration while providing interfaces, memory architecture and compute
performance for multi-sensor, high concurrency applications.

Some changes that this devices has from J784S4 are:
* 4x Cortex-A72 vs 8x Cortex-A72
* 3x C7x DSP vs 4x C7x DSP
* 4 port ethernet switch vs 8 port ethernet switch
* 2 DDR controller vs 4 DDR controller

Test logs:
https://gist.github.com/manorit2001/f7df0e8cca1e9973b4361f0559c6f53d

Link: https://lore.kernel.org/r/20250317-b4-upstream-j742s2-v4-0-4ba88bfd357a@ti.com
2025-04-03 11:37:57 -06:00
Manorit Chawdhry
fe36b22c32 configs: Introduce configs for J742S2
Based off j784s4 configs with delta changes for J742S2

[ Add AVS support for J742S2 ]

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-04-03 11:37:46 -06:00
Manorit Chawdhry
45d056e275 arm: dts: Introduce J742S2 U-boot DTS files
Include the U-boot device tree files needed to boot the board.

[ DDR config ]

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-04-03 11:37:46 -06:00
Manorit Chawdhry
4c31c0a4dd board: ti: Introduce basic board files for the J742S2 family
Introduce the basic files needed to support the TI J742S2 family of SoCs.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-04-03 11:37:46 -06:00
Manorit Chawdhry
dd837d6c88 arm: mach-k3: j742s2: Introduce clock and device files for J742S2 SoC
Re-use j784s4 clocks and power domains for j742s2 family of device.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-04-03 11:37:46 -06:00
Manorit Chawdhry
201b08702e soc: Add information to identify the J742S2 SoC family
J742S2 has the same part number as J784S4 but JTAG_DEVICE_ID has a
PKG bit that tells about J742S2.

Add support for reading JTAG_DEVICE_ID and set family as J742S2 based
on that.

Link: https://www.ti.com/lit/pdf/spruje3 (TRM)
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-04-03 11:37:46 -06:00
Manorit Chawdhry
61b6b2fcc9 arm: dts: k3-j784s4-ddr: Refactor J784s4 ddr file to a common file
Refactor J784s4 ddr file to a common file which uses the
superset device to allow reuse in j742s2-evm which uses the subset part.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-04-03 11:37:45 -06:00
Neha Malcom Francis
9e1295917e arm: dts: k3-j784s4-binman.dtsi: Clean up and templatize boot binaries
Clean up templatized boot binaries for j784s4 soc. This includes
modifying the k3-j784s4-binman.dtsi to use SPL_BOARD_DTB,
BOARD_DESCRIPTION and UBOOT_BOARD_DESCRIPTION from the files that
include it to further reuse code.

k3-j784s4-binman.dtsi will contain only templates. Only required boot
binaries can be built from the templates in the boards' respective
-u-boot.dtsi file (or k3-<board>-binman.dtsi if it exists). This allows
clear distinction between the SoC common stuff vs. what is additionally
needed to boot up a specific board.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
[ Do it only for j784s4 ]
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-04-03 11:37:45 -06:00
Neha Malcom Francis
42ce9ed7ff tools: binman: control.py: Delete template nodes after parsing
Dynamically going through the subnode array and deleting leads to
templates being skipped from deletion when templates are consecutive in
the subnode list. Prevent this from happening by first parsing the DT
and then deleting the nodes. Add a testcase as well for this cornercase.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-04-03 11:37:45 -06:00
Tom Rini
82b69fc422 Merge tag 'efi-2025-04-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2025-04-rc6

CI:

* https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/25491

Documentation:

* correct references to overlay-fdt-boot.txt
* build: docker: Fix code highlighting syntax
* build: docker: Use code-block for syntax highlighting
* Fix typo bootfloe to bootflow

UEFI:

* Correct the size of the AcpiReclaimMemory region for ACPI tables
  when using QFW
2025-04-03 07:31:28 -06:00
Tom Rini
ce09def8ab Merge tag 'u-boot-at91-fixes-2025.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2025.04 cycle:

- A single fix for the reset command on sama5d27 boards.
2025-04-03 07:27:33 -06:00
Andrew Davis
7871285a0a doc: Fix typo bootfloe to bootflow
Signed-off-by: Andrew Davis <afd@ti.com>
2025-04-03 09:06:51 +02:00
Heinrich Schuchardt
e66148060f doc: correct references to overlay-fdt-boot.txt
doc/uImage.FIT/overlay-fdt-boot.txt does not exist anymore.
Reference the correct section of doc/usage/fit/overlay-fdt-boot.rst.

Fixes: 6f6e8bb695 ("doc: Bring in the FIT overlay information")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-04-03 09:05:29 +02:00
Leonard Anderweit
4738e306fd doc: build: docker: Use code-block for syntax highlighting
Use ..code-block:: syntax highlighting instead of :: so all bash
commands use the same syntax highlighting.

Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-04-03 09:04:35 +02:00
Leonard Anderweit
e763c19507 doc: build: docker: Fix code highlighting syntax
Remove double :: before .. code-block:: bash to correctly highlight the
following commands.

Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-04-03 09:04:35 +02:00