Kever Yang
08516431cf
rockchip: clk: rk3328: convert to use live dt
...
Use live dt api to get cru base addr.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2018-03-13 18:12:35 +01:00
David Wu
7cd4ebab2b
clk: rockchip: Add rk3328 gamc clock support
...
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Signed-off-by: David Wu <david.wu@rock-chips.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2018-01-28 17:12:37 +01:00
Elaine Zhang
538f67c332
rockchip: clk: bind reset driver
...
Bind rockchip reset to clock-controller with rockchip_reset_bind().
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com >
Signed-off-by: Kever Yang <kever.yang@rock-chips.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2018-01-09 11:13:32 +01:00
Kever Yang
f24e36dac3
rockchip: clock: update sysreset driver binding
...
Using priv for new sysreset driver binding.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2017-11-21 23:57:23 +01:00
David Wu
b375d84135
rockchip: clk: Add rk3328 SARADC clock support
...
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2017-10-01 00:33:30 +02:00
Kever Yang
3a94d75d0e
rockchip: clk: update dwmmc clock div
...
dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting
Signed-off-by: Kever Yang <kever.yang@rock-chips.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2017-08-13 17:15:09 +02:00
Simon Glass
a821c4af79
dm: Rename dev_addr..() functions
...
These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.
In the end we will have:
1. dev_read_addr...() - works on devices, supports flat/live tree
2. devfdt_get_addr...() - current functions, flat tree only
3. of_get_address() etc. - new functions, live tree only
All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.
Note this involves changing some dead code - the imx_lpi2c.c file.
Signed-off-by: Simon Glass <sjg@chromium.org >
2017-06-01 07:03:01 -06:00
Xu Ziyuan
85c91cb694
rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC
...
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com >
Acked-by: Simon Glass <sjg@chromium.org >
2017-05-10 13:37:21 -06:00
Kever Yang
41793000d7
rockchip: rk3328: add clock driver
...
Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang <william.zhang@rock-chips.com >
Signed-off-by: Kever Yang <kever.yang@rock-chips.com >
2017-03-16 16:03:46 -06:00
