Kever Yang
bbfef40f92
rockchip: clk: rk1108: convert to use live dt
...
Use live dt api to get cru base addr.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2018-03-13 18:12:35 +01:00
Elaine Zhang
538f67c332
rockchip: clk: bind reset driver
...
Bind rockchip reset to clock-controller with rockchip_reset_bind().
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com >
Signed-off-by: Kever Yang <kever.yang@rock-chips.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2018-01-09 11:13:32 +01:00
Kever Yang
f24e36dac3
rockchip: clock: update sysreset driver binding
...
Using priv for new sysreset driver binding.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2017-11-21 23:57:23 +01:00
Masahiro Yamada
9b643e312d
treewide: replace with error() with pr_err()
...
U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:
# define __compiletime_error(message) __attribute__((error(message)))
This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)
Let's convert error() into now treewide-available pr_err().
Done with the help of Coccinelle, excluing tools/ directory.
The semantic patch I used is as follows:
// <smpl>
@@@@
-error
+pr_err
(...)
// </smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com >
Reviewed-by: Simon Glass <sjg@chromium.org >
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com >
2017-10-04 11:59:44 -04:00
David Wu
2e4ce50d1a
rockchip: clk: Add rv1108 SARADC clock support
...
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2017-10-01 00:33:29 +02:00
Kever Yang
217273cd44
rockchip: clk: remove RATE_TO_DIV
...
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com >
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
2017-08-13 17:15:09 +02:00
Tom Rini
872faf5d13
clk_rv1108.c: Fix unused variable warning
...
The variables gpll_init_cfg and apll_init_cfg are unused in this file,
remove them.
Cc: Simon Glass <sjg@chromium.org >
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com >
Signed-off-by: Tom Rini <trini@konsulko.com >
Reviewed-by: Simon Glass <sjg@chromium.org >
2017-06-23 10:38:05 -04:00
Andy Yan
bae2f282a9
rockchip: clk: Add rv1108 clock driver
...
Add clock driver support for Rockchip rv1108 soc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com >
Reviewed-by: Simon Glass <sjg@chromium.org >
2017-06-07 07:29:25 -06:00
