Marek Vasut
be324354ee
arm: socfpga: Clean up base address file
...
Sort the list of functional block addresses and fix indentation.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Chin Liang See <clsee@altera.com >
Cc: Dinh Nguyen <dinguyen@altera.com >
Cc: Albert Aribaud <albert.u.boot@aribaud.net >
Cc: Tom Rini <trini@ti.com >
Cc: Wolfgang Denk <wd@denx.de >
Cc: Pavel Machek <pavel@denx.de >
Acked-by: Pavel Machek <pavel@denx.de >
Acked-by: Chin Liang See <clsee@altera.com >
2014-10-06 17:46:48 +02:00
Pavel Machek
e1f006f438
arm: socfpga: Complete the list of base addresses
...
Add base addresses for all subsystems as documented in the
Cyclone V HPS documentation.
Signed-off-by: Pavel Machek <pavel@denx.de >
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Chin Liang See <clsee@altera.com >
Cc: Dinh Nguyen <dinguyen@altera.com >
Cc: Albert Aribaud <albert.u.boot@aribaud.net >
Cc: Tom Rini <trini@ti.com >
Cc: Wolfgang Denk <wd@denx.de >
Cc: Pavel Machek <pavel@denx.de >
Acked-by: Chin Liang See <clsee@altera.com >
2014-10-06 17:46:48 +02:00
Pavel Machek
99b97106f3
socfpga: initialize designware ethernet
...
Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environment.
Signed-off-by: Pavel Machek <pavel@denx.de >
2014-08-30 07:46:38 -04:00
Chin Liang See
dc4d4aa14b
socfpga: Adding Scan Manager driver
...
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See <clsee@altera.com >
Cc: Dinh Nguyen <dinguyen@altera.com >
Cc: Wolfgang Denk <wd@denx.de >
CC: Pavel Machek <pavel@denx.de >
Cc: Tom Rini <trini@ti.com >
Cc: Albert Aribaud <albert.u.boot@aribaud.net >
2014-07-05 00:27:27 +02:00
Chin Liang See
05b884b5cd
socfpga: Adding DesignWare watchdog support
...
To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.
Signed-off-by: Chin Liang See <clsee@altera.com >
Cc: Anatolij Gustschin <agust@denx.de >
Cc: Albert Aribaud <albert.u.boot@aribaud.net >
Cc: Heiko Schocher <hs@denx.de >
Cc: Tom Rini <trini@ti.com >
2014-07-05 00:24:18 +02:00
Chin Liang See
ddfeb0aaf4
socfpga: Adding Clock Manager driver
...
Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files
Signed-off-by: Chin Liang See <clsee@altera.com >
Cc: Albert Aribaud <albert.u.boot@aribaud.net >
Cc: Tom Rini <trini@ti.com >
Cc: Wolfgang Denk <wd@denx.de >
CC: Pavel Machek <pavel@denx.de >
Cc: Dinh Nguyen <dinguyen@altera.com >
Acked-by: Pavel Machek <pavel@denx.de >
2014-04-07 10:41:50 +02:00
Chin Liang See
5d649d2b08
socfpga: Adding System Manager driver
...
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See <clsee@altera.com >
Reviewed-by: Pavel Machek <pavel@denx.de >
Acked-by: Dinh Nguyen <dinguyen@altera.com >
Cc: Wolfgang Denk <wd@denx.de >
CC: Pavel Machek <pavel@denx.de >
Cc: Dinh Nguyen <dinguyen@altera.com >
Cc: Tom Rini <trini@ti.com >
Cc: Albert Aribaud <albert.u.boot@aribaud.net >
2013-10-07 19:32:21 +02:00
Wolfgang Denk
1a4596601f
Add GPL-2.0+ SPDX-License-Identifier to source files
...
Signed-off-by: Wolfgang Denk <wd@denx.de >
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com >
2013-07-24 09:44:38 -04:00
Dinh Nguyen
777544085d
ARM: Add Altera SOCFPGA Cyclone5
...
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com >
Signed-off-by: Chin Liang See <clsee@altera.com >
Signed-off-by: Pavel Machek <pavel@denx.de >
Reviewed-by: Marek Vasut <marex@denx.de >
Acked-by: Tom Trini <trini@ti.com >
Cc: Wolfgang Denx <wd@denx.de >
Cc: Albert Aribaud <albert.u.boot@aribaud.net >
Cc: Stefan Roese <sr@denx.de >
----
v8: Remove no_return attribute for reset_cpu
Based on v2012.10-rc2
2012-10-04 18:11:52 +02:00
