Commit Graph

408 Commits

Author SHA1 Message Date
Tom Rini
47e544f576 Merge patch series "Tidy up use of 'SPL' and CONFIG_SPL_BUILD"
Simon Glass <sjg@chromium.org> says:

When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL

Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.

For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:

   #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)

In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.

This series starts a change in terminology and usage to resolve the
above issues:

- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
  'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
  defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_

It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.

This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.

The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
2024-10-11 12:23:25 -06:00
Simon Glass
c46760d596 global: Rename SPL_ to XPL_
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:48 -06:00
Bhupesh Sharma
62130bc0cb phy: qcom: Add QMP UFS PHY driver
Add Qualcomm QMP UFS PHY driver which is available on the following
Snapdragon SoCs - SDM845, SM8250, SM8550 and SM8650 SoCs.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-10-04 14:57:02 +02:00
Bhupesh Sharma
b4256b5dca phy: qcom: Import QMP phy related header files from Linux
Import Qualcomm QMP phy related header files from Linux v6.11-rc7,
limit to headers needed to setup QMP v2 to v6 UFS PHYs.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-10-04 14:57:02 +02:00
Tom Rini
3a0b829efc Merge tag 'v2024.10-rc6' into next
Prepare v2024.10-rc6
2024-09-30 17:48:12 -06:00
Roger Quadros
28a4e43149 phy: cadence: sierra: Don't spam console
use dev_dbg() instead of dev_info() for debug related
prints.

Get's rid of below print from console.

"cdns,sierra serdes@5030000: sierra probed"

Signed-off-by: Roger Quadros <rogerq@kernel.org>
2024-09-20 09:09:42 -06:00
Marek Vasut
e72e683e36 phy: test: Implement sandbox PHY .set_mode and DM test
Implement trivial extension to the sandbox PHY, which makes it pretend
to support selecting USB Host mode and nothing else. Any other mode is
rejected with -EINVAL. Any submode except for default submode 0 is
rejected with -EOPNOTSUPP . The implementation behaves in this trivial
way to permit easy unit testing using test which is also added in this
commit.

To run the test, use e.g. sandbox64_defconfig and run U-Boot as follows:
$ ./u-boot -Tc 'ut dm phy_setup'

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-09-09 17:18:04 +02:00
Marek Vasut
a1f841a33c phy: rcar: Split init and set_mode operations
The current init operation also sets the PHY into USB host mode.
Split the mode configuration into set_mode callback instead and
implement support for device and OTG modes as well.

The OTG mode performs auto-detection and selects either host or
device mode. In case the OTG mode is configured, submode field
can be used to select full PHY (re)initialization or only mode
auto-detection. The full (re)initialization is only necessary
once, on start up.

Since the OTG mode may enable IRQ generation in the PHY, disable
that IRQ generation in the exit callback again.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-09-09 17:18:04 +02:00
Marek Vasut
35941d3a96 phy: Extend generic_setup_phy() with PHY mode and submode
Extend generic_setup_phy() parameter list with PHY mode and submode and
call generic_phy_set_mode() in generic_setup_phy(), so the generic PHY
setup function can configure the PHY into correct mode before powering
the PHY up.

Update all call sites of generic_setup_phy() as well, all of which are
USB host related, except for DM test which now behaves as a USB host
test.

Note that if the PHY driver does not implement the .set_mode callback,
generic_phy_set_mode() call returns 0 and does not error out, so this
should not break any existing systems.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-09-09 17:18:04 +02:00
Sebastian Kropatsch
0cb1fddb74 phy: rockchip: naneng-combphy: Introduce PHY-IDs to fix RK3588 muxing
Fix multiplex configuration for PCIe1L0 and PCIe1L1 in PCIESEL_CON for
RK3588 to correctly select between Combo PHYs and PCIe3 PHY.
Currently, the code incorrectly muxes both ports to Combo PHYs,
interfering with PCIe3 PHY settings.
Introduce PHY identifiers to identify the correct Combo PHY and set
the necessary bits accordingly.

This fix is adapted from the upstream Linux commit by Sebastian Reichel:
d16d4002fea6 ("phy: rockchip: naneng-combphy: Fix mux on rk3588")

Fixes: b37260bca1 ("phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
2024-08-09 18:35:22 +08:00
Marek Vasut
c94a0359c9 drivers: phy: Remove duplicate newlines
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-07-22 10:53:05 -06:00
Sebastian Kropatsch
9a48ec3e91 phy: rockchip: snps-pcie3: Fix clearing PHP_GRF_PCIESEL_CON bits
The pcie1ln_sel bits for the RK3588 are getting set but not cleared due
to an incorrect write mask.
Use a newly introduced constant for the write mask to fix this.
Also introduce a GENMASK-based constant for PCIE30_PHY_MODE.

This fix is adapted from the upstream Linux commit by Sebastian Reichel:
55491a5fa163 ("phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON bits")

Fixes: 50e54e8067 ("phy: rockchip: snps-pcie3: Add support for RK3588")
Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-07-17 14:48:18 +08:00
Sebastian Kropatsch
ee84a18b3d phy: rockchip: snps-pcie3: Fix bifurcation for RK3588
Misconfigured `PHP_GRF_PCIESEL` values are causing bifurcation issues,
for example on the FriendlyElec CM3588 NAS board which uses bifurcation
on both PCIe PCIe ports (all four lanes) to enable four M.2 NVMe
sockets. Without this fix, NVMe devices do not get recognized.

Correct the `PHP_GRF_PCIESEL` register configuration and simplify the
bifurcation logic, enabling proper PCIe bifurcation based on the
data-lanes property.

This fix is adapted from the upstream Linux commit by Michal Tomek:
f8020dfb311d ("phy: rockchip-snps-pcie3: fix bifurcation on rk3588")

Fixes: 50e54e8067 ("phy: rockchip: snps-pcie3: Add support for RK3588")
Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-07-17 14:48:18 +08:00
Sebastian Kropatsch
b962b490b7 phy: rockchip: snps-pcie3: Fix "rockchip" spelling
Several identifiers use "rochchip" instead of "rockchip".
Fix this by replacing every instance of "rochchip" with "rockchip".

Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-07-17 14:48:18 +08:00
Sebastian Kropatsch
f9cbd2d7b6 phy: rockchip: naneng-combphy: Fix "rockchip" spelling
Replace "rochchip" by "rockchip" in two instances.

Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-07-17 14:48:18 +08:00
Jagan Teki
35214b99eb phy: rockchip: inno-hdmi: Fix missing readl base addr
inno_poll passes the reg offset that is used by readl_poll_sleep_timeout
without any base addr.

Fix it.

Bug:
inno_hdmi_phy phy@ff430000: Pre-PLL locking failed
inno_hdmi_phy phy@ff430000: PHY: Failed to power on phy@ff430000: -110.
failed to power on phy (ret=-110)
inno_hdmi_phy phy@ff430000: Pre-PLL locking failed
inno_hdmi_phy phy@ff430000: PHY: Failed to power on phy@ff430000: -110.
failed to power on phy (ret=-110)

Fixes: aa22711846 ("phy: rockchip: Add Rockchip INNO HDMI PHY driver")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-07-17 14:48:18 +08:00
Tom Rini
475aa8345a Merge patch series "mediatek: cumulative trivial fix for OF_UPSTREAM support"
Christian Marangi <ansuelsmth@gmail.com> says:

This is an initial series that have all the initial trivial
fixes required for usage of OF_UPSTREAM for the mediatek SoC

This also contains the pcie-gen3 driver and the required tphy
support driver to make it work.

Subsequent series will follow with conversion of the mtk-clk
to permit usage of OF_UPSTREAM and upstream clk ID.

MT7981, MT7986 and MT7988 migration to upstream clock ID
is complete and working on MT7623.

Series CI tested with PR: https://github.com/u-boot/u-boot/pull/590
2024-07-08 11:56:59 -06:00
Christian Marangi
d4a489c1b2 phy: phy-mtk-tphy: add support for phy type switch
Add support for PHY type switch via the mediatek topmisc syscon.

This is needed on mt7981 to make the PCIe correctly work and display
LinkUp.

Follow the same implementation done on Linux kernel with the usage of
the mediatek,syscon-type property.

Example:

u3port0: usb-phy@11e10700 {
	reg = <0x11e10700 0x900>;
	clocks = <&topckgen CK_TOP_USB3_PHY_SEL>;
	clock-names = "ref";
	#phy-cells = <1>;
	mediatek,syscon-type = <&topmisc 0x218 0>;
	status = "okay";
};

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-07-08 11:45:50 -06:00
Neil Armstrong
affb461d9a phy: meson-gxl-usb2: remove phy_meson_gxl_usb2_set_mode
Remove the public phy_meson_gxl_usb2_set_mode and move
the implementation in the the set_mode callback.

Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20240620-u-boot-usb-gxl-phy-set-mode-v2-3-b81c027bc02c@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-06-25 15:25:10 +02:00
Neil Armstrong
e7265f62aa phy: meson-gxl-usb2: add set_mode callback
Implement set_mode callback by calling the current public
function, use a temporary function name that will be removed
when the public phy_meson_gxl_usb2_set_mode is finally removed
in a following change.

Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20240620-u-boot-usb-gxl-phy-set-mode-v2-1-b81c027bc02c@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-06-25 15:25:10 +02:00
Tom Rini
03de305ec4 Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-20 13:35:03 -06:00
Tom Rini
d4781422d1 Merge tag 'v2024.07-rc3' into next
Prepare v2024.07-rc3
2024-05-20 10:16:33 -06:00
Tom Rini
d678a59d2d Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d, reversing
changes made to 2ee6f3a5f7.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19 08:16:36 -06:00
Jim Liu
a4247055d1 phy: Use dt-bindig definations for npcm usb phy
Use dt-binding definations for the phy switch connection.
It declares the target usb controller it is connected to.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2024-05-17 12:53:17 -06:00
Tom Rini
c8ffd1356d Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"
Roger Quadros <rogerq@kernel.org> says:

Sync AM62 device tree files with Linux v6.9 and
add in the missing bits in -u-boot.dtsi to get CPSW
Ethernet working.

CI testing: https://github.com/u-boot/u-boot/pull/534
2024-05-13 09:15:51 -06:00
Tom Rini
5323767510 phy: Remove <common.h> and add needed includes
Remove <common.h> from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07 08:00:56 -06:00
Jonas Karlman
20a873a587 phy: rockchip: usbdp: Adopt driver to work with upstream DT
The upstream DT binding added in linux-phy next commit a75d8056e9fe
("dt-bindings: phy: add rockchip usbdp combo phy document") does not
define subnodes for the type of PHY, instead it is expected that phandle
args are used for setting the type of the PHY.

  phys = <&usbdp_phy0 PHY_TYPE_USB3>

Adopt the usbdp phy driver to work with upstream DT binding targeted for
Linux kernel v6.10.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-05-07 15:56:10 +08:00
Jonas Karlman
751ccceeed phy: rockchip: usbdp: Drop rockchip_u3phy_uboot_init()
Remove the rockchip_u3phy_uboot_init() function, it has no caller and is
not needed with proper driver model use.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-05-07 15:56:10 +08:00
Jonas Karlman
1a0bc25ccf phy: rockchip: usbdp: Find phy-id from the io address
The upstream Linux kernel driver find the phy-id from the io address.

Change to use a similar method as the U-Boot inno-usb2 phy driver and
the Linux kernel driver to set correct phy-id.

This is based on the linux-phy next commit 2f70bbddeb45 ("phy: rockchip:
add usbdp combo phy driver").

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-05-07 15:56:10 +08:00
Jonas Karlman
0ae7475f87 phy: rockchip-inno-usb2: Add support for RK3308
Add clkout_ctl and phy_sus regs to support USB2PHY for RK3308.

Based on linux commit 31f840e7ff3e ("phy: phy-rockchip-inno-usb2: add
support for RK3308 USB phy").

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26 15:47:03 +08:00
Caleb Connolly
82a99b3ab8 phy: qcom: snps-femto-v2: drop clocks
There is a clock associated with this phy, but it's always from the
rpmhcc and isn't actually needed for the hardware to work.

Drop all the clock handling from the driver.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23 13:29:29 +02:00
Neil Armstrong
6947939b62 phy: qcom: add Synopsys eUSB2 PHY driver
Add a driver for the new Synopsys eUSB2 PHY found in the SM8550
and SM8650 SoCs.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23 13:28:56 +02:00
Jagan Teki
aa22711846 phy: rockchip: Add Rockchip INNO HDMI PHY driver
Add Rockchip INNO HDMI PHY driver for RK3328.

Reference from linux-next phy-rockchip-inno-hdmi driver.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21 09:07:00 +02:00
Bhupesh Sharma
968f512e6c phy: qcom: Add SNPS femto v2 USB HS phy
Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy"
driver, notable the SM8250 SoC which will gain U-Boot support in
upcoming patches.

Introduce a driver based on the Linux driver.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[code cleanup, align symbol names with Linux, switch to clk/reset_bulk APIs]
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-04 17:46:46 +02:00
Bhupesh Sharma
8b133fc19c phy: qcom: add Qualcomm QUSB2 USB PHY driver
The Snapdragon 845 and several other Qualcomm SoCs feature this
USB high-speed phy. Add a driver for it based on the Linux driver, with
support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain
support in U-Boot in future patches.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[code cleanup, switch to clk_bulk]
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-04 17:46:46 +02:00
Sumit Garg
c214ebce09 phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.

Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy: Explicitly include correct DT
includes").

Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2024-03-24 13:35:59 -03:00
Jonas Karlman
b055c8952c phy: rockchip-inno-usb2: Limit changes made to regs
The USB2PHY regs already contain working default reset values for RK3328
and RK35xx as evidenced by the fact that this driver never has changed a
single value for these SoCs.

Reduce to only configure utmi_suspend_n and utmi_sel bits similar to
what is currently done on RK3399. Also add missing clkout_ctl for RK3588.

When enabled utmi_suspend_n is changed to normal mode and utmi_sel to
use otg/host controller utmi interface to phy. When disabled
utmi_suspend_n is changed to suspend mode and utmi_sel to use GRF utmi
interface to phy.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2024-03-14 11:48:40 +08:00
Jonas Karlman
803fbdfd1c phy: rockchip-inno-usb2: Write to correct GRF
On RK3399 the USB2PHY regs are located in the common GRF, remaining SoCs
that is supported by this driver have the USB2PHY regs in a different
GRF.

When support for RK356x, RK3588 and RK3328 was added this driver was
never updated to use correct GRF and have instead incorrectly written
to wrong GRF for these SoCs.

The default reset values for the USB2PHY have made USB mostly working
even when wrong GRF was used, however, following have been observed:

  scanning bus usb@fd840000 for devices...
  ERROR:  USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
  not provide a handshake (OUT) (5)
  ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
  not provide a handshake (OUT) (5)
  unable to get device descriptor (error=-1)

Fix this by using a regmap from rockchip,usbgrf prop and fall back to
getting a regmap for parent udevice instead of always getting the
common GRF.

Also protect against accidental clear of bit 0 in a reg with offset 0,
only bind driver to enabled otg/host-ports and remove unused headers.

Fixes: 3da15f0b49 ("phy: rockchip-inno-usb2: Add USB2 PHY for rk3568")
Fixes: cdf9010f6e ("phy: rockchip-inno-usb2: add initial support for rk3588 PHY")
Fixes: 9aa93d8403 ("phy: rockchip-inno-usb2: Add USB2 PHY for RK3328")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-03-14 11:48:40 +08:00
Caleb Connolly
c744e63089 board: dragonboard410c: upstream DT compat
Use the root compatible strings from upstream Linux, add missing
'#clock-cells' property to the gcc node.

Adjust some of the msm8916/apq8016 drivers to use the correct upstream
compatible properties and DT bindings.

This prepares us to switch to upstream DT in a future patch.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-03-01 14:44:37 +00:00
Sean Anderson
c9309f40a6 treewide: Remove clk_free
This function is a no-op. Remove it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
2024-01-29 22:35:02 -05:00
Chunfeng Yun
4f6dd25800 phy: phy-mtk-tphy: add properties for phy tuning
Add properties to improve eye diagram which sometimes need adjust
some parameters of u2phy;
Add a property to tune disconnect threshold;

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2024-01-11 21:19:25 -05:00
Fabio Estevam
7e3d6ec9bf phy: phy-imx8mq-usb: Remove .exit operation
Currently, when running "ums 0 mmc 2" and breaking it via
CTRL + C, the following message is seen:

u-boot=> ums 0 mmc 1
UMS: LUN 0, dev mmc 1, hwpart 0, sector 0x0, count 0x1dacc00
CTRL+C - Operation aborted
clk usb_phy_root_clk already disabled

The USB PHY clock is disabled twice: first it gets disabled
inside imx8mq_usb_phy_power_off(), then it is disabled again
inside imx8mq_usb_phy_exit().

Let the USB PHY clock be disabled only once inside
imx8mq_usb_phy_power_off() by removing the .exit operation.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-13 09:52:53 -03:00
Tom Rini
dca7a8958f Merge tag 'v2024.01-rc3' into next
Prepare v2024.01-rc3
2023-11-20 09:19:50 -05:00
Igor Prusov
13248d66ae treewide: use linux/time.h for time conversion defines
Now that we have time conversion defines from in time.h there is no need
for each driver to define their own version.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni
Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-11-16 18:59:58 -05:00
Nishanth Menon
a94a4071d4 tree-wide: Replace http:// link with https:// link for ti.com
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-10 11:01:50 -05:00
Guillaume La Roque
f699cb1dd5 phy: meson-g12a-usb2: fix ret check on power_domain_get
Patch which add A1 SoC support create a regression on khadas vim3/vim3l
boards when we try to use fastboot command:

  => fastboot usb 0
  failed to get power domain
  failed to get power domain
  No USB device found
  USB init failed: -19

Add ENOENT check on ret in probe function.

Fixes: 5533c883ce ("phy: support Amlogic A1 family")

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on vim3
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231017185725.809524-1-glaroque@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-18 09:45:48 +02:00
Tom Rini
2e1577e836 Merge tag 'u-boot-amlogic-20231015' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- add Amlogic A1 clock driver
- add Amlogic A1 reset support
- add USB Device support for Amlogic A1
- enable RNG on Amlogic A1 & Amlogic S4
- move Amlogic Secure Monitor to standalone driver
2023-10-16 09:09:54 -04:00
Matthias Schiffer
5fecea171d treewide: use dev_read_addr_*_ptr() where appropriate
A follow-up to commit 842fb5de42
("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer")
and commit 320a1938b6
("drivers: use devfdt_get_addr_index_ptr when cast to pointer").

In addition to using the *_ptr variants of these functions where the
address is cast to a pointer, this also changes devfdt_get_addr_*() to
dev_read_addr_*() in a few places. Some variable and field types are
changed from fdt_addr_t or phys_addr_t to void* where the cast was
happening later.

This patch fixes a number of compile warnings when building a 32bit
U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error
handling where the return value of dev_read_addr() etc. was checked for
NULL instead of FDT_ADDR_T_NONE.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-13 14:01:42 -06:00
Alexey Romanov
5533c883ce phy: support Amlogic A1 family
Setting G12A and A1 is similar, so we can use G12A phy
driver with little changes.

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231005085434.74755-6-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-12 13:39:41 +02:00
Alexey Romanov
80f45c3b36 phy: move clk enable/disable in init/exit
It is better to place clk_enable() in phy_meson_g12a_usb2_init()
and clk_disable() in phy_meson_g12a_usb2_exit().

For more detailed information, please see comments in the review of
a similar driver in the Linux Kernel:

https://lore.kernel.org/all/CAFBinCCEhobbyKHuKDWzTYCQWgNT1-e8=7hMhq1mvT6CuEOjGw@mail.gmail.com/

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231005085434.74755-5-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-12 13:39:41 +02:00