Tom Rini
03de305ec4
Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"
...
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se >
Signed-off-by: Tom Rini <trini@konsulko.com >
2024-05-20 13:35:03 -06:00
Tom Rini
d678a59d2d
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d2ee6f3a5f7jonas@kwiboo.se >
Signed-off-by: Tom Rini <trini@konsulko.com >
2024-05-19 08:16:36 -06:00
Tom Rini
5323767510
phy: Remove <common.h> and add needed includes
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Remove <common.h> from this driver directory and when needed
add missing include files directly.
Signed-off-by: Tom Rini <trini@konsulko.com >
2024-05-07 08:00:56 -06:00
Ashok Reddy Soma
e9869f474c
phy: zynqmp: Increase timeout value to 10ms
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Observing psgtr pll timeouts with some usb hubs and devices behind it.
Increase timeout to 10ms to take care of it.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com >
Link: https://lore.kernel.org/r/20220510131234.2650-1-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com >
2022-05-18 13:17:54 +02:00
Michal Simek
462f76bc00
phy: zynqmp: Add support for sata and DP phy initialization
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DP is untested but just c&p from Linux driver. Sata is tested on kv260-revA
board which has SATA connector populated.
Signed-off-by: Michal Simek <michal.simek@xilinx.com >
Link: https://lore.kernel.org/r/d231610160e76a2ad1b4a163e0e8db0ddc4733e2.1644226590.git.michal.simek@xilinx.com
2022-02-15 13:04:28 +01:00
Michal Simek
1d78d68349
phy: zynqmp: Add serdes/psgtr driver
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Add PSGTR driver for Xilinx ZynqMP.
The most of configurations are taken from Linux kernel psgtr driver.
USB3.0 and SGMII configurations are tested on SOM. In SGMII case also
IOU_SLCR reg is updated to get proper clock setup and signal detection
configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com >
Reviewed-by: Simon Glass <sjg@chromium.org >
Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com
2022-01-12 10:41:46 +01:00
