3 Commits

Author	SHA1	Message	Date
Melin Tomas	d3826fb052	xilinx_xiic: Fix transfer initialisation ... Prior to starting a new transfer, conditionally wait for bus to not be busy. Reinitialise controller as otherwise operation is not stable. For reference, see linux kernel commit 9656eeebf3f1 ("i2c: Revert i2c: xiic: Do not reset controller before every transfer") hs: Fixed DOS line endings added missing '\n' Fixed git commit description style Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>	2019-07-09 07:02:11 +02:00
Melin Tomas	5324e8ef6c	xilinx_xiic: Fix fill tx fifo loop ... Comparison should be against the actual message length, not loop index. len is used for stopping while loop, pos is position in message. stop should be sent when entire message is sent, not when len and pos meet. hs: fixed DOS line endings Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>	2019-07-09 07:02:11 +02:00
Marek Vasut	ad827a500b	i2c: xiic: Add Xilinx AXI I2C driver ... Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver. This driver is stripped of all the IRQ handling and uses pure polling, yet tries to retain most of the structure of the Linux driver to make backporting of fixes easy. Note that the IP has a known limitation on 255 bytes read and write, according to xilinx this is still being worked on [1]. [1] https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-I2C-Master-Reading-multiple-bytes-from-I2C-slave/m-p/854419/highlight/true#M39387 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Michal Simek <monstr@monstr.eu> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>	2019-01-15 09:04:49 +01:00