0be402375d
Use content of EEPROM to detect the actual RAM size and adjust DDR timings, size and banks accordingly. Also enable the SoM detection per default in the defconfigs. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Tested-by: John Ma <jma@phytec.com>
207 lines
4.4 KiB
C
207 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2024 PHYTEC Messtechnik GmbH
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* Author: Wadim Egorov <w.egorov@phytec.de>
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*/
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#ifndef PHYCORE_DDR_DATA
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#define PHYCORE_DDR_DATA
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#include "../common/k3/k3_ddrss_patch.h"
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/* 1 GB variant delta */
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struct ddr_reg ddr_1gb_ctl_regs[] = {
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{ 55, 0x0400DB60 },
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{ 58, 0x0400DB60 },
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{ 61, 0x0400DB60 },
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{ 73, 0x00001860 },
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{ 75, 0x00001860 },
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{ 77, 0x00001860 },
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{ 119, 0x00061800 },
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{ 120, 0x00061800 },
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{ 121, 0x00061800 },
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{ 122, 0x00061800 },
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{ 123, 0x00061800 },
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{ 125, 0x0000AAA0 },
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{ 126, 0x00061800 },
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{ 127, 0x00061800 },
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{ 128, 0x00061800 },
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{ 129, 0x00061800 },
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{ 130, 0x00061800 },
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{ 132, 0x0000AAA0 },
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{ 133, 0x00061800 },
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{ 134, 0x00061800 },
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{ 135, 0x00061800 },
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{ 136, 0x00061800 },
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{ 137, 0x00061800 },
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{ 139, 0x0000AAA0 },
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{ 206, 0x00000000 },
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{ 209, 0x00000000 },
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{ 212, 0x00000000 },
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{ 215, 0x00000000 },
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{ 218, 0x00000000 },
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{ 221, 0x00000000 },
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{ 230, 0x00000000 },
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{ 231, 0x00000000 },
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{ 232, 0x00000000 },
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{ 233, 0x00000000 },
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{ 234, 0x00000000 },
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{ 235, 0x00000000 },
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{ 316, 0x01010000 },
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{ 318, 0x3FFF0000 },
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{ 327, 0x00000C01 },
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{ 328, 0x00000000 },
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{ 385, 0x000030C0 },
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{ 390, 0x0000DB60 },
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{ 391, 0x0001E780 },
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{ 394, 0x000030C0 },
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{ 399, 0x0000DB60 },
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{ 400, 0x0001E780 },
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{ 403, 0x000030C0 },
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{ 408, 0x0000DB60 },
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{ 409, 0x0001E780 }
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};
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struct ddr_reg ddr_1gb_pi_regs[] = {
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{ 77, 0x04000100 },
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{ 176, 0x00001860 },
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{ 178, 0x00001860 },
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{ 180, 0x04001860 },
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{ 233, 0x0000C570 },
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{ 238, 0x0000C570 },
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{ 243, 0x0000C570 },
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{ 247, 0x000030C0 },
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{ 248, 0x0001E780 },
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{ 249, 0x000030C0 },
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{ 250, 0x0001E780 },
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{ 251, 0x000030C0 },
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{ 252, 0x0001E780 },
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{ 299, 0x00000000 },
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{ 301, 0x00000000 },
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{ 307, 0x00000000 },
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{ 309, 0x00000000 },
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{ 315, 0x00000000 },
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{ 317, 0x00000000 },
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{ 323, 0x00000000 },
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{ 325, 0x00000000 },
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{ 331, 0x00000000 },
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{ 333, 0x00000000 },
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{ 339, 0x00000000 },
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{ 341, 0x00000000 }
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};
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struct ddr_reg ddr_1gb_phy_regs[] = {
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{ 1371, 0x0001F7C2 },
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};
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/* 4 GB variant delta */
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struct ddr_reg ddr_4gb_ctl_regs[] = {
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{ 55, 0x0400DB60 },
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{ 58, 0x0400DB60 },
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{ 61, 0x0400DB60 },
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{ 73, 0x00001860 },
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{ 75, 0x00001860 },
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{ 77, 0x00001860 },
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{ 119, 0x00061800 },
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{ 120, 0x00061800 },
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{ 121, 0x00061800 },
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{ 122, 0x00061800 },
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{ 123, 0x00061800 },
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{ 125, 0x0000AAA0 },
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{ 126, 0x00061800 },
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{ 127, 0x00061800 },
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{ 128, 0x00061800 },
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{ 129, 0x00061800 },
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{ 130, 0x00061800 },
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{ 132, 0x0000AAA0 },
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{ 133, 0x00061800 },
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{ 134, 0x00061800 },
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{ 135, 0x00061800 },
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{ 136, 0x00061800 },
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{ 137, 0x00061800 },
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{ 139, 0x0000AAA0 },
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{ 206, 0x00000000 },
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{ 209, 0x00000000 },
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{ 212, 0x00000000 },
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{ 215, 0x00000000 },
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{ 218, 0x00000000 },
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{ 221, 0x00000000 },
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{ 230, 0x00000000 },
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{ 231, 0x00000000 },
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{ 232, 0x00000000 },
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{ 233, 0x00000000 },
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{ 234, 0x00000000 },
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{ 235, 0x00000000 },
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{ 316, 0x00000000 },
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{ 318, 0x7FFF0000 },
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{ 327, 0x01000C01 },
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{ 328, 0x00000001 },
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{ 385, 0x000030C0 },
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{ 390, 0x0000DB60 },
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{ 391, 0x0001E780 },
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{ 394, 0x000030C0 },
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{ 399, 0x0000DB60 },
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{ 400, 0x0001E780 },
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{ 403, 0x000030C0 },
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{ 408, 0x0000DB60 },
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{ 409, 0x0001E780 }
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};
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struct ddr_reg ddr_4gb_pi_regs[] = {
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{ 77, 0x04000000 },
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{ 176, 0x00001860 },
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{ 178, 0x00001860 },
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{ 180, 0x04001860 },
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{ 233, 0x0000C570 },
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{ 238, 0x0000C570 },
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{ 243, 0x0000C570 },
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{ 247, 0x000030C0 },
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{ 248, 0x0001E780 },
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{ 249, 0x000030C0 },
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{ 250, 0x0001E780 },
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{ 251, 0x000030C0 },
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{ 252, 0x0001E780 },
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{ 299, 0x00000000 },
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{ 301, 0x00000000 },
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{ 307, 0x00000000 },
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{ 309, 0x00000000 },
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{ 315, 0x00000000 },
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{ 317, 0x00000000 },
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{ 323, 0x00000000 },
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{ 325, 0x00000000 },
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{ 331, 0x00000000 },
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{ 333, 0x00000000 },
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{ 339, 0x00000000 },
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{ 341, 0x00000000 }
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};
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struct ddr_reg ddr_4gb_phy_regs[] = {
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{ 1371, 0x0001F7C2 },
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};
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enum {
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PHYCORE_1GB,
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PHYCORE_4GB,
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};
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struct ddrss phycore_ddrss_data[] = {
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[PHYCORE_1GB] = {
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.ctl_regs = &ddr_1gb_ctl_regs[0],
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.ctl_regs_num = ARRAY_SIZE(ddr_1gb_ctl_regs),
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.pi_regs = &ddr_1gb_pi_regs[0],
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.pi_regs_num = ARRAY_SIZE(ddr_1gb_pi_regs),
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.phy_regs = &ddr_1gb_phy_regs[0],
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.phy_regs_num = ARRAY_SIZE(ddr_1gb_phy_regs),
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},
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[PHYCORE_4GB] = {
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.ctl_regs = &ddr_4gb_ctl_regs[0],
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.ctl_regs_num = ARRAY_SIZE(ddr_4gb_ctl_regs),
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.pi_regs = &ddr_4gb_pi_regs[0],
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.pi_regs_num = ARRAY_SIZE(ddr_4gb_pi_regs),
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.phy_regs = &ddr_4gb_phy_regs[0],
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.phy_regs_num = ARRAY_SIZE(ddr_4gb_phy_regs),
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},
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};
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#endif /* PHYCORE_DDR_DATA */
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