Stefan Roese a5f50e0114 mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues ...

It has been noticed, that sometimes the d-cache is not in a
"clean-state" when U-Boot is running on MT7688. This was detected when
using the ethernet driver (which uses d-cache) and a TFTP command does
not complete. Flushing the complete d-cache (again?) here seems to fix
this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

2018-12-19 15:23:01 +01:00

..

cpu.c

mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues

2018-12-19 15:23:01 +01:00

ddr_calibrate.c

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Kconfig

mips: mt76xx: gardena-smart-gateway: Add board_late_init() to set LED def state

2018-11-18 16:02:23 +01:00

lowlevel_init.S

mips: mt76xx: lowlevel_init.S: Add missing memory controller reset in DDR init

2018-11-18 16:02:22 +01:00

Makefile

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mt76xx.h

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