69a5616f06
These header files presumably duplicate things already in the U-Boot devicetree. For now, bring them in to get the ASL code and ACPI table code to compile. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Matthias Brugger <mbrugger@suse.com> Cc: Matthias Brugger <mbrugger@suse.com> Cc: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Rini <trini@konsulko.com>
128 lines
5.5 KiB
C
128 lines
5.5 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause-Patent */
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/**
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*
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* Copyright (c) 2019, ARM Limited. All rights reserved.
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* Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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*
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**/
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#ifndef __BCM2836_H__
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#define __BCM2836_H__
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/*
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* Both "core" and SoC perpherals (1M each).
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*/
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#define BCM2836_SOC_REGISTERS 0xfe000000
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#define BCM2836_SOC_REGISTER_LENGTH 0x02000000
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/*
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* Offset between the CPU's view and the VC's view of system memory.
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*/
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#define BCM2836_DMA_DEVICE_OFFSET 0xc0000000
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/* watchdog constants */
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#define BCM2836_WDOG_OFFSET 0x00100000
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#define BCM2836_WDOG_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_WDOG_OFFSET)
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#define BCM2836_WDOG_PASSWORD 0x5a000000
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#define BCM2836_WDOG_RSTC_OFFSET 0x0000001c
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#define BCM2836_WDOG_WDOG_OFFSET 0x00000024
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#define BCM2836_WDOG_RSTC_WRCFG_MASK 0x00000030
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#define BCM2836_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020
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/* clock manager constants */
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#define BCM2836_CM_OFFSET 0x00101000
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#define BCM2836_CM_BASE (BCM2836_SOC_REGISTERS + BCM2836_CM_OFFSET)
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#define BCM2836_CM_GEN_CLOCK_CONTROL 0x0000
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#define BCM2836_CM_GEN_CLOCK_DIVISOR 0x0004
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#define BCM2836_CM_VPU_CLOCK_CONTROL 0x0008
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#define BCM2836_CM_VPU_CLOCK_DIVISOR 0x000c
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#define BCM2836_CM_SYSTEM_CLOCK_CONTROL 0x0010
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#define BCM2836_CM_SYSTEM_CLOCK_DIVISOR 0x0014
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#define BCM2836_CM_H264_CLOCK_CONTROL 0x0028
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#define BCM2836_CM_H264_CLOCK_DIVISOR 0x002c
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#define BCM2836_CM_PWM_CLOCK_CONTROL 0x00a0
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#define BCM2836_CM_PWM_CLOCK_DIVISOR 0x00a4
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#define BCM2836_CM_UART_CLOCK_CONTROL 0x00f0
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#define BCM2836_CM_UART_CLOCK_DIVISOR 0x00f4
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#define BCM2836_CM_SDC_CLOCK_CONTROL 0x01a8
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#define BCM2836_CM_SDC_CLOCK_DIVISOR 0x01ac
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#define BCM2836_CM_ARM_CLOCK_CONTROL 0x01b0
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#define BCM2836_CM_ARM_CLOCK_DIVISOR 0x01b4
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#define BCM2836_CM_EMMC_CLOCK_CONTROL 0x01c0
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#define BCM2836_CM_EMMC_CLOCK_DIVISOR 0x01c4
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/* mailbox interface constants */
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#define BCM2836_MBOX_OFFSET 0x0000b880
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#define BCM2836_MBOX_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MBOX_OFFSET)
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#define BCM2836_MBOX_LENGTH 0x00000024
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#define BCM2836_MBOX_READ_OFFSET 0x00000000
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#define BCM2836_MBOX_STATUS_OFFSET 0x00000018
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#define BCM2836_MBOX_CONFIG_OFFSET 0x0000001c
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#define BCM2836_MBOX_WRITE_OFFSET 0x00000020
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#define BCM2836_MBOX_STATUS_FULL 0x1f
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#define BCM2836_MBOX_STATUS_EMPTY 0x1e
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#define BCM2836_MBOX_NUM_CHANNELS 16
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/* interrupt controller constants */
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#define BCM2836_INTC_TIMER_CONTROL_OFFSET 0x00000040
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#define BCM2836_INTC_TIMER_PENDING_OFFSET 0x00000060
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/* usb constants */
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#define BCM2836_USB_OFFSET 0x00980000
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#define BCM2836_USB_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_USB_OFFSET)
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#define BCM2836_USB_LENGTH 0x00010000
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/* serial based protocol constants */
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#define BCM2836_PL011_UART_OFFSET 0x00201000
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#define BCM2836_PL011_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PL011_UART_OFFSET)
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#define BCM2836_PL011_UART_LENGTH 0x00001000
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#define BCM2836_MINI_UART_OFFSET 0x00215000
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#define BCM2836_MINI_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MINI_UART_OFFSET)
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#define BCM2836_MINI_UART_LENGTH 0x00000070
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#define BCM2836_I2C0_OFFSET 0x00205000
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#define BCM2836_I2C0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C0_OFFSET)
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#define BCM2836_I2C0_LENGTH 0x00000020
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#define BCM2836_I2C1_OFFSET 0x00804000
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#define BCM2836_I2C1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C1_OFFSET)
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#define BCM2836_I2C1_LENGTH 0x00000020
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#define BCM2836_I2C2_OFFSET 0x00805000
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#define BCM2836_I2C2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C2_OFFSET)
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#define BCM2836_I2C2_LENGTH 0x00000020
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#define BCM2836_SPI0_OFFSET 0x00204000
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#define BCM2836_SPI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI0_OFFSET)
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#define BCM2836_SPI0_LENGTH 0x00000020
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#define BCM2836_SPI1_OFFSET 0x00215080
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#define BCM2836_SPI1_LENGTH 0x00000040
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#define BCM2836_SPI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI1_OFFSET)
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#define BCM2836_SPI2_OFFSET 0x002150C0
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#define BCM2836_SPI2_LENGTH 0x00000040
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#define BCM2836_SPI2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI2_OFFSET)
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#define BCM2836_SYSTEM_TIMER_OFFSET 0x00003000
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#define BCM2836_SYSTEM_TIMER_LENGTH 0x00000020
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#define BCM2836_SYSTEM_TIMER_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SYSTEM_TIMER_OFFSET)
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/* dma constants */
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#define BCM2836_DMA0_OFFSET 0x00007000
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#define BCM2836_DMA0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA0_OFFSET)
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#define BCM2836_DMA15_OFFSET 0x00E05000
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#define BCM2836_DMA15_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA15_OFFSET)
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#define BCM2836_DMA_CTRL_OFFSET 0x00007FE0
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#define BCM2836_DMA_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA_CTRL_OFFSET)
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#define BCM2836_DMA_CHANNEL_LENGTH 0x00000100
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#endif /*__BCM2836_H__ */
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