7d8c3fa26c
SPL_TEXT_BASE is used as the load address for the main domain SPL on k3 platforms. Since the config value is the same for every board, this patch sets the value 0x80080000 as default for all 64-bit ARCH_K3, 0x43c00000 as default for the R5 cores and deletes the instances of SPL_TEXT_BASE in individual defconfigs. Signed-off-by: Anshul Dalal <anshuld@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
129 lines
3.3 KiB
Plaintext
129 lines
3.3 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_K3=y
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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CONFIG_SPL_GPIO=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_SOC_K3_AM625=y
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CONFIG_TARGET_AM625_A53_BEAGLEPLAY=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-beagleplay"
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CONFIG_OF_LIBFDT_OVERLAY=y
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CONFIG_DM_RESET=y
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CONFIG_SPL_MMC=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_STACK_R_ADDR=0x82000000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x80c80000
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CONFIG_SPL_BSS_MAX_SIZE=0x80000
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_SIZE_LIMIT=0x40000
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CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
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CONFIG_SPL_FS_FAT=y
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CONFIG_SPL_LIBDISK_SUPPORT=y
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# CONFIG_PSCI_RESET is not set
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
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CONFIG_BOOTSTD_FULL=y
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CONFIG_AUTOBOOT_KEYED=y
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CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
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CONFIG_AUTOBOOT_DELAY_STR="d"
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CONFIG_AUTOBOOT_STOP_STR=" "
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CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb;run set_led_state_fail_load"
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CONFIG_BOARD_LATE_INIT=y
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CONFIG_SPL_MAX_SIZE=0x58000
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CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
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CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
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CONFIG_SPL_I2C=y
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CONFIG_SPL_DM_MAILBOX=y
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CONFIG_SPL_POWER_DOMAIN=y
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CONFIG_SPL_YMODEM_SUPPORT=y
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CONFIG_CMD_BOOTEFI_SELFTEST=y
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CONFIG_CMD_NVEDIT_EFI=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPIO_READ=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_EFIDEBUG=y
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CONFIG_CMD_PMIC=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_UPSTREAM=y
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CONFIG_MULTI_DTB_FIT=y
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CONFIG_SPL_MULTI_DTB_FIT=y
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CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SPL_OF_TRANSLATE=y
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_CLK_TI_SCI=y
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CONFIG_DFU_MMC=y
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CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
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CONFIG_SYS_DFU_MAX_FILE_SIZE=0x180000
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CONFIG_DMA_CHANNELS=y
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CONFIG_TI_K3_NAVSS_UDMA=y
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CONFIG_TI_SCI_PROTOCOL=y
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CONFIG_DA8XX_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_OMAP24XX=y
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CONFIG_LED=y
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CONFIG_SPL_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_SPL_LED_GPIO=y
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CONFIG_DM_MAILBOX=y
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CONFIG_K3_SEC_PROXY=y
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CONFIG_MMC_IO_VOLTAGE=y
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CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ADMA=y
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CONFIG_SPL_MMC_SDHCI_ADMA=y
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CONFIG_MMC_SDHCI_AM654=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TI=y
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CONFIG_DM_ETH_PHY=y
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CONFIG_TI_AM65_CPSW_NUSS=y
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CONFIG_PHY=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_PINCTRL_SINGLE=y
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CONFIG_POWER_DOMAIN=y
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CONFIG_TI_SCI_POWER_DOMAIN=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_TPS65219=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_DM_REGULATOR_TPS65219=y
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CONFIG_K3_SYSTEM_CONTROLLER=y
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CONFIG_RESET_TI_SCI=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_EMULATION=y
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CONFIG_DM_SERIAL=y
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CONFIG_SOC_DEVICE=y
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CONFIG_SOC_DEVICE_TI_K3=y
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CONFIG_SOC_TI=y
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CONFIG_SYSRESET=y
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CONFIG_SPL_SYSRESET=y
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CONFIG_SYSRESET_TI_SCI=y
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CONFIG_EXT4_WRITE=y
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CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
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CONFIG_LZO=y
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CONFIG_EFI_SET_TIME=y
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#include <configs/k3_efi_capsule.config>
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#include <configs/am62x_a53_usbdfu.config>
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