3c72b81200
With DM_SERIAL in place, there is no need to setup the UART pins in the board code. The UART pins are setup via devicetree, thanks to DM. Remove the unneeded code. Signed-off-by: Fabio Estevam <festevam@denx.de>
158 lines
3.9 KiB
C
158 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* Copyright (C) 2013, 2014 TQ-Systems (ported SabreSD to TQMa6x)
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* Author: Markus Niebel <markus.niebel@tq-group.com>
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*/
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#include <init.h>
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#include <net.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <fsl_esdhc_imx.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <i2c.h>
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#include <micrel.h>
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#include <miiphy.h>
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#include <mmc.h>
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#include <netdev.h>
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#include "tqma6_bb.h"
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#if defined(CONFIG_TQMA6Q)
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#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
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#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
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#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
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#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
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#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
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#else
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#error "need to select module"
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#endif
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/* disable on die termination for RGMII */
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#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
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/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
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#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000
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/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
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#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
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static void mba6_setup_iomuxc_enet(void)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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/* clear gpr1[ENET_CLK_SEL] for externel clock */
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clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
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(void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
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__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
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(void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
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}
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int board_mmc_get_env_dev(int devno)
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{
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/*
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* This assumes that the baseboard registered
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* the boot device first ...
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* Note: SDHC3 == idx2
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*/
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return (2 == devno) ? 0 : 1;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/*
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* optimized pad skew values depends on CPU variant on the TQMa6x module:
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* CONFIG_TQMA6Q: i.MX6Q/D
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* CONFIG_TQMA6S: i.MX6S
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* CONFIG_TQMA6DL: i.MX6DL
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*/
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#if defined(CONFIG_TQMA6Q)
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#define MBA6X_KSZ9031_CTRL_SKEW 0x0032
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#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
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#define MBA6X_KSZ9031_RX_SKEW 0x3333
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#define MBA6X_KSZ9031_TX_SKEW 0x2036
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#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
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#define MBA6X_KSZ9031_CTRL_SKEW 0x0030
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#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
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#define MBA6X_KSZ9031_RX_SKEW 0x3333
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#define MBA6X_KSZ9031_TX_SKEW 0x2052
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#else
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#error
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#endif
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/* min rx/tx ctrl delay */
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ksz9031_phy_extended_write(phydev, 2,
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MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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MBA6X_KSZ9031_CTRL_SKEW);
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/* min rx delay */
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ksz9031_phy_extended_write(phydev, 2,
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MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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MBA6X_KSZ9031_RX_SKEW);
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/* max tx delay */
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ksz9031_phy_extended_write(phydev, 2,
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MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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MBA6X_KSZ9031_TX_SKEW);
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/* rx/tx clk skew */
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ksz9031_phy_extended_write(phydev, 2,
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MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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MBA6X_KSZ9031_CLK_SKEW);
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phydev->drv->config(phydev);
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return 0;
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}
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int tqma6_bb_board_early_init_f(void)
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{
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return 0;
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}
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int tqma6_bb_board_init(void)
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{
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mba6_setup_iomuxc_enet();
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return 0;
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}
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int tqma6_bb_board_late_init(void)
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{
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return 0;
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}
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const char *tqma6_bb_get_boardname(void)
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{
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return "MBa6x";
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}
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/*
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* Device Tree Support
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*/
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd)
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{
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/* TBD */
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}
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#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
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