1ae1e9c55e
The Cadence NAND is a configurable mtd raw block which supports multiple options for chipsets, clocking and reset structure, and feature list. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
99 lines
2.0 KiB
YAML
99 lines
2.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence NAND controller
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maintainers:
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- Dinesh Maniyam <dinesh.maniyam@intel.com>
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properties:
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compatible:
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enum:
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- cdns,nand
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reg-names:
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description: |
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There are two register regions:
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reg: register interface
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sdma: host data/command interface
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items:
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- const: reg
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- const: sdma
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reg:
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minItems: 2
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maxItems: 2
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interrupts:
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maxItems: 1
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clocks:
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description: |
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There is one controller core clock
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maxItems: 1
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resets:
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description: |
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There are two resets:
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controller core reset
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combo-phy register reset
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minItems: 1
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maxItems: 2
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cdns,board-delay-ps:
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description: |
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Estimated Board delay. The value includes the total
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round trip delay for the signals and is used for deciding on values
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associated with data read capture. The example formula for SDR mode is
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the following:
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board delay = RE#PAD delay + PCB trace to device + PCB trace from device
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+ DQ PAD delay
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enum:
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- 4830
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patternProperties:
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"^nand@[a-f0-9]$":
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type: object
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properties:
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compatible:
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const: cdns,nand
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reg:
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maxItems: 1
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label:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- cdns,board-delay-ps
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unevaluatedProperties: false
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examples:
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- |
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nand-controller@60000000 {
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compatible = "cdns,nand";
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reg = <0x60000000 0x10000>, <0x80000000 0x1000>;
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reg-names = "reg", "sdma";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk>;
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cdns,board-delay-ps = <4830>;
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interrupts = <2 0>;
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nand@0 {
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label = "nand-0";
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reg = <0>;
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};
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nand@1 {
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label = "nand-1";
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reg = <1>;
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};
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};
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