Bin Meng 16f53be076 riscv: Correct a comment in io.h ...

Replace NDS32 with RISC-V in the comments.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>

2023-04-20 20:45:08 +08:00

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arch-andes

riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

2023-02-17 19:07:48 +08:00

arch-fu540

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arch-fu740

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arch-generic

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arch-jh7110

riscv: cpu: jh7110: Add support for jh7110 SoC

2023-04-20 16:08:44 +08:00

asm.h

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barrier.h

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bitops.h

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byteorder.h

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cache.h

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config.h

Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig

2022-07-07 14:01:09 -04:00

csr.h

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dma-mapping.h

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encoding.h

global: Finish CONFIG -> CFG migration

2023-01-20 12:27:24 -05:00

global_data.h

riscv: global_data.h: Correct the comment for PLICSW

2023-02-17 19:07:48 +08:00

gpio.h

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io.h

riscv: Correct a comment in io.h

2023-04-20 20:45:08 +08:00

linkage.h

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posix_types.h

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processor.h

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ptrace.h

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sbi.h

riscv: provide missing base extension functions

2022-04-06 09:40:05 +08:00

sections.h

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setjmp.h

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smp.h

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spl.h

arch/riscv: add semihosting support for RISC-V

2022-12-08 15:15:58 +08:00

string.h

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syscon.h

riscv: Rename Andes PLIC to PLICSW

2022-11-03 13:27:56 +08:00

system.h

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types.h

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u-boot-riscv.h

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u-boot.h

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unaligned.h

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